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Searched refs:PORT_A (Results 1 – 25 of 35) sorted by relevance

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/drivers/gpu/drm/i915/display/
Dintel_display_device.c202 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C), /* DVO A/B/C */
337 ….__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) /* DP A, SDV…
359 ….__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SD…
373 ….__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SD…
408 ….__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E…
428 ….__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E…
468 ….__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E…
493 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C)
554 ….__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E…
560 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D),
[all …]
Dg4x_dp.c128 if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) { in intel_dp_prepare()
139 } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { in intel_dp_prepare()
284 if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) in g4x_dp_port_enabled()
286 else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) in g4x_dp_port_enabled()
348 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A; in intel_dp_get_config()
350 if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { in intel_dp_get_config()
391 if (port == PORT_A) { in intel_dp_get_config()
424 if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) || in intel_dp_link_down()
425 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) { in intel_dp_link_down()
444 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) { in intel_dp_link_down()
[all …]
Dvlv_dsi.c344 intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), GLK_MIPIIO_RESET_RELEASED, 0); in glk_dsi_enable_io()
383 intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), 0, GLK_MIPIIO_RESET_RELEASED); in glk_dsi_device_ready()
484 intel_de_rmw(dev_priv, MIPI_PORT_CTRL(PORT_A), 0, LP_OUTPUT_HOLD); in vlv_dsi_device_ready()
543 intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), GLK_MIPIIO_RESET_RELEASED, 0); in glk_dsi_disable_mipi_io()
573 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A); in vlv_dsi_clear_device_ready()
591 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) || port == PORT_A) && in vlv_dsi_clear_device_ready()
638 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) { in intel_dsi_port_enable()
993 *pipe = port == PORT_A ? PIPE_A : PIPE_B; in intel_dsi_get_hw_state()
1328 tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); in intel_dsi_prepare()
1330 intel_de_write(dev_priv, MIPI_CTRL(PORT_A), in intel_dsi_prepare()
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Dintel_ddi.c713 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) in intel_ddi_connector_get_hw_state()
780 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) { in intel_ddi_get_encoder_pipes()
1062 if (encoder->port == PORT_A && dig_port->max_lanes == 4) in skl_ddi_set_iboost()
1852 case PORT_A: in bxt_ddi_get_pll()
2662 is_mst && (port == PORT_A || port == PORT_E)); in hsw_ddi_pre_enable_dp()
2664 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); in hsw_ddi_pre_enable_dp()
2702 if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) && in hsw_ddi_pre_enable_dp()
3104 if (port == PORT_A && DISPLAY_VER(dev_priv) < 9) in intel_enable_ddi_dp()
3123 [PORT_A] = TRANSCODER_EDP, in gen9_chicken_trans_reg_by_port()
3132 if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E)) in gen9_chicken_trans_reg_by_port()
[all …]
Dintel_display_limits.h78 PORT_A = 0, enumerator
Dintel_bios.c1631 panel->vbt.dsi.bl_ports = BIT(PORT_A); in parse_dsi_backlight_ports()
1638 panel->vbt.dsi.bl_ports = BIT(PORT_A) | BIT(port_bc); in parse_dsi_backlight_ports()
1647 panel->vbt.dsi.cabc_ports = BIT(PORT_A); in parse_dsi_backlight_ports()
1655 BIT(PORT_A) | BIT(port_bc); in parse_dsi_backlight_ports()
2292 for (port = PORT_A; port < n_ports; port++) { in __dvo_port_to_port()
2313 [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 }, in dvo_port_to_port()
2328 [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 }, in dvo_port_to_port()
2339 [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 }, in dvo_port_to_port()
2348 [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 }, in dvo_port_to_port()
2386 return PORT_A; in dsi_dvo_port_to_port()
[all …]
Dicl_dsi.c92 if (port == PORT_A) in dsi_port_to_transcoder()
222 port = PORT_A; in icl_dsi_frame_update()
391 port == PORT_A ? in get_dsi_io_power_domains()
1375 port == PORT_A ? in gen11_dsi_disable_io_power()
1512 if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A))) in gen11_dsi_get_cmd_mode_config()
2026 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B); in icl_dsi_init()
Dintel_display.h131 case PORT_A: in port_identifier()
244 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)
Dintel_display_irq.c920 PORT_A : PORT_B; in gen11_dsi_te_interrupt_handler()
921 dsi_trans = (port == PORT_A) ? TRANSCODER_DSI_0 : TRANSCODER_DSI_1; in gen11_dsi_te_interrupt_handler()
952 port = (te_trigger & DSI1_TE) ? PORT_B : PORT_A; in gen11_dsi_te_interrupt_handler()
1270 port = PORT_A; in gen11_dsi_configure_te()
Dintel_combo_phy.c166 bool ddi_a_present = intel_bios_is_port_present(i915, PORT_A); in ehl_vbt_ddi_d_present()
Dintel_display_power.c2341 .port_start = PORT_A,
2357 .port_start = PORT_A,
2384 .port_start = PORT_A,
2411 .port_start = PORT_A,
Dintel_dpio_phy.c181 [DPIO_CH0] = { .port = PORT_A },
204 [DPIO_CH0] = { .port = PORT_A },
Dintel_dvo.c81 .port = PORT_A,
Dvlv_dsi_regs.h16 #define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */
Dintel_audio.c599 if (drm_WARN_ON(&i915->drm, port == PORT_A)) in ibx_audio_codec_disable()
635 if (drm_WARN_ON(&i915->drm, port == PORT_A)) in ibx_audio_codec_enable()
Dintel_dp.c402 encoder->port != PORT_A); in intel_dp_can_bigjoiner()
1323 if (DISPLAY_VER(dev_priv) == 11 && encoder->port != PORT_A && in intel_dp_source_supports_fec()
1945 if (DISPLAY_VER(dev_priv) < 12 && port == PORT_A) in intel_dp_port_has_audio()
2277 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A) in intel_dp_compute_config()
5358 if (DISPLAY_VER(dev_priv) < 9 && port == PORT_A) in _intel_dp_is_port_edp()
5384 if (port == PORT_A) in has_gamut_metadata_dip()
5403 if (!IS_G4X(dev_priv) && port != PORT_A) in intel_dp_add_properties()
Dvlv_dsi_pll.c191 if (intel_dsi->ports & (1 << PORT_A)) in vlv_dsi_pll_compute()
Dintel_pch_refclk.c513 if (encoder->port == PORT_A) in ilk_init_pch_refclk()
Dintel_pps.c1519 case PORT_A: in pps_init_registers()
1695 g4x_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe); in assert_pps_unlocked()
/drivers/gpu/drm/i915/gvt/
Ddisplay.c207 for (port = PORT_A; port <= PORT_C; port++) { in emulate_monitor_status_change()
267 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { in emulate_monitor_status_change()
273 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |= in emulate_monitor_status_change()
275 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &= in emulate_monitor_status_change()
278 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_A)) |= in emulate_monitor_status_change()
282 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= in emulate_monitor_status_change()
284 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &= in emulate_monitor_status_change()
487 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { in emulate_monitor_status_change()
494 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED; in emulate_monitor_status_change()
692 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { in intel_vgpu_emulate_hotplug()
Dmmio.c272 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &= in intel_vgpu_reset_mmio()
274 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |= in intel_vgpu_reset_mmio()
Dhandlers.c546 case PORT_A: in bxt_vgpu_get_dp_bitrate()
1159 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS))
2342 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write); in init_generic_mmio_info()
2348 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write); in init_generic_mmio_info()
2354 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write); in init_generic_mmio_info()
2758 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT, in init_bxt_mmio_info()
/drivers/staging/media/tegra-video/
Dcsi.h29 PORT_A = 0, enumerator
Dtegra210.c1016 val = ((portno & 1) == PORT_A) ? in tegra210_csi_port_start_streaming()
1109 val = ((portno & 1) == PORT_A) ? in tegra210_csi_port_stop_streaming()
/drivers/gpu/drm/i915/
Dintel_gvt_mmio_table.c482 MMIO_D(PORT_CLK_SEL(PORT_A)); in iterate_generic_mmio()
513 MMIO_D(DDI_BUF_CTL(PORT_A)); in iterate_generic_mmio()
518 MMIO_D(DP_TP_CTL(PORT_A)); in iterate_generic_mmio()
523 MMIO_D(DP_TP_STATUS(PORT_A)); in iterate_generic_mmio()
1125 MMIO_D(BXT_PHY_CTL(PORT_A)); in iterate_bxt_mmio()
1128 MMIO_D(BXT_PORT_PLL_ENABLE(PORT_A)); in iterate_bxt_mmio()

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