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Searched refs:PRIV_REG_INT_ENABLE (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/radeon/
Dcikd.h1335 # define PRIV_REG_INT_ENABLE (1 << 23) macro
1368 # define PRIV_REG_INT_ENABLE (1 << 23) macro
Dcik.c7039 cp_int_cntl |= PRIV_INSTR_INT_ENABLE | PRIV_REG_INT_ENABLE; in cik_irq_set()
/drivers/gpu/drm/amd/amdgpu/
Dgfx_v9_4_3.c2770 PRIV_REG_INT_ENABLE, in gfx_v9_4_3_set_priv_reg_fault_state()
Dgfx_v11_0.c5904 PRIV_REG_INT_ENABLE, in gfx_v11_0_set_priv_reg_fault_state()
Dgfx_v8_0.c6473 WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_REG_INT_ENABLE, in gfx_v8_0_set_priv_reg_fault_state()
Dgfx_v9_0.c5788 PRIV_REG_INT_ENABLE, in gfx_v9_0_set_priv_reg_fault_state()
Dgfx_v10_0.c8955 PRIV_REG_INT_ENABLE, in gfx_v10_0_set_priv_reg_fault_state()