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Searched refs:QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR (Results 1 – 3 of 3) sorted by relevance

/drivers/iommu/arm/arm-smmu/
Darm-smmu-qcom.h20 QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR, enumerator
Darm-smmu-qcom-debug.c41 ret = qcom_scm_io_readl(smmu->ioaddr + cfg->reg_offset[QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR], in qcom_smmu_tlb_sync_debug()
Darm-smmu-qcom.c478 [QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR] = 0x2670,