Home
last modified time | relevance | path

Searched refs:QSERDES_COM_PLL_CCTRL_MODE0 (Results 1 – 6 of 6) sorted by relevance

/drivers/phy/qualcomm/
Dphy-qcom-sgmii-eth.c29 #define QSERDES_COM_PLL_CCTRL_MODE0 (QSERDES_QMP_PLL + 0x84) macro
121 regmap_write(regmap, QSERDES_COM_PLL_CCTRL_MODE0, 0x36); in qcom_dwmac_sgmii_phy_init_1g()
209 regmap_write(regmap, QSERDES_COM_PLL_CCTRL_MODE0, 0x36); in qcom_dwmac_sgmii_phy_init_2p5g()
Dphy-qcom-qmp-qserdes-com.h51 #define QSERDES_COM_PLL_CCTRL_MODE0 0x090 macro
Dphy-qcom-qmp-usb.c159 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
241 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
315 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
943 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
Dphy-qcom-qmp-ufs.c137 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
205 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
Dphy-qcom-qmp-pcie-msm8996.c118 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
Dphy-qcom-qmp-pcie.c340 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),