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Searched refs:REG_A6XX_GMU_GMU2HOST_INTR_MASK (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/msm/adreno/
Da6xx_gmu.xml.h335 #define REG_A6XX_GMU_GMU2HOST_INTR_MASK 0x00005193 macro
Da6xx_gmu.c855 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~0); in a6xx_gmu_irq_disable()
1006 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~A6XX_HFI_IRQ_MASK); in a6xx_gmu_resume()