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Searched refs:REG_FIELD_GET (Results 1 – 25 of 44) sorted by relevance

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/drivers/gpu/drm/i915/gt/uc/
Dintel_guc_fw.c100 u32 uk_val = REG_FIELD_GET(GS_UKERNEL_MASK, val); in guc_load_done()
101 u32 br_val = REG_FIELD_GET(GS_BOOTROM_MASK, val); in guc_load_done()
196 REG_FIELD_GET(GS_BOOTROM_MASK, status), in guc_wait_ucode()
197 REG_FIELD_GET(GS_UKERNEL_MASK, status)); in guc_wait_ucode()
203 u32 ukernel = REG_FIELD_GET(GS_UKERNEL_MASK, status); in guc_wait_ucode()
204 u32 bootrom = REG_FIELD_GET(GS_BOOTROM_MASK, status); in guc_wait_ucode()
209 REG_FIELD_GET(GS_MIA_IN_RESET, status), in guc_wait_ucode()
211 REG_FIELD_GET(GS_MIA_MASK, status), in guc_wait_ucode()
212 REG_FIELD_GET(GS_AUTH_STATUS_MASK, status)); in guc_wait_ucode()
Dintel_gsc_fw.c21 return REG_FIELD_GET(HECI1_FWSTS1_CURRENT_STATE, fw_status) == in gsc_is_in_reset()
42 return REG_FIELD_GET(HECI1_FWSTS1_CURRENT_STATE, in intel_gsc_uc_fw_proxy_init_done()
Dintel_guc_slpc.c364 return DIV_ROUND_CLOSEST(REG_FIELD_GET(SLPC_MIN_UNSLICE_FREQ_MASK, in slpc_decode_min_freq()
375 return DIV_ROUND_CLOSEST(REG_FIELD_GET(SLPC_MAX_UNSLICE_FREQ_MASK, in slpc_decode_max_freq()
/drivers/gpu/drm/i915/display/
Dintel_pmdemand.c406 REG_FIELD_GET(XELPDP_PMDEMAND_QCLK_GV_BW_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
408 REG_FIELD_GET(XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
410 REG_FIELD_GET(XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
412 REG_FIELD_GET(XELPDP_PMDEMAND_PIPES_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
414 REG_FIELD_GET(XELPDP_PMDEMAND_DBUFS_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
416 REG_FIELD_GET(XELPDP_PMDEMAND_PHYS_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
420 REG_FIELD_GET(XELPDP_PMDEMAND_CDCLK_FREQ_MASK, reg2); in intel_pmdemand_init_pmdemand_params()
422 REG_FIELD_GET(XELPDP_PMDEMAND_DDICLK_FREQ_MASK, reg2); in intel_pmdemand_init_pmdemand_params()
424 REG_FIELD_GET(XELPDP_PMDEMAND_SCALERS_MASK, reg2); in intel_pmdemand_init_pmdemand_params()
492 u32 current_val = serialized ? 0 : REG_FIELD_GET((mask), *(reg)); \ in intel_pmdemand_update_params()
Dintel_lvds.c98 *pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK_CPT, val); in intel_lvds_port_enabled()
100 *pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK, val); in intel_lvds_port_enabled()
167 pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val); in intel_lvds_pps_get_hw_state()
168 pps->t1_t2 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
169 pps->t5 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
172 pps->t3 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
173 pps->tx = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
176 pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val); in intel_lvds_pps_get_hw_state()
177 val = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
Dintel_color.c802 entry->red = intel_color_lut_pack(REG_FIELD_GET(PALETTE_RED_MASK, val), 8); in i9xx_lut_8_pack()
803 entry->green = intel_color_lut_pack(REG_FIELD_GET(PALETTE_GREEN_MASK, val), 8); in i9xx_lut_8_pack()
804 entry->blue = intel_color_lut_pack(REG_FIELD_GET(PALETTE_BLUE_MASK, val), 8); in i9xx_lut_8_pack()
851 u16 red = REG_FIELD_GET(PALETTE_10BIT_RED_LDW_MASK, ldw) | in i9xx_lut_10_pack()
852 REG_FIELD_GET(PALETTE_10BIT_RED_UDW_MASK, udw) << 8; in i9xx_lut_10_pack()
853 u16 green = REG_FIELD_GET(PALETTE_10BIT_GREEN_LDW_MASK, ldw) | in i9xx_lut_10_pack()
854 REG_FIELD_GET(PALETTE_10BIT_GREEN_UDW_MASK, udw) << 8; in i9xx_lut_10_pack()
855 u16 blue = REG_FIELD_GET(PALETTE_10BIT_BLUE_LDW_MASK, ldw) | in i9xx_lut_10_pack()
856 REG_FIELD_GET(PALETTE_10BIT_BLUE_UDW_MASK, udw) << 8; in i9xx_lut_10_pack()
866 int r_exp = REG_FIELD_GET(PALETTE_10BIT_RED_EXP_MASK, udw); in i9xx_lut_10_pack_slope()
[all …]
Dintel_bw.c48 dclk_ratio = REG_FIELD_GET(DG1_QCLK_RATIO_MASK, val); in dg1_mchbar_read_qgv_point_info()
63 sp->t_rp = REG_FIELD_GET(DG1_DRAM_T_RP_MASK, val); in dg1_mchbar_read_qgv_point_info()
64 sp->t_rdpre = REG_FIELD_GET(DG1_DRAM_T_RDPRE_MASK, val); in dg1_mchbar_read_qgv_point_info()
67 sp->t_rcd = REG_FIELD_GET(DG1_DRAM_T_RCD_MASK, val); in dg1_mchbar_read_qgv_point_info()
68 sp->t_ras = REG_FIELD_GET(DG1_DRAM_T_RAS_MASK, val); in dg1_mchbar_read_qgv_point_info()
184 dclk = REG_FIELD_GET(MTL_DCLK_MASK, val); in mtl_read_qgv_point_info()
186 sp->t_rp = REG_FIELD_GET(MTL_TRP_MASK, val); in mtl_read_qgv_point_info()
187 sp->t_rcd = REG_FIELD_GET(MTL_TRCD_MASK, val); in mtl_read_qgv_point_info()
189 sp->t_rdpre = REG_FIELD_GET(MTL_TRDPRE_MASK, val2); in mtl_read_qgv_point_info()
190 sp->t_ras = REG_FIELD_GET(MTL_TRAS_MASK, val2); in mtl_read_qgv_point_info()
Dintel_hti.c40 return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, i915->display.hti.state); in intel_hti_dpll_mask()
Dintel_cx0_phy.c130 if (REG_FIELD_GET(XELPDP_PORT_P2M_COMMAND_TYPE_MASK, *val) != command) { in intel_cx0_wait_for_ack()
167 return REG_FIELD_GET(XELPDP_PORT_P2M_DATA_MASK, val); in __intel_cx0_read_once()
2373 unsigned int tx_rate = REG_FIELD_GET(C20_PHY_TX_RATE, pll_state->tx[0]); in intel_c20pll_calc_port_clock()
2377 frac_en = REG_FIELD_GET(C20_MPLLB_FRACEN, pll_state->mpllb[6]); in intel_c20pll_calc_port_clock()
2381 multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mpllb[0]); in intel_c20pll_calc_port_clock()
2382 tx_clk_div = REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK, pll_state->mpllb[0]); in intel_c20pll_calc_port_clock()
2383 ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mpllb[6]); in intel_c20pll_calc_port_clock()
2387 frac_en = REG_FIELD_GET(C20_MPLLA_FRACEN, pll_state->mplla[6]); in intel_c20pll_calc_port_clock()
2391 multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mplla[0]); in intel_c20pll_calc_port_clock()
2392 tx_clk_div = REG_FIELD_GET(C20_MPLLA_TX_CLK_DIV_MASK, pll_state->mplla[1]); in intel_c20pll_calc_port_clock()
[all …]
Dskl_watermark.c81 return REG_FIELD_GET(MTL_LATENCY_QCLK_SAGV, val); in intel_sagv_block_time()
768 REG_FIELD_GET(PLANE_BUF_START_MASK, reg), in skl_ddb_entry_init_from_hw()
769 REG_FIELD_GET(PLANE_BUF_END_MASK, reg)); in skl_ddb_entry_init_from_hw()
2940 level->blocks = REG_FIELD_GET(PLANE_WM_BLOCKS_MASK, val); in skl_wm_level_from_reg_val()
2941 level->lines = REG_FIELD_GET(PLANE_WM_LINES_MASK, val); in skl_wm_level_from_reg_val()
3344 wm[0] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val); in mtl_read_wm_latency()
3345 wm[1] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val); in mtl_read_wm_latency()
3348 wm[2] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val); in mtl_read_wm_latency()
3349 wm[3] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val); in mtl_read_wm_latency()
3352 wm[4] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val); in mtl_read_wm_latency()
[all …]
Dintel_vrr.c267 REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl); in intel_vrr_get_config()
271 REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl); in intel_vrr_get_config()
Dintel_crt.c714 vtotal = REG_FIELD_GET(VTOTAL_MASK, save_vtotal) + 1; in intel_crt_load_detect()
715 vactive = REG_FIELD_GET(VACTIVE_MASK, save_vtotal) + 1; in intel_crt_load_detect()
717 vblank_start = REG_FIELD_GET(VBLANK_START_MASK, vblank) + 1; in intel_crt_load_detect()
718 vblank_end = REG_FIELD_GET(VBLANK_END_MASK, vblank) + 1; in intel_crt_load_detect()
748 u32 vsync_start = REG_FIELD_GET(VSYNC_START_MASK, vsync) + 1; in intel_crt_load_detect()
Dskl_scaler.c883 REG_FIELD_GET(PS_WIN_XPOS_MASK, pos), in skl_scaler_get_config()
884 REG_FIELD_GET(PS_WIN_YPOS_MASK, pos), in skl_scaler_get_config()
885 REG_FIELD_GET(PS_WIN_XSIZE_MASK, size), in skl_scaler_get_config()
886 REG_FIELD_GET(PS_WIN_YSIZE_MASK, size)); in skl_scaler_get_config()
Dintel_display.c2613 adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1; in intel_get_transcoder_timings()
2614 adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1; in intel_get_transcoder_timings()
2618 adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1; in intel_get_transcoder_timings()
2619 adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1; in intel_get_transcoder_timings()
2623 adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1; in intel_get_transcoder_timings()
2624 adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1; in intel_get_transcoder_timings()
2627 adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1; in intel_get_transcoder_timings()
2628 adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1; in intel_get_transcoder_timings()
2633 adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1; in intel_get_transcoder_timings()
2634 adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1; in intel_get_transcoder_timings()
[all …]
Dintel_snps_phy.c1931 refclk >>= REG_FIELD_GET(SNPS_PHY_MPLLB_REF_CLK_DIV, pll_state->mpllb_div2) - 1; in intel_mpllb_calc_port_clock()
1933 frac_en = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_EN, pll_state->mpllb_fracn1); in intel_mpllb_calc_port_clock()
1936 frac_quot = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_QUOT, pll_state->mpllb_fracn2); in intel_mpllb_calc_port_clock()
1937 frac_rem = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_REM, pll_state->mpllb_fracn2); in intel_mpllb_calc_port_clock()
1938 frac_den = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_DEN, pll_state->mpllb_fracn1); in intel_mpllb_calc_port_clock()
1941 multiplier = REG_FIELD_GET(SNPS_PHY_MPLLB_MULTIPLIER, pll_state->mpllb_div2) / 2 + 16; in intel_mpllb_calc_port_clock()
1943 tx_clk_div = REG_FIELD_GET(SNPS_PHY_MPLLB_TX_CLK_DIV, pll_state->mpllb_div); in intel_mpllb_calc_port_clock()
Dintel_pps.c1286 seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on); in intel_pps_readout_hw_state()
1287 seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on); in intel_pps_readout_hw_state()
1288 seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off); in intel_pps_readout_hw_state()
1289 seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off); in intel_pps_readout_hw_state()
1296 seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000; in intel_pps_readout_hw_state()
1298 seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000; in intel_pps_readout_hw_state()
Di9xx_plane.c688 *pipe = REG_FIELD_GET(DISP_PIPE_SEL_MASK, val); in i9xx_plane_get_hw_state()
1044 fb->width = REG_FIELD_GET(PIPESRC_WIDTH_MASK, val) + 1; in i9xx_get_initial_plane_config()
1045 fb->height = REG_FIELD_GET(PIPESRC_HEIGHT_MASK, val) + 1; in i9xx_get_initial_plane_config()
Dintel_display_device.c839 *ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val); in probe_gmdid_display()
840 *rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val); in probe_gmdid_display()
841 *step = REG_FIELD_GET(GMD_ID_STEP, val); in probe_gmdid_display()
/drivers/gpu/drm/i915/
Di915_hwmon.c100 reg_value = REG_FIELD_GET(field_msk, reg_value); in hwm_field_read_and_scale()
170 x = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_X, r); in hwm_power1_max_interval_show()
171 y = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_Y, r); in hwm_power1_max_interval_show()
214 x = REG_FIELD_GET(PKG_MAX_WIN_X, r); in hwm_power1_max_interval_store()
215 y = REG_FIELD_GET(PKG_MAX_WIN_Y, r); in hwm_power1_max_interval_store()
329 *val = DIV_ROUND_CLOSEST(REG_FIELD_GET(GEN12_VOLTAGE_MASK, reg_value) * 25, 10); in hwm_in_read()
387 min = REG_FIELD_GET(PKG_MIN_PWR, r); in hwm_power_max_read()
389 max = REG_FIELD_GET(PKG_MAX_PWR, r); in hwm_power_max_read()
477 *val = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval), in hwm_power_read()
594 *val = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval), in hwm_curr_read()
[all …]
Dintel_device_info.c306 ip->ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val); in ip_ver_read()
307 ip->rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val); in ip_ver_read()
308 ip->step = REG_FIELD_GET(GMD_ID_STEP, val); in ip_ver_read()
Di915_reg_defs.h132 #define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val)) macro
/drivers/gpu/drm/i915/soc/
Dintel_dram.c624 switch (REG_FIELD_GET(MTL_DDR_TYPE_MASK, val)) { in xelpdp_get_dram_info()
648 dram_info->num_channels = REG_FIELD_GET(MTL_N_OF_POPULATED_CH_MASK, val); in xelpdp_get_dram_info()
649 dram_info->num_qgv_points = REG_FIELD_GET(MTL_N_OF_ENABLED_QGV_POINTS_MASK, val); in xelpdp_get_dram_info()
/drivers/gpu/drm/i915/gt/
Dintel_rps.c1111 caps->rp0_freq = REG_FIELD_GET(MTL_RP0_CAP_MASK, rp_state_cap); in mtl_get_freq_caps()
1112 caps->min_freq = REG_FIELD_GET(MTL_RPN_CAP_MASK, rp_state_cap); in mtl_get_freq_caps()
1113 caps->rp1_freq = REG_FIELD_GET(MTL_RPE_MASK, rpe); in mtl_get_freq_caps()
1132 caps->rp1_freq = REG_FIELD_GET(RPE_MASK, in __gen6_rps_get_freq_caps()
2078 cagf = REG_FIELD_GET(MTL_CAGF_MASK, rpstat); in intel_rps_get_cagf()
2080 cagf = REG_FIELD_GET(GEN12_CAGF_MASK, rpstat); in intel_rps_get_cagf()
2082 cagf = REG_FIELD_GET(RPE_MASK, rpstat); in intel_rps_get_cagf()
2084 cagf = REG_FIELD_GET(GEN9_CAGF_MASK, rpstat); in intel_rps_get_cagf()
2086 cagf = REG_FIELD_GET(HSW_CAGF_MASK, rpstat); in intel_rps_get_cagf()
2088 cagf = REG_FIELD_GET(GEN6_CAGF_MASK, rpstat); in intel_rps_get_cagf()
[all …]
Dintel_gt_pm_debugfs.c285 switch (REG_FIELD_GET(MTL_CC_MASK, gt_core_status)) { in mtl_drpc()
293 MISSING_CASE(REG_FIELD_GET(MTL_CC_MASK, gt_core_status)); in mtl_drpc()
354 REG_FIELD_GET(MEMSTAT_PSTATE_MASK, rgvstat)); in intel_gt_pm_frequency_dump()
Dintel_gt_mcr.c170 fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK, in intel_gt_mcr_init()
174 fuse = REG_FIELD_GET(GT_L3_EXC_MASK, in intel_gt_mcr_init()

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