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Searched refs:REG_GENMASK (Results 1 – 25 of 25) sorted by relevance

/drivers/gpu/drm/i915/display/
Dintel_snps_phy_regs.h23 #define SNPS_PHY_MPLLB_CP_INT REG_GENMASK(31, 25)
24 #define SNPS_PHY_MPLLB_CP_INT_GS REG_GENMASK(23, 17)
25 #define SNPS_PHY_MPLLB_CP_PROP REG_GENMASK(15, 9)
26 #define SNPS_PHY_MPLLB_CP_PROP_GS REG_GENMASK(7, 1)
32 #define SNPS_PHY_MPLLB_V2I REG_GENMASK(27, 26)
33 #define SNPS_PHY_MPLLB_FREQ_VCO REG_GENMASK(25, 24)
34 #define SNPS_PHY_MPLLB_DIV_MULTIPLIER REG_GENMASK(23, 16)
38 #define SNPS_PHY_MPLLB_TX_CLK_DIV REG_GENMASK(7, 5)
44 #define SNPS_PHY_MPLLB_FRACN_DEN REG_GENMASK(15, 0)
47 #define SNPS_PHY_MPLLB_FRACN_REM REG_GENMASK(31, 16)
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Dintel_psr_regs.h14 #define EXITLINE_MASK REG_GENMASK(12, 0)
31 #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK REG_GENMASK(26, 25)
36 #define EDP_PSR_MAX_SLEEP_TIME_MASK REG_GENMASK(24, 20)
43 #define EDP_PSR_TP2_TP3_TIME_MASK REG_GENMASK(9, 8)
48 #define EDP_PSR_TP4_TIME_MASK REG_GENMASK(7, 6)
50 #define EDP_PSR_TP1_TIME_MASK REG_GENMASK(5, 4)
55 #define EDP_PSR_IDLE_FRAMES_MASK REG_GENMASK(3, 0)
71 #define TGL_PSR_MASK REG_GENMASK(2, 0)
103 #define EDP_PSR_STATUS_STATE_MASK REG_GENMASK(31, 29)
111 #define EDP_PSR_STATUS_LINK_MASK REG_GENMASK(27, 26)
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Dintel_cx0_phy_regs.h21 #define XELPDP_PORT_M2P_COMMAND_TYPE_MASK REG_GENMASK(30, 27)
25 #define XELPDP_PORT_M2P_DATA_MASK REG_GENMASK(23, 16)
28 #define XELPDP_PORT_M2P_ADDRESS_MASK REG_GENMASK(11, 0)
36 #define XELPDP_PORT_P2M_COMMAND_TYPE_MASK REG_GENMASK(30, 27)
39 #define XELPDP_PORT_P2M_DATA_MASK REG_GENMASK(23, 16)
65 #define XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK REG_GENMASK(19, 18)
75 #define XELPDP_PORT_WIDTH_MASK REG_GENMASK(3, 1)
87 #define _XELPDP_LANE0_POWERDOWN_NEW_STATE_MASK REG_GENMASK(23, 20)
89 #define _XELPDP_LANE1_POWERDOWN_NEW_STATE_MASK REG_GENMASK(19, 16)
94 #define XELPDP_LANE_POWERDOWN_NEW_STATE_MASK REG_GENMASK(3, 0)
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Dintel_pps_regs.h31 #define PP_SEQUENCE_MASK REG_GENMASK(29, 28)
36 #define PP_SEQUENCE_STATE_MASK REG_GENMASK(3, 0)
49 #define PANEL_UNLOCK_MASK REG_GENMASK(31, 16)
51 #define BXT_POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4)
59 #define PANEL_PORT_SELECT_MASK REG_GENMASK(31, 30)
65 #define PANEL_POWER_UP_DELAY_MASK REG_GENMASK(28, 16)
66 #define PANEL_LIGHT_ON_DELAY_MASK REG_GENMASK(12, 0)
70 #define PANEL_POWER_DOWN_DELAY_MASK REG_GENMASK(28, 16)
71 #define PANEL_LIGHT_OFF_DELAY_MASK REG_GENMASK(12, 0)
75 #define PP_REFERENCE_DIVIDER_MASK REG_GENMASK(31, 8)
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Dskl_watermark_regs.h15 #define MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK REG_GENMASK(24, 20) /* tgl+ */
17 #define MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK REG_GENMASK(19, 17) /* tgl+ */
20 #define MBUS_DBOX_BW_CREDIT_MASK REG_GENMASK(15, 14)
24 #define MBUS_DBOX_B_CREDIT_MASK REG_GENMASK(12, 8)
26 #define MBUS_DBOX_I_CREDIT_MASK REG_GENMASK(7, 5)
28 #define MBUS_DBOX_A_CREDIT_MASK REG_GENMASK(3, 0)
40 #define MBUS_JOIN_PIPE_SELECT_MASK REG_GENMASK(28, 26)
71 #define PLANE_WM_LINES_MASK REG_GENMASK(26, 14)
72 #define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0)
146 #define DBUF_TRACKER_STATE_SERVICE_MASK REG_GENMASK(23, 19)
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Dintel_audio_regs.h13 #define G4X_ELD_BUFFER_SIZE_MASK REG_GENMASK(13, 9)
14 #define G4X_ELD_ADDRESS_MASK REG_GENMASK(8, 5)
26 #define IBX_ELD_BUFFER_SIZE_MASK REG_GENMASK(14, 10)
27 #define IBX_ELD_ADDRESS_MASK REG_GENMASK(9, 5)
60 #define AUD_CONFIG_UPPER_N_MASK REG_GENMASK(27, 20)
61 #define AUD_CONFIG_LOWER_N_MASK REG_GENMASK(15, 4)
66 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK REG_GENMASK(19, 16)
96 #define AUD_CONFIG_M_MASK REG_GENMASK(19, 0)
Dintel_dp_aux_regs.h58 #define DP_AUX_CH_CTL_TIME_OUT_MASK REG_GENMASK(27, 26)
64 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK REG_GENMASK(24, 20)
66 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK REG_GENMASK(19, 16) /* pre-skl */
79 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK REG_GENMASK(10, 0) /* pre-skl */
81 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK REG_GENMASK(9, 5) /* skl+ */
83 #define DP_AUX_CH_CTL_SYNC_PULSE_SKL_MASK REG_GENMASK(4, 0) /* skl+ */
Dintel_lvds_regs.h21 #define LVDS_PIPE_SEL_MASK_CPT REG_GENMASK(30, 29)
35 #define LVDS_A0A2_CLKA_POWER_MASK REG_GENMASK(9, 8)
43 #define LVDS_A3_POWER_MASK REG_GENMASK(7, 6)
50 #define LVDS_CLKB_POWER_MASK REG_GENMASK(5, 4)
58 #define LVDS_B0B3_POWER_MASK REG_GENMASK(3, 2)
Dintel_dsb_regs.h27 #define DSB_MMIO_DEAD_CLOCKS_COUNT_MASK REG_GENMASK(15, 8)
29 #define DSB_MMIO_CYCLES_MASK REG_GENMASK(7, 0)
33 #define DSB_POLL_WAIT_MASK REG_GENMASK(30, 23)
35 #define DSB_POLL_COUNT_MASK REG_GENMASK(22, 15)
55 #define DSB_RM_CLAIM_TIMEOUT_COUNT_MASK REG_GENMASK(23, 16)
57 #define DSB_RM_READY_TIMEOUT_VALUE_MASK REG_GENMASK(15, 0)
Dintel_dvo_regs.h18 #define DVO_PIPE_STALL_MASK REG_GENMASK(29, 28)
24 #define DVO_PRESERVE_MASK REG_GENMASK(25, 24)
49 #define DVO_SRCDIM_HORIZONTAL_MASK REG_GENMASK(22, 12)
51 #define DVO_SRCDIM_VERTICAL_MASK REG_GENMASK(10, 0)
Dintel_dkl_phy_regs.h59 #define DKL_PLL_DIV0_AFC_STARTUP_MASK REG_GENMASK(27, 25)
150 #define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK REG_GENMASK(4, 3)
152 #define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK REG_GENMASK(6, 5)
Dintel_dmc_regs.h55 #define DMC_EVT_CTL_TYPE_MASK REG_GENMASK(17, 16)
61 #define DMC_EVT_CTL_EVENT_ID_MASK REG_GENMASK(15, 8)
Dicl_dsi_regs.h33 #define TX_ESC_CLK_DIV_PHY_MASK REG_GENMASK(23, 16)
101 #define TGL_DSI_CHKN_LSHS_GB_MASK REG_GENMASK(15, 12)
109 #define DSI_T_INIT_MASTER_MASK REG_GENMASK(15, 0)
Dintel_combo_phy_regs.h93 #define DCC_MODE_SELECT_MASK REG_GENMASK(21, 20)
155 #define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK REG_GENMASK(30, 29)
Dintel_hti_regs.h12 #define HDPORT_DPLL_USED_MASK REG_GENMASK(15, 12)
Dintel_vdsc_regs.h37 #define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25)
/drivers/gpu/drm/i915/
Dintel_mchbar_regs.h82 #define MLTR_WM2_MASK REG_GENMASK(13, 8)
83 #define MLTR_WM1_MASK REG_GENMASK(5, 0)
126 #define DG1_DRAM_T_RDPRE_MASK REG_GENMASK(16, 11)
127 #define DG1_DRAM_T_RP_MASK REG_GENMASK(6, 0)
129 #define DG1_DRAM_T_RCD_MASK REG_GENMASK(15, 9)
130 #define DG1_DRAM_T_RAS_MASK REG_GENMASK(8, 1)
189 #define DG1_QCLK_RATIO_MASK REG_GENMASK(9, 2)
204 #define PKG_PWR_UNIT REG_GENMASK(3, 0)
205 #define PKG_ENERGY_UNIT REG_GENMASK(12, 8)
206 #define PKG_TIME_UNIT REG_GENMASK(19, 16)
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Di915_reg.h596 #define PORT_PLL_P1_MASK REG_GENMASK(15, 13)
598 #define PORT_PLL_P2_MASK REG_GENMASK(12, 8)
617 #define PORT_PLL_M2_INT_MASK REG_GENMASK(7, 0)
620 #define PORT_PLL_N_MASK REG_GENMASK(11, 8)
623 #define PORT_PLL_M2_FRAC_MASK REG_GENMASK(21, 0)
628 #define PORT_PLL_GAIN_CTL_MASK REG_GENMASK(18, 16)
630 #define PORT_PLL_INT_COEFF_MASK REG_GENMASK(12, 8)
632 #define PORT_PLL_PROP_COEFF_MASK REG_GENMASK(3, 0)
635 #define PORT_PLL_TARGET_CNT_MASK REG_GENMASK(9, 0)
638 #define PORT_PLL_LOCK_THRESHOLD_MASK REG_GENMASK(3, 1)
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Di915_reg_defs.h47 #define REG_GENMASK(__high, __low) \ macro
/drivers/gpu/drm/i915/gt/
Dintel_gt_regs.h26 #define MTL_CAGF_MASK REG_GENMASK(8, 0)
29 #define MTL_CC_MASK REG_GENMASK(12, 9)
83 #define MTL_MCR_GROUPID REG_GENMASK(11, 8)
84 #define MTL_MCR_INSTANCEID REG_GENMASK(3, 0)
294 #define VERT_WM_VAL REG_GENMASK(9, 0)
428 #define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24)
430 #define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16)
526 #define PREEMPTION_VERTEX_COUNT REG_GENMASK(15, 0)
571 #define GT_L3_EXC_MASK REG_GENMASK(6, 4)
580 #define XEHP_SFC_ENABLE_MASK REG_GENMASK(27, 24)
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Dintel_gpu_commands.h132 #define MI_SEMAPHORE_TOKEN_MASK REG_GENMASK(9, 5)
246 #define XY_FAST_COPY_BLT_D0_SRC_TILING_MASK REG_GENMASK(21, 20)
247 #define XY_FAST_COPY_BLT_D0_DST_TILING_MASK REG_GENMASK(14, 13)
259 #define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 0)
260 #define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 8)
Dintel_engine_regs.h131 #define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 8)
132 #define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 0)
148 #define CMD_CCTL_WRITE_OVERRIDE_MASK REG_GENMASK(13, 7)
149 #define CMD_CCTL_READ_OVERRIDE_MASK REG_GENMASK(6, 0)
208 #define RING_FORCE_TO_NONPRIV_ADDRESS_MASK REG_GENMASK(25, 2)
Dintel_gtt.h158 #define MTL_PPAT_L4_CACHE_POLICY_MASK REG_GENMASK(3, 2)
159 #define MTL_PAT_INDEX_COH_MODE_MASK REG_GENMASK(1, 0)
/drivers/gpu/drm/i915/gt/uc/abi/
Dguc_actions_slpc_abi.h168 #define SLPC_MAX_UNSLICE_FREQ_MASK REG_GENMASK(7, 0)
169 #define SLPC_MIN_UNSLICE_FREQ_MASK REG_GENMASK(15, 8)
170 #define SLPC_MAX_SLICE_FREQ_MASK REG_GENMASK(23, 16)
171 #define SLPC_MIN_SLICE_FREQ_MASK REG_GENMASK(31, 24)
/drivers/gpu/drm/i915/gvt/
Dhandlers.c773 u32 reg_nonpriv = (*(u32 *)p_data) & REG_GENMASK(25, 2); in force_nonpriv_write()