1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * RZ/G2L MIPI DSI Interface Registers Definitions 4 * 5 * Copyright (C) 2022 Renesas Electronics Corporation 6 */ 7 8 #ifndef __RZG2L_MIPI_DSI_REGS_H__ 9 #define __RZG2L_MIPI_DSI_REGS_H__ 10 11 #include <linux/bits.h> 12 13 /* DPHY Registers */ 14 #define DSIDPHYCTRL0 0x00 15 #define DSIDPHYCTRL0_CAL_EN_HSRX_OFS BIT(16) 16 #define DSIDPHYCTRL0_CMN_MASTER_EN BIT(8) 17 #define DSIDPHYCTRL0_RE_VDD_DETVCCQLV18 BIT(2) 18 #define DSIDPHYCTRL0_EN_LDO1200 BIT(1) 19 #define DSIDPHYCTRL0_EN_BGR BIT(0) 20 21 #define DSIDPHYTIM0 0x04 22 #define DSIDPHYTIM0_TCLK_MISS(x) ((x) << 24) 23 #define DSIDPHYTIM0_T_INIT(x) ((x) << 0) 24 25 #define DSIDPHYTIM1 0x08 26 #define DSIDPHYTIM1_THS_PREPARE(x) ((x) << 24) 27 #define DSIDPHYTIM1_TCLK_PREPARE(x) ((x) << 16) 28 #define DSIDPHYTIM1_THS_SETTLE(x) ((x) << 8) 29 #define DSIDPHYTIM1_TCLK_SETTLE(x) ((x) << 0) 30 31 #define DSIDPHYTIM2 0x0c 32 #define DSIDPHYTIM2_TCLK_TRAIL(x) ((x) << 24) 33 #define DSIDPHYTIM2_TCLK_POST(x) ((x) << 16) 34 #define DSIDPHYTIM2_TCLK_PRE(x) ((x) << 8) 35 #define DSIDPHYTIM2_TCLK_ZERO(x) ((x) << 0) 36 37 #define DSIDPHYTIM3 0x10 38 #define DSIDPHYTIM3_TLPX(x) ((x) << 24) 39 #define DSIDPHYTIM3_THS_EXIT(x) ((x) << 16) 40 #define DSIDPHYTIM3_THS_TRAIL(x) ((x) << 8) 41 #define DSIDPHYTIM3_THS_ZERO(x) ((x) << 0) 42 43 /* --------------------------------------------------------*/ 44 /* Link Registers */ 45 #define LINK_REG_OFFSET 0x10000 46 47 /* Link Status Register */ 48 #define LINKSR 0x10 49 #define LINKSR_LPBUSY BIT(13) 50 #define LINKSR_HSBUSY BIT(12) 51 #define LINKSR_VICHRUN1 BIT(8) 52 #define LINKSR_SQCHRUN1 BIT(4) 53 #define LINKSR_SQCHRUN0 BIT(0) 54 55 /* Tx Set Register */ 56 #define TXSETR 0x100 57 #define TXSETR_NUMLANECAP (0x3 << 16) 58 #define TXSETR_DLEN (1 << 9) 59 #define TXSETR_CLEN (1 << 8) 60 #define TXSETR_NUMLANEUSE(x) (((x) & 0x3) << 0) 61 62 /* HS Clock Set Register */ 63 #define HSCLKSETR 0x104 64 #define HSCLKSETR_HSCLKMODE_CONT (1 << 1) 65 #define HSCLKSETR_HSCLKMODE_NON_CONT (0 << 1) 66 #define HSCLKSETR_HSCLKRUN_HS (1 << 0) 67 #define HSCLKSETR_HSCLKRUN_LP (0 << 0) 68 69 /* Reset Control Register */ 70 #define RSTCR 0x110 71 #define RSTCR_SWRST BIT(0) 72 #define RSTCR_FCETXSTP BIT(16) 73 74 /* Reset Status Register */ 75 #define RSTSR 0x114 76 #define RSTSR_DL0DIR (1 << 15) 77 #define RSTSR_DLSTPST (0xf << 8) 78 #define RSTSR_SWRSTV1 (1 << 4) 79 #define RSTSR_SWRSTIB (1 << 3) 80 #define RSTSR_SWRSTAPB (1 << 2) 81 #define RSTSR_SWRSTLP (1 << 1) 82 #define RSTSR_SWRSTHS (1 << 0) 83 84 /* Clock Lane Stop Time Set Register */ 85 #define CLSTPTSETR 0x314 86 #define CLSTPTSETR_CLKKPT(x) ((x) << 24) 87 #define CLSTPTSETR_CLKBFHT(x) ((x) << 16) 88 #define CLSTPTSETR_CLKSTPT(x) ((x) << 2) 89 90 /* LP Transition Time Set Register */ 91 #define LPTRNSTSETR 0x318 92 #define LPTRNSTSETR_GOLPBKT(x) ((x) << 0) 93 94 /* Physical Lane Status Register */ 95 #define PLSR 0x320 96 #define PLSR_CLHS2LP BIT(27) 97 #define PLSR_CLLP2HS BIT(26) 98 99 /* Video-Input Channel 1 Set 0 Register */ 100 #define VICH1SET0R 0x400 101 #define VICH1SET0R_VSEN BIT(12) 102 #define VICH1SET0R_HFPNOLP BIT(10) 103 #define VICH1SET0R_HBPNOLP BIT(9) 104 #define VICH1SET0R_HSANOLP BIT(8) 105 #define VICH1SET0R_VSTPAFT BIT(1) 106 #define VICH1SET0R_VSTART BIT(0) 107 108 /* Video-Input Channel 1 Set 1 Register */ 109 #define VICH1SET1R 0x404 110 #define VICH1SET1R_DLY(x) (((x) & 0xfff) << 2) 111 112 /* Video-Input Channel 1 Status Register */ 113 #define VICH1SR 0x410 114 #define VICH1SR_VIRDY BIT(3) 115 #define VICH1SR_RUNNING BIT(2) 116 #define VICH1SR_STOP BIT(1) 117 #define VICH1SR_START BIT(0) 118 119 /* Video-Input Channel 1 Pixel Packet Set Register */ 120 #define VICH1PPSETR 0x420 121 #define VICH1PPSETR_DT_RGB18 (0x1e << 16) 122 #define VICH1PPSETR_DT_RGB18_LS (0x2e << 16) 123 #define VICH1PPSETR_DT_RGB24 (0x3e << 16) 124 #define VICH1PPSETR_TXESYNC_PULSE (1 << 15) 125 #define VICH1PPSETR_VC(x) ((x) << 22) 126 127 /* Video-Input Channel 1 Vertical Size Set Register */ 128 #define VICH1VSSETR 0x428 129 #define VICH1VSSETR_VACTIVE(x) (((x) & 0x7fff) << 16) 130 #define VICH1VSSETR_VSPOL_LOW (1 << 15) 131 #define VICH1VSSETR_VSPOL_HIGH (0 << 15) 132 #define VICH1VSSETR_VSA(x) (((x) & 0xfff) << 0) 133 134 /* Video-Input Channel 1 Vertical Porch Set Register */ 135 #define VICH1VPSETR 0x42c 136 #define VICH1VPSETR_VFP(x) (((x) & 0x1fff) << 16) 137 #define VICH1VPSETR_VBP(x) (((x) & 0x1fff) << 0) 138 139 /* Video-Input Channel 1 Horizontal Size Set Register */ 140 #define VICH1HSSETR 0x430 141 #define VICH1HSSETR_HACTIVE(x) (((x) & 0x7fff) << 16) 142 #define VICH1HSSETR_HSPOL_LOW (1 << 15) 143 #define VICH1HSSETR_HSPOL_HIGH (0 << 15) 144 #define VICH1HSSETR_HSA(x) (((x) & 0xfff) << 0) 145 146 /* Video-Input Channel 1 Horizontal Porch Set Register */ 147 #define VICH1HPSETR 0x434 148 #define VICH1HPSETR_HFP(x) (((x) & 0x1fff) << 16) 149 #define VICH1HPSETR_HBP(x) (((x) & 0x1fff) << 0) 150 151 #endif /* __RZG2L_MIPI_DSI_REGS_H__ */ 152