Searched refs:SMU_SCLK_DPM_STATE_0_CNTL_1 (Results 1 – 2 of 2) sorted by relevance
574 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix); in trinity_set_ds_dividers()577 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value); in trinity_set_ds_dividers()586 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix); in trinity_set_ss_dividers()589 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value); in trinity_set_ss_dividers()640 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix); in trinity_set_display_wm()643 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value); in trinity_set_display_wm()652 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix); in trinity_set_vce_wm()655 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value); in trinity_set_vce_wm()
47 #define SMU_SCLK_DPM_STATE_0_CNTL_1 0x1f004 macro