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Searched refs:SOCFPGA_PLL_DIVQ_SHIFT (Results 1 – 2 of 2) sorted by relevance

/drivers/clk/socfpga/
Dclk-pll-a10.c24 #define SOCFPGA_PLL_DIVQ_SHIFT 16 macro
44 divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT; in clk_pll_recalc_rate()
Dclk-pll.c29 #define SOCFPGA_PLL_DIVQ_SHIFT 16 macro
52 divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT; in clk_pll_recalc_rate()