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1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2 /* QLogic qed NIC Driver
3  * Copyright (c) 2015-2017  QLogic Corporation
4  * Copyright (c) 2019-2021 Marvell International Ltd.
5  */
6 
7 #ifndef _QED_HSI_H
8 #define _QED_HSI_H
9 
10 #include <linux/types.h>
11 #include <linux/io.h>
12 #include <linux/bitops.h>
13 #include <linux/delay.h>
14 #include <linux/kernel.h>
15 #include <linux/list.h>
16 #include <linux/slab.h>
17 #include <linux/qed/common_hsi.h>
18 #include <linux/qed/storage_common.h>
19 #include <linux/qed/tcp_common.h>
20 #include <linux/qed/fcoe_common.h>
21 #include <linux/qed/eth_common.h>
22 #include <linux/qed/iscsi_common.h>
23 #include <linux/qed/nvmetcp_common.h>
24 #include <linux/qed/iwarp_common.h>
25 #include <linux/qed/rdma_common.h>
26 #include <linux/qed/roce_common.h>
27 #include <linux/qed/qed_fcoe_if.h>
28 
29 struct qed_hwfn;
30 struct qed_ptt;
31 
32 /* Opcodes for the event ring */
33 enum common_event_opcode {
34 	COMMON_EVENT_PF_START,
35 	COMMON_EVENT_PF_STOP,
36 	COMMON_EVENT_VF_START,
37 	COMMON_EVENT_VF_STOP,
38 	COMMON_EVENT_VF_PF_CHANNEL,
39 	COMMON_EVENT_VF_FLR,
40 	COMMON_EVENT_PF_UPDATE,
41 	COMMON_EVENT_FW_ERROR,
42 	COMMON_EVENT_RL_UPDATE,
43 	COMMON_EVENT_EMPTY,
44 	MAX_COMMON_EVENT_OPCODE
45 };
46 
47 /* Common Ramrod Command IDs */
48 enum common_ramrod_cmd_id {
49 	COMMON_RAMROD_UNUSED,
50 	COMMON_RAMROD_PF_START,
51 	COMMON_RAMROD_PF_STOP,
52 	COMMON_RAMROD_VF_START,
53 	COMMON_RAMROD_VF_STOP,
54 	COMMON_RAMROD_PF_UPDATE,
55 	COMMON_RAMROD_RL_UPDATE,
56 	COMMON_RAMROD_EMPTY,
57 	MAX_COMMON_RAMROD_CMD_ID
58 };
59 
60 /* How ll2 should deal with packet upon errors */
61 enum core_error_handle {
62 	LL2_DROP_PACKET,
63 	LL2_DO_NOTHING,
64 	LL2_ASSERT,
65 	MAX_CORE_ERROR_HANDLE
66 };
67 
68 /* Opcodes for the event ring */
69 enum core_event_opcode {
70 	CORE_EVENT_TX_QUEUE_START,
71 	CORE_EVENT_TX_QUEUE_STOP,
72 	CORE_EVENT_RX_QUEUE_START,
73 	CORE_EVENT_RX_QUEUE_STOP,
74 	CORE_EVENT_RX_QUEUE_FLUSH,
75 	CORE_EVENT_TX_QUEUE_UPDATE,
76 	CORE_EVENT_QUEUE_STATS_QUERY,
77 	MAX_CORE_EVENT_OPCODE
78 };
79 
80 /* The L4 pseudo checksum mode for Core */
81 enum core_l4_pseudo_checksum_mode {
82 	CORE_L4_PSEUDO_CSUM_CORRECT_LENGTH,
83 	CORE_L4_PSEUDO_CSUM_ZERO_LENGTH,
84 	MAX_CORE_L4_PSEUDO_CHECKSUM_MODE
85 };
86 
87 /* LL2 SP error code */
88 enum core_ll2_error_code {
89 	LL2_OK = 0,
90 	LL2_ERROR,
91 	MAX_CORE_LL2_ERROR_CODE
92 };
93 
94 /* Light-L2 RX Producers in Tstorm RAM */
95 struct core_ll2_port_stats {
96 	struct regpair gsi_invalid_hdr;
97 	struct regpair gsi_invalid_pkt_length;
98 	struct regpair gsi_unsupported_pkt_typ;
99 	struct regpair gsi_crcchksm_error;
100 };
101 
102 /* LL2 TX Per Queue Stats */
103 struct core_ll2_pstorm_per_queue_stat {
104 	struct regpair sent_ucast_bytes;
105 	struct regpair sent_mcast_bytes;
106 	struct regpair sent_bcast_bytes;
107 	struct regpair sent_ucast_pkts;
108 	struct regpair sent_mcast_pkts;
109 	struct regpair sent_bcast_pkts;
110 	struct regpair error_drop_pkts;
111 };
112 
113 /* Light-L2 RX Producers in Tstorm RAM */
114 struct core_ll2_rx_prod {
115 	__le16 bd_prod;
116 	__le16 cqe_prod;
117 };
118 
119 struct core_ll2_tstorm_per_queue_stat {
120 	struct regpair packet_too_big_discard;
121 	struct regpair no_buff_discard;
122 };
123 
124 struct core_ll2_ustorm_per_queue_stat {
125 	struct regpair rcv_ucast_bytes;
126 	struct regpair rcv_mcast_bytes;
127 	struct regpair rcv_bcast_bytes;
128 	struct regpair rcv_ucast_pkts;
129 	struct regpair rcv_mcast_pkts;
130 	struct regpair rcv_bcast_pkts;
131 };
132 
133 struct core_ll2_rx_per_queue_stat {
134 	struct core_ll2_tstorm_per_queue_stat tstorm_stat;
135 	struct core_ll2_ustorm_per_queue_stat ustorm_stat;
136 };
137 
138 struct core_ll2_tx_per_queue_stat {
139 	struct core_ll2_pstorm_per_queue_stat pstorm_stat;
140 };
141 
142 /* Structure for doorbell data, in PWM mode, for RX producers update. */
143 struct core_pwm_prod_update_data {
144 	__le16 icid; /* internal CID */
145 	u8 reserved0;
146 	u8 params;
147 #define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_MASK	  0x3
148 #define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_SHIFT   0
149 #define CORE_PWM_PROD_UPDATE_DATA_RESERVED1_MASK  0x3F	/* Set 0 */
150 #define CORE_PWM_PROD_UPDATE_DATA_RESERVED1_SHIFT 2
151 	struct core_ll2_rx_prod prod; /* Producers */
152 };
153 
154 /* Ramrod data for rx/tx queue statistics query ramrod */
155 struct core_queue_stats_query_ramrod_data {
156 	u8 rx_stat;
157 	u8 tx_stat;
158 	__le16 reserved[3];
159 	struct regpair rx_stat_addr;
160 	struct regpair tx_stat_addr;
161 };
162 
163 /* Core Ramrod Command IDs (light L2) */
164 enum core_ramrod_cmd_id {
165 	CORE_RAMROD_UNUSED,
166 	CORE_RAMROD_RX_QUEUE_START,
167 	CORE_RAMROD_TX_QUEUE_START,
168 	CORE_RAMROD_RX_QUEUE_STOP,
169 	CORE_RAMROD_TX_QUEUE_STOP,
170 	CORE_RAMROD_RX_QUEUE_FLUSH,
171 	CORE_RAMROD_TX_QUEUE_UPDATE,
172 	CORE_RAMROD_QUEUE_STATS_QUERY,
173 	MAX_CORE_RAMROD_CMD_ID
174 };
175 
176 /* Core RX CQE Type for Light L2 */
177 enum core_roce_flavor_type {
178 	CORE_ROCE,
179 	CORE_RROCE,
180 	MAX_CORE_ROCE_FLAVOR_TYPE
181 };
182 
183 /* Specifies how ll2 should deal with packets errors: packet_too_big and
184  * no_buff.
185  */
186 struct core_rx_action_on_error {
187 	u8 error_type;
188 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK	0x3
189 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_SHIFT	0
190 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK		0x3
191 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_SHIFT		2
192 #define CORE_RX_ACTION_ON_ERROR_RESERVED_MASK		0xF
193 #define CORE_RX_ACTION_ON_ERROR_RESERVED_SHIFT		4
194 };
195 
196 /* Core RX BD for Light L2 */
197 struct core_rx_bd {
198 	struct regpair addr;
199 	__le16 reserved[4];
200 };
201 
202 /* Core RX CM offload BD for Light L2 */
203 struct core_rx_bd_with_buff_len {
204 	struct regpair addr;
205 	__le16 buff_length;
206 	__le16 reserved[3];
207 };
208 
209 /* Core RX CM offload BD for Light L2 */
210 union core_rx_bd_union {
211 	struct core_rx_bd rx_bd;
212 	struct core_rx_bd_with_buff_len rx_bd_with_len;
213 };
214 
215 /* Opaque Data for Light L2 RX CQE */
216 struct core_rx_cqe_opaque_data {
217 	__le32 data[2];
218 };
219 
220 /* Core RX CQE Type for Light L2 */
221 enum core_rx_cqe_type {
222 	CORE_RX_CQE_ILLEGAL_TYPE,
223 	CORE_RX_CQE_TYPE_REGULAR,
224 	CORE_RX_CQE_TYPE_GSI_OFFLOAD,
225 	CORE_RX_CQE_TYPE_SLOW_PATH,
226 	MAX_CORE_RX_CQE_TYPE
227 };
228 
229 /* Core RX CQE for Light L2 */
230 struct core_rx_fast_path_cqe {
231 	u8 type;
232 	u8 placement_offset;
233 	struct parsing_and_err_flags parse_flags;
234 	__le16 packet_length;
235 	__le16 vlan;
236 	struct core_rx_cqe_opaque_data opaque_data;
237 	struct parsing_err_flags err_flags;
238 	u8 packet_source;
239 	u8 reserved0;
240 	__le32 reserved1[3];
241 };
242 
243 /* Core Rx CM offload CQE */
244 struct core_rx_gsi_offload_cqe {
245 	u8 type;
246 	u8 data_length_error;
247 	struct parsing_and_err_flags parse_flags;
248 	__le16 data_length;
249 	__le16 vlan;
250 	__le32 src_mac_addrhi;
251 	__le16 src_mac_addrlo;
252 	__le16 qp_id;
253 	__le32 src_qp;
254 	struct core_rx_cqe_opaque_data opaque_data;
255 	u8 packet_source;
256 	u8 reserved[3];
257 };
258 
259 /* Core RX CQE for Light L2 */
260 struct core_rx_slow_path_cqe {
261 	u8 type;
262 	u8 ramrod_cmd_id;
263 	__le16 echo;
264 	struct core_rx_cqe_opaque_data opaque_data;
265 	__le32 reserved1[5];
266 };
267 
268 /* Core RX CM offload BD for Light L2 */
269 union core_rx_cqe_union {
270 	struct core_rx_fast_path_cqe rx_cqe_fp;
271 	struct core_rx_gsi_offload_cqe rx_cqe_gsi;
272 	struct core_rx_slow_path_cqe rx_cqe_sp;
273 };
274 
275 /* RX packet source. */
276 enum core_rx_pkt_source {
277 	CORE_RX_PKT_SOURCE_NETWORK = 0,
278 	CORE_RX_PKT_SOURCE_LB,
279 	CORE_RX_PKT_SOURCE_TX,
280 	CORE_RX_PKT_SOURCE_LL2_TX,
281 	MAX_CORE_RX_PKT_SOURCE
282 };
283 
284 /* Ramrod data for rx queue start ramrod */
285 struct core_rx_start_ramrod_data {
286 	struct regpair bd_base;
287 	struct regpair cqe_pbl_addr;
288 	__le16 mtu;
289 	__le16 sb_id;
290 	u8 sb_index;
291 	u8 complete_cqe_flg;
292 	u8 complete_event_flg;
293 	u8 drop_ttl0_flg;
294 	__le16 num_of_pbl_pages;
295 	u8 inner_vlan_stripping_en;
296 	u8 report_outer_vlan;
297 	u8 queue_id;
298 	u8 main_func_queue;
299 	u8 mf_si_bcast_accept_all;
300 	u8 mf_si_mcast_accept_all;
301 	struct core_rx_action_on_error action_on_error;
302 	u8 gsi_offload_flag;
303 	u8 vport_id_valid;
304 	u8 vport_id;
305 	u8 zero_prod_flg;
306 	u8 wipe_inner_vlan_pri_en;
307 	u8 reserved[2];
308 };
309 
310 /* Ramrod data for rx queue stop ramrod */
311 struct core_rx_stop_ramrod_data {
312 	u8 complete_cqe_flg;
313 	u8 complete_event_flg;
314 	u8 queue_id;
315 	u8 reserved1;
316 	__le16 reserved2[2];
317 };
318 
319 /* Flags for Core TX BD */
320 struct core_tx_bd_data {
321 	__le16 as_bitfield;
322 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_MASK		0x1
323 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_SHIFT		0
324 #define CORE_TX_BD_DATA_VLAN_INSERTION_MASK		0x1
325 #define CORE_TX_BD_DATA_VLAN_INSERTION_SHIFT		1
326 #define CORE_TX_BD_DATA_START_BD_MASK			0x1
327 #define CORE_TX_BD_DATA_START_BD_SHIFT			2
328 #define CORE_TX_BD_DATA_IP_CSUM_MASK			0x1
329 #define CORE_TX_BD_DATA_IP_CSUM_SHIFT			3
330 #define CORE_TX_BD_DATA_L4_CSUM_MASK			0x1
331 #define CORE_TX_BD_DATA_L4_CSUM_SHIFT			4
332 #define CORE_TX_BD_DATA_IPV6_EXT_MASK			0x1
333 #define CORE_TX_BD_DATA_IPV6_EXT_SHIFT			5
334 #define CORE_TX_BD_DATA_L4_PROTOCOL_MASK		0x1
335 #define CORE_TX_BD_DATA_L4_PROTOCOL_SHIFT		6
336 #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_MASK	0x1
337 #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_SHIFT	7
338 #define CORE_TX_BD_DATA_NBDS_MASK			0xF
339 #define CORE_TX_BD_DATA_NBDS_SHIFT			8
340 #define CORE_TX_BD_DATA_ROCE_FLAV_MASK			0x1
341 #define CORE_TX_BD_DATA_ROCE_FLAV_SHIFT			12
342 #define CORE_TX_BD_DATA_IP_LEN_MASK			0x1
343 #define CORE_TX_BD_DATA_IP_LEN_SHIFT			13
344 #define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_MASK	0x1
345 #define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_SHIFT	14
346 #define CORE_TX_BD_DATA_RESERVED0_MASK			0x1
347 #define CORE_TX_BD_DATA_RESERVED0_SHIFT			15
348 };
349 
350 /* Core TX BD for Light L2 */
351 struct core_tx_bd {
352 	struct regpair addr;
353 	__le16 nbytes;
354 	__le16 nw_vlan_or_lb_echo;
355 	struct core_tx_bd_data bd_data;
356 	__le16 bitfield1;
357 #define CORE_TX_BD_L4_HDR_OFFSET_W_MASK		0x3FFF
358 #define CORE_TX_BD_L4_HDR_OFFSET_W_SHIFT	0
359 #define CORE_TX_BD_TX_DST_MASK			0x3
360 #define CORE_TX_BD_TX_DST_SHIFT			14
361 };
362 
363 /* Light L2 TX Destination */
364 enum core_tx_dest {
365 	CORE_TX_DEST_NW,
366 	CORE_TX_DEST_LB,
367 	CORE_TX_DEST_RESERVED,
368 	CORE_TX_DEST_DROP,
369 	MAX_CORE_TX_DEST
370 };
371 
372 /* Ramrod data for tx queue start ramrod */
373 struct core_tx_start_ramrod_data {
374 	struct regpair pbl_base_addr;
375 	__le16 mtu;
376 	__le16 sb_id;
377 	u8 sb_index;
378 	u8 stats_en;
379 	u8 stats_id;
380 	u8 conn_type;
381 	__le16 pbl_size;
382 	__le16 qm_pq_id;
383 	u8 gsi_offload_flag;
384 	u8 ctx_stats_en;
385 	u8 vport_id_valid;
386 	u8 vport_id;
387 	u8 enforce_security_flag;
388 	u8 reserved[7];
389 };
390 
391 /* Ramrod data for tx queue stop ramrod */
392 struct core_tx_stop_ramrod_data {
393 	__le32 reserved0[2];
394 };
395 
396 /* Ramrod data for tx queue update ramrod */
397 struct core_tx_update_ramrod_data {
398 	u8 update_qm_pq_id_flg;
399 	u8 reserved0;
400 	__le16 qm_pq_id;
401 	__le32 reserved1[1];
402 };
403 
404 /* Enum flag for what type of dcb data to update */
405 enum dcb_dscp_update_mode {
406 	DONT_UPDATE_DCB_DSCP,
407 	UPDATE_DCB,
408 	UPDATE_DSCP,
409 	UPDATE_DCB_DSCP,
410 	MAX_DCB_DSCP_UPDATE_MODE
411 };
412 
413 /* The core storm context for the Ystorm */
414 struct ystorm_core_conn_st_ctx {
415 	__le32 reserved[4];
416 };
417 
418 /* The core storm context for the Pstorm */
419 struct pstorm_core_conn_st_ctx {
420 	__le32 reserved[20];
421 };
422 
423 /* Core Slowpath Connection storm context of Xstorm */
424 struct xstorm_core_conn_st_ctx {
425 	struct regpair spq_base_addr;
426 	__le32 reserved0[2];
427 	__le16 spq_cons;
428 	__le16 reserved1[111];
429 };
430 
431 struct xstorm_core_conn_ag_ctx {
432 	u8 reserved0;
433 	u8 state;
434 	u8 flags0;
435 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
436 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
437 #define XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK	0x1
438 #define XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT	1
439 #define XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK	0x1
440 #define XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT	2
441 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK	0x1
442 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT	3
443 #define XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK	0x1
444 #define XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT	4
445 #define XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK	0x1
446 #define XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT	5
447 #define XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK	0x1
448 #define XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT	6
449 #define XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK	0x1
450 #define XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT	7
451 	u8 flags1;
452 #define XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK	0x1
453 #define XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT	0
454 #define XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK	0x1
455 #define XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT	1
456 #define XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK	0x1
457 #define XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT	2
458 #define XSTORM_CORE_CONN_AG_CTX_BIT11_MASK		0x1
459 #define XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT		3
460 #define XSTORM_CORE_CONN_AG_CTX_BIT12_MASK		0x1
461 #define XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT		4
462 #define XSTORM_CORE_CONN_AG_CTX_BIT13_MASK		0x1
463 #define XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT		5
464 #define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK	0x1
465 #define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT	6
466 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK	0x1
467 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT	7
468 	u8 flags2;
469 #define XSTORM_CORE_CONN_AG_CTX_CF0_MASK	0x3
470 #define XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT	0
471 #define XSTORM_CORE_CONN_AG_CTX_CF1_MASK	0x3
472 #define XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT	2
473 #define XSTORM_CORE_CONN_AG_CTX_CF2_MASK	0x3
474 #define XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT	4
475 #define XSTORM_CORE_CONN_AG_CTX_CF3_MASK	0x3
476 #define XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT	6
477 	u8 flags3;
478 #define XSTORM_CORE_CONN_AG_CTX_CF4_MASK	0x3
479 #define XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT	0
480 #define XSTORM_CORE_CONN_AG_CTX_CF5_MASK	0x3
481 #define XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT	2
482 #define XSTORM_CORE_CONN_AG_CTX_CF6_MASK	0x3
483 #define XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT	4
484 #define XSTORM_CORE_CONN_AG_CTX_CF7_MASK	0x3
485 #define XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT	6
486 	u8 flags4;
487 #define XSTORM_CORE_CONN_AG_CTX_CF8_MASK	0x3
488 #define XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT	0
489 #define XSTORM_CORE_CONN_AG_CTX_CF9_MASK	0x3
490 #define XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT	2
491 #define XSTORM_CORE_CONN_AG_CTX_CF10_MASK	0x3
492 #define XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT	4
493 #define XSTORM_CORE_CONN_AG_CTX_CF11_MASK	0x3
494 #define XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT	6
495 	u8 flags5;
496 #define XSTORM_CORE_CONN_AG_CTX_CF12_MASK	0x3
497 #define XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT	0
498 #define XSTORM_CORE_CONN_AG_CTX_CF13_MASK	0x3
499 #define XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT	2
500 #define XSTORM_CORE_CONN_AG_CTX_CF14_MASK	0x3
501 #define XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT	4
502 #define XSTORM_CORE_CONN_AG_CTX_CF15_MASK	0x3
503 #define XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT	6
504 	u8 flags6;
505 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK	0x3
506 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT	0
507 #define XSTORM_CORE_CONN_AG_CTX_CF17_MASK			0x3
508 #define XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT			2
509 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK			0x3
510 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT			4
511 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK		0x3
512 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT		6
513 	u8 flags7;
514 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK	0x3
515 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT	0
516 #define XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK	0x3
517 #define XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT	2
518 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK	0x3
519 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT	4
520 #define XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK		0x1
521 #define XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT		6
522 #define XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK		0x1
523 #define XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT		7
524 	u8 flags8;
525 #define XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK	0x1
526 #define XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT	0
527 #define XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK	0x1
528 #define XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT	1
529 #define XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK	0x1
530 #define XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT	2
531 #define XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK	0x1
532 #define XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT	3
533 #define XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK	0x1
534 #define XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT	4
535 #define XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK	0x1
536 #define XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT	5
537 #define XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK	0x1
538 #define XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT	6
539 #define XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK	0x1
540 #define XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT	7
541 	u8 flags9;
542 #define XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK			0x1
543 #define XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT			0
544 #define XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK			0x1
545 #define XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT			1
546 #define XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK			0x1
547 #define XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT			2
548 #define XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK			0x1
549 #define XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT			3
550 #define XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK			0x1
551 #define XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT			4
552 #define XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK			0x1
553 #define XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT			5
554 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK	0x1
555 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT	6
556 #define XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK			0x1
557 #define XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT			7
558 	u8 flags10;
559 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK		0x1
560 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT		0
561 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK		0x1
562 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT	1
563 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK		0x1
564 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT		2
565 #define XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK		0x1
566 #define XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT		3
567 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK		0x1
568 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT		4
569 #define XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK			0x1
570 #define XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT			5
571 #define XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK		0x1
572 #define XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT		6
573 #define XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK		0x1
574 #define XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT		7
575 	u8 flags11;
576 #define XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK	0x1
577 #define XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT	0
578 #define XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK	0x1
579 #define XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT	1
580 #define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK	0x1
581 #define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT	2
582 #define XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK		0x1
583 #define XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT	3
584 #define XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK		0x1
585 #define XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT	4
586 #define XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK		0x1
587 #define XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT	5
588 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK	0x1
589 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT	6
590 #define XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK		0x1
591 #define XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT	7
592 	u8 flags12;
593 #define XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK	0x1
594 #define XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT	0
595 #define XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK	0x1
596 #define XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT	1
597 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK	0x1
598 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT	2
599 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK	0x1
600 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT	3
601 #define XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK	0x1
602 #define XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT	4
603 #define XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK	0x1
604 #define XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT	5
605 #define XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK	0x1
606 #define XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT	6
607 #define XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK	0x1
608 #define XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT	7
609 	u8 flags13;
610 #define XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK	0x1
611 #define XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT	0
612 #define XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK	0x1
613 #define XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT	1
614 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK	0x1
615 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT	2
616 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK	0x1
617 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT	3
618 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK	0x1
619 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT	4
620 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK	0x1
621 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT	5
622 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK	0x1
623 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT	6
624 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK	0x1
625 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT	7
626 	u8 flags14;
627 #define XSTORM_CORE_CONN_AG_CTX_BIT16_MASK	0x1
628 #define XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT	0
629 #define XSTORM_CORE_CONN_AG_CTX_BIT17_MASK	0x1
630 #define XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT	1
631 #define XSTORM_CORE_CONN_AG_CTX_BIT18_MASK	0x1
632 #define XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT	2
633 #define XSTORM_CORE_CONN_AG_CTX_BIT19_MASK	0x1
634 #define XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT	3
635 #define XSTORM_CORE_CONN_AG_CTX_BIT20_MASK	0x1
636 #define XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT	4
637 #define XSTORM_CORE_CONN_AG_CTX_BIT21_MASK	0x1
638 #define XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT	5
639 #define XSTORM_CORE_CONN_AG_CTX_CF23_MASK	0x3
640 #define XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT	6
641 	u8 byte2;
642 	__le16 physical_q0;
643 	__le16 consolid_prod;
644 	__le16 reserved16;
645 	__le16 tx_bd_cons;
646 	__le16 tx_bd_or_spq_prod;
647 	__le16 updated_qm_pq_id;
648 	__le16 conn_dpi;
649 	u8 byte3;
650 	u8 byte4;
651 	u8 byte5;
652 	u8 byte6;
653 	__le32 reg0;
654 	__le32 reg1;
655 	__le32 reg2;
656 	__le32 reg3;
657 	__le32 reg4;
658 	__le32 reg5;
659 	__le32 reg6;
660 	__le16 word7;
661 	__le16 word8;
662 	__le16 word9;
663 	__le16 word10;
664 	__le32 reg7;
665 	__le32 reg8;
666 	__le32 reg9;
667 	u8 byte7;
668 	u8 byte8;
669 	u8 byte9;
670 	u8 byte10;
671 	u8 byte11;
672 	u8 byte12;
673 	u8 byte13;
674 	u8 byte14;
675 	u8 byte15;
676 	u8 e5_reserved;
677 	__le16 word11;
678 	__le32 reg10;
679 	__le32 reg11;
680 	__le32 reg12;
681 	__le32 reg13;
682 	__le32 reg14;
683 	__le32 reg15;
684 	__le32 reg16;
685 	__le32 reg17;
686 	__le32 reg18;
687 	__le32 reg19;
688 	__le16 word12;
689 	__le16 word13;
690 	__le16 word14;
691 	__le16 word15;
692 };
693 
694 struct tstorm_core_conn_ag_ctx {
695 	u8 byte0;
696 	u8 byte1;
697 	u8 flags0;
698 #define TSTORM_CORE_CONN_AG_CTX_BIT0_MASK	0x1
699 #define TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT	0
700 #define TSTORM_CORE_CONN_AG_CTX_BIT1_MASK	0x1
701 #define TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT	1
702 #define TSTORM_CORE_CONN_AG_CTX_BIT2_MASK	0x1
703 #define TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT	2
704 #define TSTORM_CORE_CONN_AG_CTX_BIT3_MASK	0x1
705 #define TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT	3
706 #define TSTORM_CORE_CONN_AG_CTX_BIT4_MASK	0x1
707 #define TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT	4
708 #define TSTORM_CORE_CONN_AG_CTX_BIT5_MASK	0x1
709 #define TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT	5
710 #define TSTORM_CORE_CONN_AG_CTX_CF0_MASK	0x3
711 #define TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT	6
712 	u8 flags1;
713 #define TSTORM_CORE_CONN_AG_CTX_CF1_MASK	0x3
714 #define TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT	0
715 #define TSTORM_CORE_CONN_AG_CTX_CF2_MASK	0x3
716 #define TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT	2
717 #define TSTORM_CORE_CONN_AG_CTX_CF3_MASK	0x3
718 #define TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT	4
719 #define TSTORM_CORE_CONN_AG_CTX_CF4_MASK	0x3
720 #define TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT	6
721 	u8 flags2;
722 #define TSTORM_CORE_CONN_AG_CTX_CF5_MASK	0x3
723 #define TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT	0
724 #define TSTORM_CORE_CONN_AG_CTX_CF6_MASK	0x3
725 #define TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT	2
726 #define TSTORM_CORE_CONN_AG_CTX_CF7_MASK	0x3
727 #define TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT	4
728 #define TSTORM_CORE_CONN_AG_CTX_CF8_MASK	0x3
729 #define TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT	6
730 	u8 flags3;
731 #define TSTORM_CORE_CONN_AG_CTX_CF9_MASK	0x3
732 #define TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT	0
733 #define TSTORM_CORE_CONN_AG_CTX_CF10_MASK	0x3
734 #define TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT	2
735 #define TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK	0x1
736 #define TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT	4
737 #define TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK	0x1
738 #define TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT	5
739 #define TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK	0x1
740 #define TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT	6
741 #define TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK	0x1
742 #define TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT	7
743 	u8 flags4;
744 #define TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK		0x1
745 #define TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT		0
746 #define TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK		0x1
747 #define TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT		1
748 #define TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK		0x1
749 #define TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT		2
750 #define TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK		0x1
751 #define TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT		3
752 #define TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK		0x1
753 #define TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT		4
754 #define TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK		0x1
755 #define TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT		5
756 #define TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK		0x1
757 #define TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT		6
758 #define TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK		0x1
759 #define TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT	7
760 	u8 flags5;
761 #define TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK		0x1
762 #define TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT	0
763 #define TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK		0x1
764 #define TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT	1
765 #define TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK		0x1
766 #define TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT	2
767 #define TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK		0x1
768 #define TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT	3
769 #define TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK		0x1
770 #define TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT	4
771 #define TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK		0x1
772 #define TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT	5
773 #define TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK		0x1
774 #define TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT	6
775 #define TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK		0x1
776 #define TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT	7
777 	__le32 reg0;
778 	__le32 reg1;
779 	__le32 reg2;
780 	__le32 reg3;
781 	__le32 reg4;
782 	__le32 reg5;
783 	__le32 reg6;
784 	__le32 reg7;
785 	__le32 reg8;
786 	u8 byte2;
787 	u8 byte3;
788 	__le16 word0;
789 	u8 byte4;
790 	u8 byte5;
791 	__le16 word1;
792 	__le16 word2;
793 	__le16 word3;
794 	__le32 ll2_rx_prod;
795 	__le32 reg10;
796 };
797 
798 struct ustorm_core_conn_ag_ctx {
799 	u8 reserved;
800 	u8 byte1;
801 	u8 flags0;
802 #define USTORM_CORE_CONN_AG_CTX_BIT0_MASK	0x1
803 #define USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT	0
804 #define USTORM_CORE_CONN_AG_CTX_BIT1_MASK	0x1
805 #define USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT	1
806 #define USTORM_CORE_CONN_AG_CTX_CF0_MASK	0x3
807 #define USTORM_CORE_CONN_AG_CTX_CF0_SHIFT	2
808 #define USTORM_CORE_CONN_AG_CTX_CF1_MASK	0x3
809 #define USTORM_CORE_CONN_AG_CTX_CF1_SHIFT	4
810 #define USTORM_CORE_CONN_AG_CTX_CF2_MASK	0x3
811 #define USTORM_CORE_CONN_AG_CTX_CF2_SHIFT	6
812 	u8 flags1;
813 #define USTORM_CORE_CONN_AG_CTX_CF3_MASK	0x3
814 #define USTORM_CORE_CONN_AG_CTX_CF3_SHIFT	0
815 #define USTORM_CORE_CONN_AG_CTX_CF4_MASK	0x3
816 #define USTORM_CORE_CONN_AG_CTX_CF4_SHIFT	2
817 #define USTORM_CORE_CONN_AG_CTX_CF5_MASK	0x3
818 #define USTORM_CORE_CONN_AG_CTX_CF5_SHIFT	4
819 #define USTORM_CORE_CONN_AG_CTX_CF6_MASK	0x3
820 #define USTORM_CORE_CONN_AG_CTX_CF6_SHIFT	6
821 	u8 flags2;
822 #define USTORM_CORE_CONN_AG_CTX_CF0EN_MASK		0x1
823 #define USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT		0
824 #define USTORM_CORE_CONN_AG_CTX_CF1EN_MASK		0x1
825 #define USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT		1
826 #define USTORM_CORE_CONN_AG_CTX_CF2EN_MASK		0x1
827 #define USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT		2
828 #define USTORM_CORE_CONN_AG_CTX_CF3EN_MASK		0x1
829 #define USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT		3
830 #define USTORM_CORE_CONN_AG_CTX_CF4EN_MASK		0x1
831 #define USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT		4
832 #define USTORM_CORE_CONN_AG_CTX_CF5EN_MASK		0x1
833 #define USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT		5
834 #define USTORM_CORE_CONN_AG_CTX_CF6EN_MASK		0x1
835 #define USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT		6
836 #define USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK		0x1
837 #define USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT	7
838 	u8 flags3;
839 #define USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK		0x1
840 #define USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT	0
841 #define USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK		0x1
842 #define USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT	1
843 #define USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK		0x1
844 #define USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT	2
845 #define USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK		0x1
846 #define USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT	3
847 #define USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK		0x1
848 #define USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT	4
849 #define USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK		0x1
850 #define USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT	5
851 #define USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK		0x1
852 #define USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT	6
853 #define USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK		0x1
854 #define USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT	7
855 	u8 byte2;
856 	u8 byte3;
857 	__le16 word0;
858 	__le16 word1;
859 	__le32 rx_producers;
860 	__le32 reg1;
861 	__le32 reg2;
862 	__le32 reg3;
863 	__le16 word2;
864 	__le16 word3;
865 };
866 
867 /* The core storm context for the Mstorm */
868 struct mstorm_core_conn_st_ctx {
869 	__le32 reserved[40];
870 };
871 
872 /* The core storm context for the Ustorm */
873 struct ustorm_core_conn_st_ctx {
874 	__le32 reserved[20];
875 };
876 
877 /* The core storm context for the Tstorm */
878 struct tstorm_core_conn_st_ctx {
879 	__le32 reserved[4];
880 };
881 
882 /* core connection context */
883 struct core_conn_context {
884 	struct ystorm_core_conn_st_ctx ystorm_st_context;
885 	struct regpair ystorm_st_padding[2];
886 	struct pstorm_core_conn_st_ctx pstorm_st_context;
887 	struct regpair pstorm_st_padding[2];
888 	struct xstorm_core_conn_st_ctx xstorm_st_context;
889 	struct xstorm_core_conn_ag_ctx xstorm_ag_context;
890 	struct tstorm_core_conn_ag_ctx tstorm_ag_context;
891 	struct ustorm_core_conn_ag_ctx ustorm_ag_context;
892 	struct mstorm_core_conn_st_ctx mstorm_st_context;
893 	struct ustorm_core_conn_st_ctx ustorm_st_context;
894 	struct regpair ustorm_st_padding[2];
895 	struct tstorm_core_conn_st_ctx tstorm_st_context;
896 	struct regpair tstorm_st_padding[2];
897 };
898 
899 struct eth_mstorm_per_pf_stat {
900 	struct regpair gre_discard_pkts;
901 	struct regpair vxlan_discard_pkts;
902 	struct regpair geneve_discard_pkts;
903 	struct regpair lb_discard_pkts;
904 };
905 
906 struct eth_mstorm_per_queue_stat {
907 	struct regpair ttl0_discard;
908 	struct regpair packet_too_big_discard;
909 	struct regpair no_buff_discard;
910 	struct regpair not_active_discard;
911 	struct regpair tpa_coalesced_pkts;
912 	struct regpair tpa_coalesced_events;
913 	struct regpair tpa_aborts_num;
914 	struct regpair tpa_coalesced_bytes;
915 };
916 
917 /* Ethernet TX Per PF */
918 struct eth_pstorm_per_pf_stat {
919 	struct regpair sent_lb_ucast_bytes;
920 	struct regpair sent_lb_mcast_bytes;
921 	struct regpair sent_lb_bcast_bytes;
922 	struct regpair sent_lb_ucast_pkts;
923 	struct regpair sent_lb_mcast_pkts;
924 	struct regpair sent_lb_bcast_pkts;
925 	struct regpair sent_gre_bytes;
926 	struct regpair sent_vxlan_bytes;
927 	struct regpair sent_geneve_bytes;
928 	struct regpair sent_mpls_bytes;
929 	struct regpair sent_gre_mpls_bytes;
930 	struct regpair sent_udp_mpls_bytes;
931 	struct regpair sent_gre_pkts;
932 	struct regpair sent_vxlan_pkts;
933 	struct regpair sent_geneve_pkts;
934 	struct regpair sent_mpls_pkts;
935 	struct regpair sent_gre_mpls_pkts;
936 	struct regpair sent_udp_mpls_pkts;
937 	struct regpair gre_drop_pkts;
938 	struct regpair vxlan_drop_pkts;
939 	struct regpair geneve_drop_pkts;
940 	struct regpair mpls_drop_pkts;
941 	struct regpair gre_mpls_drop_pkts;
942 	struct regpair udp_mpls_drop_pkts;
943 };
944 
945 /* Ethernet TX Per Queue Stats */
946 struct eth_pstorm_per_queue_stat {
947 	struct regpair sent_ucast_bytes;
948 	struct regpair sent_mcast_bytes;
949 	struct regpair sent_bcast_bytes;
950 	struct regpair sent_ucast_pkts;
951 	struct regpair sent_mcast_pkts;
952 	struct regpair sent_bcast_pkts;
953 	struct regpair error_drop_pkts;
954 };
955 
956 /* ETH Rx producers data */
957 struct eth_rx_rate_limit {
958 	__le16 mult;
959 	__le16 cnst;
960 	u8 add_sub_cnst;
961 	u8 reserved0;
962 	__le16 reserved1;
963 };
964 
965 /* Update RSS indirection table entry command */
966 struct eth_tstorm_rss_update_data {
967 	u8 vport_id;
968 	u8 ind_table_index;
969 	__le16 ind_table_value;
970 	__le16 reserved1;
971 	u8 reserved;
972 	u8 valid;
973 };
974 
975 struct eth_ustorm_per_pf_stat {
976 	struct regpair rcv_lb_ucast_bytes;
977 	struct regpair rcv_lb_mcast_bytes;
978 	struct regpair rcv_lb_bcast_bytes;
979 	struct regpair rcv_lb_ucast_pkts;
980 	struct regpair rcv_lb_mcast_pkts;
981 	struct regpair rcv_lb_bcast_pkts;
982 	struct regpair rcv_gre_bytes;
983 	struct regpair rcv_vxlan_bytes;
984 	struct regpair rcv_geneve_bytes;
985 	struct regpair rcv_gre_pkts;
986 	struct regpair rcv_vxlan_pkts;
987 	struct regpair rcv_geneve_pkts;
988 };
989 
990 struct eth_ustorm_per_queue_stat {
991 	struct regpair rcv_ucast_bytes;
992 	struct regpair rcv_mcast_bytes;
993 	struct regpair rcv_bcast_bytes;
994 	struct regpair rcv_ucast_pkts;
995 	struct regpair rcv_mcast_pkts;
996 	struct regpair rcv_bcast_pkts;
997 };
998 
999 /* Event Ring VF-PF Channel data */
1000 struct vf_pf_channel_eqe_data {
1001 	struct regpair msg_addr;
1002 };
1003 
1004 /* Event Ring initial cleanup data */
1005 struct initial_cleanup_eqe_data {
1006 	u8 vf_id;
1007 	u8 reserved[7];
1008 };
1009 
1010 /* FW error data */
1011 struct fw_err_data {
1012 	u8 recovery_scope;
1013 	u8 err_id;
1014 	__le16 entity_id;
1015 	u8 reserved[4];
1016 };
1017 
1018 /* Event Data Union */
1019 union event_ring_data {
1020 	u8 bytes[8];
1021 	struct vf_pf_channel_eqe_data vf_pf_channel;
1022 	struct iscsi_eqe_data iscsi_info;
1023 	struct iscsi_connect_done_results iscsi_conn_done_info;
1024 	union rdma_eqe_data rdma_data;
1025 	struct initial_cleanup_eqe_data vf_init_cleanup;
1026 	struct fw_err_data err_data;
1027 };
1028 
1029 /* Event Ring Entry */
1030 struct event_ring_entry {
1031 	u8 protocol_id;
1032 	u8 opcode;
1033 	u8 reserved0;
1034 	u8 vf_id;
1035 	__le16 echo;
1036 	u8 fw_return_code;
1037 	u8 flags;
1038 #define EVENT_RING_ENTRY_ASYNC_MASK		0x1
1039 #define EVENT_RING_ENTRY_ASYNC_SHIFT		0
1040 #define EVENT_RING_ENTRY_RESERVED1_MASK		0x7F
1041 #define EVENT_RING_ENTRY_RESERVED1_SHIFT	1
1042 	union event_ring_data data;
1043 };
1044 
1045 /* Event Ring Next Page Address */
1046 struct event_ring_next_addr {
1047 	struct regpair addr;
1048 	__le32 reserved[2];
1049 };
1050 
1051 /* Event Ring Element */
1052 union event_ring_element {
1053 	struct event_ring_entry entry;
1054 	struct event_ring_next_addr next_addr;
1055 };
1056 
1057 /* Ports mode */
1058 enum fw_flow_ctrl_mode {
1059 	flow_ctrl_pause,
1060 	flow_ctrl_pfc,
1061 	MAX_FW_FLOW_CTRL_MODE
1062 };
1063 
1064 /* GFT profile type */
1065 enum gft_profile_type {
1066 	GFT_PROFILE_TYPE_4_TUPLE,
1067 	GFT_PROFILE_TYPE_L4_DST_PORT,
1068 	GFT_PROFILE_TYPE_IP_DST_ADDR,
1069 	GFT_PROFILE_TYPE_IP_SRC_ADDR,
1070 	GFT_PROFILE_TYPE_TUNNEL_TYPE,
1071 	MAX_GFT_PROFILE_TYPE
1072 };
1073 
1074 /* Major and Minor hsi Versions */
1075 struct hsi_fp_ver_struct {
1076 	u8 minor_ver_arr[2];
1077 	u8 major_ver_arr[2];
1078 };
1079 
1080 /* Integration Phase */
1081 enum integ_phase {
1082 	INTEG_PHASE_BB_A0_LATEST = 3,
1083 	INTEG_PHASE_BB_B0_NO_MCP = 10,
1084 	INTEG_PHASE_BB_B0_WITH_MCP = 11,
1085 	MAX_INTEG_PHASE
1086 };
1087 
1088 /* Ports mode */
1089 enum iwarp_ll2_tx_queues {
1090 	IWARP_LL2_IN_ORDER_TX_QUEUE = 1,
1091 	IWARP_LL2_ALIGNED_TX_QUEUE,
1092 	IWARP_LL2_ALIGNED_RIGHT_TRIMMED_TX_QUEUE,
1093 	IWARP_LL2_ERROR,
1094 	MAX_IWARP_LL2_TX_QUEUES
1095 };
1096 
1097 /* Function error ID */
1098 enum func_err_id {
1099 	FUNC_NO_ERROR,
1100 	VF_PF_CHANNEL_NOT_READY,
1101 	VF_ZONE_MSG_NOT_VALID,
1102 	VF_ZONE_FUNC_NOT_ENABLED,
1103 	ETH_PACKET_TOO_SMALL,
1104 	ETH_ILLEGAL_VLAN_MODE,
1105 	ETH_MTU_VIOLATION,
1106 	ETH_ILLEGAL_INBAND_TAGS,
1107 	ETH_VLAN_INSERT_AND_INBAND_VLAN,
1108 	ETH_ILLEGAL_NBDS,
1109 	ETH_FIRST_BD_WO_SOP,
1110 	ETH_INSUFFICIENT_BDS,
1111 	ETH_ILLEGAL_LSO_HDR_NBDS,
1112 	ETH_ILLEGAL_LSO_MSS,
1113 	ETH_ZERO_SIZE_BD,
1114 	ETH_ILLEGAL_LSO_HDR_LEN,
1115 	ETH_INSUFFICIENT_PAYLOAD,
1116 	ETH_EDPM_OUT_OF_SYNC,
1117 	ETH_TUNN_IPV6_EXT_NBD_ERR,
1118 	ETH_CONTROL_PACKET_VIOLATION,
1119 	ETH_ANTI_SPOOFING_ERR,
1120 	ETH_PACKET_SIZE_TOO_LARGE,
1121 	CORE_ILLEGAL_VLAN_MODE,
1122 	CORE_ILLEGAL_NBDS,
1123 	CORE_FIRST_BD_WO_SOP,
1124 	CORE_INSUFFICIENT_BDS,
1125 	CORE_PACKET_TOO_SMALL,
1126 	CORE_ILLEGAL_INBAND_TAGS,
1127 	CORE_VLAN_INSERT_AND_INBAND_VLAN,
1128 	CORE_MTU_VIOLATION,
1129 	CORE_CONTROL_PACKET_VIOLATION,
1130 	CORE_ANTI_SPOOFING_ERR,
1131 	CORE_PACKET_SIZE_TOO_LARGE,
1132 	CORE_ILLEGAL_BD_FLAGS,
1133 	CORE_GSI_PACKET_VIOLATION,
1134 	MAX_FUNC_ERR_ID
1135 };
1136 
1137 /* FW error handling mode */
1138 enum fw_err_mode {
1139 	FW_ERR_FATAL_ASSERT,
1140 	FW_ERR_DRV_REPORT,
1141 	MAX_FW_ERR_MODE
1142 };
1143 
1144 /* FW error recovery scope */
1145 enum fw_err_recovery_scope {
1146 	ERR_SCOPE_INVALID,
1147 	ERR_SCOPE_TX_Q,
1148 	ERR_SCOPE_RX_Q,
1149 	ERR_SCOPE_QP,
1150 	ERR_SCOPE_VPORT,
1151 	ERR_SCOPE_FUNC,
1152 	ERR_SCOPE_PORT,
1153 	ERR_SCOPE_ENGINE,
1154 	MAX_FW_ERR_RECOVERY_SCOPE
1155 };
1156 
1157 /* Mstorm non-triggering VF zone */
1158 struct mstorm_non_trigger_vf_zone {
1159 	struct eth_mstorm_per_queue_stat eth_queue_stat;
1160 	struct eth_rx_prod_data eth_rx_queue_producers[ETH_MAX_RXQ_VF_QUAD];
1161 };
1162 
1163 /* Mstorm VF zone */
1164 struct mstorm_vf_zone {
1165 	struct mstorm_non_trigger_vf_zone non_trigger;
1166 };
1167 
1168 /* vlan header including TPID and TCI fields */
1169 struct vlan_header {
1170 	__le16 tpid;
1171 	__le16 tci;
1172 };
1173 
1174 /* outer tag configurations */
1175 struct outer_tag_config_struct {
1176 	u8 enable_stag_pri_change;
1177 	u8 pri_map_valid;
1178 	u8 reserved[2];
1179 	struct vlan_header outer_tag;
1180 	u8 inner_to_outer_pri_map[8];
1181 };
1182 
1183 /* personality per PF */
1184 enum personality_type {
1185 	BAD_PERSONALITY_TYP,
1186 	PERSONALITY_TCP_ULP,
1187 	PERSONALITY_FCOE,
1188 	PERSONALITY_RDMA_AND_ETH,
1189 	PERSONALITY_RDMA,
1190 	PERSONALITY_CORE,
1191 	PERSONALITY_ETH,
1192 	PERSONALITY_RESERVED,
1193 	MAX_PERSONALITY_TYPE
1194 };
1195 
1196 /* tunnel configuration */
1197 struct pf_start_tunnel_config {
1198 	u8 set_vxlan_udp_port_flg;
1199 	u8 set_geneve_udp_port_flg;
1200 	u8 set_no_inner_l2_vxlan_udp_port_flg;
1201 	u8 tunnel_clss_vxlan;
1202 	u8 tunnel_clss_l2geneve;
1203 	u8 tunnel_clss_ipgeneve;
1204 	u8 tunnel_clss_l2gre;
1205 	u8 tunnel_clss_ipgre;
1206 	__le16 vxlan_udp_port;
1207 	__le16 geneve_udp_port;
1208 	__le16 no_inner_l2_vxlan_udp_port;
1209 	__le16 reserved[3];
1210 };
1211 
1212 /* Ramrod data for PF start ramrod */
1213 struct pf_start_ramrod_data {
1214 	struct regpair event_ring_pbl_addr;
1215 	struct regpair consolid_q_pbl_base_addr;
1216 	struct pf_start_tunnel_config tunnel_config;
1217 	__le16 event_ring_sb_id;
1218 	u8 base_vf_id;
1219 	u8 num_vfs;
1220 	u8 event_ring_num_pages;
1221 	u8 event_ring_sb_index;
1222 	u8 path_id;
1223 	u8 warning_as_error;
1224 	u8 dont_log_ramrods;
1225 	u8 personality;
1226 	__le16 log_type_mask;
1227 	u8 mf_mode;
1228 	u8 integ_phase;
1229 	u8 allow_npar_tx_switching;
1230 	u8 reserved0;
1231 	struct hsi_fp_ver_struct hsi_fp_ver;
1232 	struct outer_tag_config_struct outer_tag_config;
1233 	u8 pf_fp_err_mode;
1234 	u8 consolid_q_num_pages;
1235 	u8 reserved[6];
1236 };
1237 
1238 /* Data for port update ramrod */
1239 struct protocol_dcb_data {
1240 	u8 dcb_enable_flag;
1241 	u8 dscp_enable_flag;
1242 	u8 dcb_priority;
1243 	u8 dcb_tc;
1244 	u8 dscp_val;
1245 	u8 dcb_dont_add_vlan0;
1246 };
1247 
1248 /* Update tunnel configuration */
1249 struct pf_update_tunnel_config {
1250 	u8 update_rx_pf_clss;
1251 	u8 update_rx_def_ucast_clss;
1252 	u8 update_rx_def_non_ucast_clss;
1253 	u8 set_vxlan_udp_port_flg;
1254 	u8 set_geneve_udp_port_flg;
1255 	u8 set_no_inner_l2_vxlan_udp_port_flg;
1256 	u8 tunnel_clss_vxlan;
1257 	u8 tunnel_clss_l2geneve;
1258 	u8 tunnel_clss_ipgeneve;
1259 	u8 tunnel_clss_l2gre;
1260 	u8 tunnel_clss_ipgre;
1261 	u8 reserved;
1262 	__le16 vxlan_udp_port;
1263 	__le16 geneve_udp_port;
1264 	__le16 no_inner_l2_vxlan_udp_port;
1265 	__le16 reserved1[3];
1266 };
1267 
1268 /* Data for port update ramrod */
1269 struct pf_update_ramrod_data {
1270 	u8 update_eth_dcb_data_mode;
1271 	u8 update_fcoe_dcb_data_mode;
1272 	u8 update_iscsi_dcb_data_mode;
1273 	u8 update_roce_dcb_data_mode;
1274 	u8 update_rroce_dcb_data_mode;
1275 	u8 update_iwarp_dcb_data_mode;
1276 	u8 update_mf_vlan_flag;
1277 	u8 update_enable_stag_pri_change;
1278 	struct protocol_dcb_data eth_dcb_data;
1279 	struct protocol_dcb_data fcoe_dcb_data;
1280 	struct protocol_dcb_data iscsi_dcb_data;
1281 	struct protocol_dcb_data roce_dcb_data;
1282 	struct protocol_dcb_data rroce_dcb_data;
1283 	struct protocol_dcb_data iwarp_dcb_data;
1284 	__le16 mf_vlan;
1285 	u8 enable_stag_pri_change;
1286 	u8 reserved;
1287 	struct pf_update_tunnel_config tunnel_config;
1288 };
1289 
1290 /* Ports mode */
1291 enum ports_mode {
1292 	ENGX2_PORTX1,
1293 	ENGX2_PORTX2,
1294 	ENGX1_PORTX1,
1295 	ENGX1_PORTX2,
1296 	ENGX1_PORTX4,
1297 	MAX_PORTS_MODE
1298 };
1299 
1300 /* Protocol-common error code */
1301 enum protocol_common_error_code {
1302 	COMMON_ERR_CODE_OK = 0,
1303 	COMMON_ERR_CODE_ERROR,
1304 	MAX_PROTOCOL_COMMON_ERROR_CODE
1305 };
1306 
1307 /* use to index in hsi_fp_[major|minor]_ver_arr per protocol */
1308 enum protocol_version_array_key {
1309 	ETH_VER_KEY = 0,
1310 	ROCE_VER_KEY,
1311 	MAX_PROTOCOL_VERSION_ARRAY_KEY
1312 };
1313 
1314 /* RDMA TX Stats */
1315 struct rdma_sent_stats {
1316 	struct regpair sent_bytes;
1317 	struct regpair sent_pkts;
1318 };
1319 
1320 /* Pstorm non-triggering VF zone */
1321 struct pstorm_non_trigger_vf_zone {
1322 	struct eth_pstorm_per_queue_stat eth_queue_stat;
1323 	struct rdma_sent_stats rdma_stats;
1324 };
1325 
1326 /* Pstorm VF zone */
1327 struct pstorm_vf_zone {
1328 	struct pstorm_non_trigger_vf_zone non_trigger;
1329 	struct regpair reserved[7];
1330 };
1331 
1332 /* Ramrod Header of SPQE */
1333 struct ramrod_header {
1334 	__le32 cid;
1335 	u8 cmd_id;
1336 	u8 protocol_id;
1337 	__le16 echo;
1338 };
1339 
1340 /* RDMA RX Stats */
1341 struct rdma_rcv_stats {
1342 	struct regpair rcv_bytes;
1343 	struct regpair rcv_pkts;
1344 };
1345 
1346 /* Data for update QCN/DCQCN RL ramrod */
1347 struct rl_update_ramrod_data {
1348 	u8 qcn_update_param_flg;
1349 	u8 dcqcn_update_param_flg;
1350 	u8 rl_init_flg;
1351 	u8 rl_start_flg;
1352 	u8 rl_stop_flg;
1353 	u8 rl_id_first;
1354 	u8 rl_id_last;
1355 	u8 rl_dc_qcn_flg;
1356 	u8 dcqcn_reset_alpha_on_idle;
1357 	u8 rl_bc_stage_th;
1358 	u8 rl_timer_stage_th;
1359 	u8 reserved1;
1360 	__le32 rl_bc_rate;
1361 	__le16 rl_max_rate;
1362 	__le16 rl_r_ai;
1363 	__le16 rl_r_hai;
1364 	__le16 dcqcn_g;
1365 	__le32 dcqcn_k_us;
1366 	__le32 dcqcn_timeuot_us;
1367 	__le32 qcn_timeuot_us;
1368 	__le32 reserved2;
1369 };
1370 
1371 /* Slowpath Element (SPQE) */
1372 struct slow_path_element {
1373 	struct ramrod_header hdr;
1374 	struct regpair data_ptr;
1375 };
1376 
1377 /* Tstorm non-triggering VF zone */
1378 struct tstorm_non_trigger_vf_zone {
1379 	struct rdma_rcv_stats rdma_stats;
1380 };
1381 
1382 struct tstorm_per_port_stat {
1383 	struct regpair trunc_error_discard;
1384 	struct regpair mac_error_discard;
1385 	struct regpair mftag_filter_discard;
1386 	struct regpair eth_mac_filter_discard;
1387 	struct regpair ll2_mac_filter_discard;
1388 	struct regpair ll2_conn_disabled_discard;
1389 	struct regpair iscsi_irregular_pkt;
1390 	struct regpair fcoe_irregular_pkt;
1391 	struct regpair roce_irregular_pkt;
1392 	struct regpair iwarp_irregular_pkt;
1393 	struct regpair eth_irregular_pkt;
1394 	struct regpair toe_irregular_pkt;
1395 	struct regpair preroce_irregular_pkt;
1396 	struct regpair eth_gre_tunn_filter_discard;
1397 	struct regpair eth_vxlan_tunn_filter_discard;
1398 	struct regpair eth_geneve_tunn_filter_discard;
1399 	struct regpair eth_gft_drop_pkt;
1400 };
1401 
1402 /* Tstorm VF zone */
1403 struct tstorm_vf_zone {
1404 	struct tstorm_non_trigger_vf_zone non_trigger;
1405 };
1406 
1407 /* Tunnel classification scheme */
1408 enum tunnel_clss {
1409 	TUNNEL_CLSS_MAC_VLAN = 0,
1410 	TUNNEL_CLSS_MAC_VNI,
1411 	TUNNEL_CLSS_INNER_MAC_VLAN,
1412 	TUNNEL_CLSS_INNER_MAC_VNI,
1413 	TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE,
1414 	MAX_TUNNEL_CLSS
1415 };
1416 
1417 /* Ustorm non-triggering VF zone */
1418 struct ustorm_non_trigger_vf_zone {
1419 	struct eth_ustorm_per_queue_stat eth_queue_stat;
1420 	struct regpair vf_pf_msg_addr;
1421 };
1422 
1423 /* Ustorm triggering VF zone */
1424 struct ustorm_trigger_vf_zone {
1425 	u8 vf_pf_msg_valid;
1426 	u8 reserved[7];
1427 };
1428 
1429 /* Ustorm VF zone */
1430 struct ustorm_vf_zone {
1431 	struct ustorm_non_trigger_vf_zone non_trigger;
1432 	struct ustorm_trigger_vf_zone trigger;
1433 };
1434 
1435 /* VF-PF channel data */
1436 struct vf_pf_channel_data {
1437 	__le32 ready;
1438 	u8 valid;
1439 	u8 reserved0;
1440 	__le16 reserved1;
1441 };
1442 
1443 /* Ramrod data for VF start ramrod */
1444 struct vf_start_ramrod_data {
1445 	u8 vf_id;
1446 	u8 enable_flr_ack;
1447 	__le16 opaque_fid;
1448 	u8 personality;
1449 	u8 reserved[7];
1450 	struct hsi_fp_ver_struct hsi_fp_ver;
1451 
1452 };
1453 
1454 /* Ramrod data for VF start ramrod */
1455 struct vf_stop_ramrod_data {
1456 	u8 vf_id;
1457 	u8 reserved0;
1458 	__le16 reserved1;
1459 	__le32 reserved2;
1460 };
1461 
1462 /* VF zone size mode */
1463 enum vf_zone_size_mode {
1464 	VF_ZONE_SIZE_MODE_DEFAULT,
1465 	VF_ZONE_SIZE_MODE_DOUBLE,
1466 	VF_ZONE_SIZE_MODE_QUAD,
1467 	MAX_VF_ZONE_SIZE_MODE
1468 };
1469 
1470 /* Xstorm non-triggering VF zone */
1471 struct xstorm_non_trigger_vf_zone {
1472 	struct regpair non_edpm_ack_pkts;
1473 };
1474 
1475 /* Tstorm VF zone */
1476 struct xstorm_vf_zone {
1477 	struct xstorm_non_trigger_vf_zone non_trigger;
1478 };
1479 
1480 /* Attentions status block */
1481 struct atten_status_block {
1482 	__le32 atten_bits;
1483 	__le32 atten_ack;
1484 	__le16 reserved0;
1485 	__le16 sb_index;
1486 	__le32 reserved1;
1487 };
1488 
1489 /* DMAE command */
1490 struct dmae_cmd {
1491 	__le32 opcode;
1492 #define DMAE_CMD_SRC_MASK		0x1
1493 #define DMAE_CMD_SRC_SHIFT		0
1494 #define DMAE_CMD_DST_MASK		0x3
1495 #define DMAE_CMD_DST_SHIFT		1
1496 #define DMAE_CMD_C_DST_MASK		0x1
1497 #define DMAE_CMD_C_DST_SHIFT		3
1498 #define DMAE_CMD_CRC_RESET_MASK		0x1
1499 #define DMAE_CMD_CRC_RESET_SHIFT	4
1500 #define DMAE_CMD_SRC_ADDR_RESET_MASK	0x1
1501 #define DMAE_CMD_SRC_ADDR_RESET_SHIFT	5
1502 #define DMAE_CMD_DST_ADDR_RESET_MASK	0x1
1503 #define DMAE_CMD_DST_ADDR_RESET_SHIFT	6
1504 #define DMAE_CMD_COMP_FUNC_MASK		0x1
1505 #define DMAE_CMD_COMP_FUNC_SHIFT	7
1506 #define DMAE_CMD_COMP_WORD_EN_MASK	0x1
1507 #define DMAE_CMD_COMP_WORD_EN_SHIFT	8
1508 #define DMAE_CMD_COMP_CRC_EN_MASK	0x1
1509 #define DMAE_CMD_COMP_CRC_EN_SHIFT	9
1510 #define DMAE_CMD_COMP_CRC_OFFSET_MASK	0x7
1511 #define DMAE_CMD_COMP_CRC_OFFSET_SHIFT 10
1512 #define DMAE_CMD_RESERVED1_MASK		0x1
1513 #define DMAE_CMD_RESERVED1_SHIFT	13
1514 #define DMAE_CMD_ENDIANITY_MODE_MASK	0x3
1515 #define DMAE_CMD_ENDIANITY_MODE_SHIFT	14
1516 #define DMAE_CMD_ERR_HANDLING_MASK	0x3
1517 #define DMAE_CMD_ERR_HANDLING_SHIFT	16
1518 #define DMAE_CMD_PORT_ID_MASK		0x3
1519 #define DMAE_CMD_PORT_ID_SHIFT		18
1520 #define DMAE_CMD_SRC_PF_ID_MASK		0xF
1521 #define DMAE_CMD_SRC_PF_ID_SHIFT	20
1522 #define DMAE_CMD_DST_PF_ID_MASK		0xF
1523 #define DMAE_CMD_DST_PF_ID_SHIFT	24
1524 #define DMAE_CMD_SRC_VF_ID_VALID_MASK	0x1
1525 #define DMAE_CMD_SRC_VF_ID_VALID_SHIFT 28
1526 #define DMAE_CMD_DST_VF_ID_VALID_MASK	0x1
1527 #define DMAE_CMD_DST_VF_ID_VALID_SHIFT 29
1528 #define DMAE_CMD_RESERVED2_MASK		0x3
1529 #define DMAE_CMD_RESERVED2_SHIFT	30
1530 	__le32 src_addr_lo;
1531 	__le32 src_addr_hi;
1532 	__le32 dst_addr_lo;
1533 	__le32 dst_addr_hi;
1534 	__le16 length_dw;
1535 	__le16 opcode_b;
1536 #define DMAE_CMD_SRC_VF_ID_MASK		0xFF
1537 #define DMAE_CMD_SRC_VF_ID_SHIFT	0
1538 #define DMAE_CMD_DST_VF_ID_MASK		0xFF
1539 #define DMAE_CMD_DST_VF_ID_SHIFT	8
1540 	__le32 comp_addr_lo;
1541 	__le32 comp_addr_hi;
1542 	__le32 comp_val;
1543 	__le32 crc32;
1544 	__le32 crc_32_c;
1545 	__le16 crc16;
1546 	__le16 crc16_c;
1547 	__le16 crc10;
1548 	__le16 error_bit_reserved;
1549 #define DMAE_CMD_ERROR_BIT_MASK        0x1
1550 #define DMAE_CMD_ERROR_BIT_SHIFT       0
1551 #define DMAE_CMD_RESERVED_MASK	       0x7FFF
1552 #define DMAE_CMD_RESERVED_SHIFT        1
1553 	__le16 xsum16;
1554 	__le16 xsum8;
1555 };
1556 
1557 enum dmae_cmd_comp_crc_en_enum {
1558 	dmae_cmd_comp_crc_disabled,
1559 	dmae_cmd_comp_crc_enabled,
1560 	MAX_DMAE_CMD_COMP_CRC_EN_ENUM
1561 };
1562 
1563 enum dmae_cmd_comp_func_enum {
1564 	dmae_cmd_comp_func_to_src,
1565 	dmae_cmd_comp_func_to_dst,
1566 	MAX_DMAE_CMD_COMP_FUNC_ENUM
1567 };
1568 
1569 enum dmae_cmd_comp_word_en_enum {
1570 	dmae_cmd_comp_word_disabled,
1571 	dmae_cmd_comp_word_enabled,
1572 	MAX_DMAE_CMD_COMP_WORD_EN_ENUM
1573 };
1574 
1575 enum dmae_cmd_c_dst_enum {
1576 	dmae_cmd_c_dst_pcie,
1577 	dmae_cmd_c_dst_grc,
1578 	MAX_DMAE_CMD_C_DST_ENUM
1579 };
1580 
1581 enum dmae_cmd_dst_enum {
1582 	dmae_cmd_dst_none_0,
1583 	dmae_cmd_dst_pcie,
1584 	dmae_cmd_dst_grc,
1585 	dmae_cmd_dst_none_3,
1586 	MAX_DMAE_CMD_DST_ENUM
1587 };
1588 
1589 enum dmae_cmd_error_handling_enum {
1590 	dmae_cmd_error_handling_send_regular_comp,
1591 	dmae_cmd_error_handling_send_comp_with_err,
1592 	dmae_cmd_error_handling_dont_send_comp,
1593 	MAX_DMAE_CMD_ERROR_HANDLING_ENUM
1594 };
1595 
1596 enum dmae_cmd_src_enum {
1597 	dmae_cmd_src_pcie,
1598 	dmae_cmd_src_grc,
1599 	MAX_DMAE_CMD_SRC_ENUM
1600 };
1601 
1602 struct mstorm_core_conn_ag_ctx {
1603 	u8 byte0;
1604 	u8 byte1;
1605 	u8 flags0;
1606 #define MSTORM_CORE_CONN_AG_CTX_BIT0_MASK	0x1
1607 #define MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT	0
1608 #define MSTORM_CORE_CONN_AG_CTX_BIT1_MASK	0x1
1609 #define MSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT	1
1610 #define MSTORM_CORE_CONN_AG_CTX_CF0_MASK	0x3
1611 #define MSTORM_CORE_CONN_AG_CTX_CF0_SHIFT	2
1612 #define MSTORM_CORE_CONN_AG_CTX_CF1_MASK	0x3
1613 #define MSTORM_CORE_CONN_AG_CTX_CF1_SHIFT	4
1614 #define MSTORM_CORE_CONN_AG_CTX_CF2_MASK	0x3
1615 #define MSTORM_CORE_CONN_AG_CTX_CF2_SHIFT	6
1616 	u8 flags1;
1617 #define MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK		0x1
1618 #define MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT		0
1619 #define MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK		0x1
1620 #define MSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT		1
1621 #define MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK		0x1
1622 #define MSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT		2
1623 #define MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK		0x1
1624 #define MSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT	3
1625 #define MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK		0x1
1626 #define MSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT	4
1627 #define MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK		0x1
1628 #define MSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT	5
1629 #define MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK		0x1
1630 #define MSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT	6
1631 #define MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK		0x1
1632 #define MSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT	7
1633 	__le16 word0;
1634 	__le16 word1;
1635 	__le32 reg0;
1636 	__le32 reg1;
1637 };
1638 
1639 struct ystorm_core_conn_ag_ctx {
1640 	u8 byte0;
1641 	u8 byte1;
1642 	u8 flags0;
1643 #define YSTORM_CORE_CONN_AG_CTX_BIT0_MASK	0x1
1644 #define YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT	0
1645 #define YSTORM_CORE_CONN_AG_CTX_BIT1_MASK	0x1
1646 #define YSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT	1
1647 #define YSTORM_CORE_CONN_AG_CTX_CF0_MASK	0x3
1648 #define YSTORM_CORE_CONN_AG_CTX_CF0_SHIFT	2
1649 #define YSTORM_CORE_CONN_AG_CTX_CF1_MASK	0x3
1650 #define YSTORM_CORE_CONN_AG_CTX_CF1_SHIFT	4
1651 #define YSTORM_CORE_CONN_AG_CTX_CF2_MASK	0x3
1652 #define YSTORM_CORE_CONN_AG_CTX_CF2_SHIFT	6
1653 	u8 flags1;
1654 #define YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK		0x1
1655 #define YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT		0
1656 #define YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK		0x1
1657 #define YSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT		1
1658 #define YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK		0x1
1659 #define YSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT		2
1660 #define YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK		0x1
1661 #define YSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT	3
1662 #define YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK		0x1
1663 #define YSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT	4
1664 #define YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK		0x1
1665 #define YSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT	5
1666 #define YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK		0x1
1667 #define YSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT	6
1668 #define YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK		0x1
1669 #define YSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT	7
1670 	u8 byte2;
1671 	u8 byte3;
1672 	__le16 word0;
1673 	__le32 reg0;
1674 	__le32 reg1;
1675 	__le16 word1;
1676 	__le16 word2;
1677 	__le16 word3;
1678 	__le16 word4;
1679 	__le32 reg2;
1680 	__le32 reg3;
1681 };
1682 
1683 /* DMAE parameters */
1684 struct qed_dmae_params {
1685 	u32 flags;
1686 /* If QED_DMAE_PARAMS_RW_REPL_SRC flag is set and the
1687  * source is a block of length DMAE_MAX_RW_SIZE and the
1688  * destination is larger, the source block will be duplicated as
1689  * many times as required to fill the destination block. This is
1690  * used mostly to write a zeroed buffer to destination address
1691  * using DMA
1692  */
1693 #define QED_DMAE_PARAMS_RW_REPL_SRC_MASK	0x1
1694 #define QED_DMAE_PARAMS_RW_REPL_SRC_SHIFT	0
1695 #define QED_DMAE_PARAMS_SRC_VF_VALID_MASK	0x1
1696 #define QED_DMAE_PARAMS_SRC_VF_VALID_SHIFT	1
1697 #define QED_DMAE_PARAMS_DST_VF_VALID_MASK	0x1
1698 #define QED_DMAE_PARAMS_DST_VF_VALID_SHIFT	2
1699 #define QED_DMAE_PARAMS_COMPLETION_DST_MASK	0x1
1700 #define QED_DMAE_PARAMS_COMPLETION_DST_SHIFT	3
1701 #define QED_DMAE_PARAMS_PORT_VALID_MASK		0x1
1702 #define QED_DMAE_PARAMS_PORT_VALID_SHIFT	4
1703 #define QED_DMAE_PARAMS_SRC_PF_VALID_MASK	0x1
1704 #define QED_DMAE_PARAMS_SRC_PF_VALID_SHIFT	5
1705 #define QED_DMAE_PARAMS_DST_PF_VALID_MASK	0x1
1706 #define QED_DMAE_PARAMS_DST_PF_VALID_SHIFT	6
1707 #define QED_DMAE_PARAMS_RESERVED_MASK		0x1FFFFFF
1708 #define QED_DMAE_PARAMS_RESERVED_SHIFT		7
1709 	u8 src_vfid;
1710 	u8 dst_vfid;
1711 	u8 port_id;
1712 	u8 src_pfid;
1713 	u8 dst_pfid;
1714 	u8 reserved1;
1715 	__le16 reserved2;
1716 };
1717 
1718 /* IGU cleanup command */
1719 struct igu_cleanup {
1720 	__le32 sb_id_and_flags;
1721 #define IGU_CLEANUP_RESERVED0_MASK	0x7FFFFFF
1722 #define IGU_CLEANUP_RESERVED0_SHIFT	0
1723 #define IGU_CLEANUP_CLEANUP_SET_MASK	0x1
1724 #define IGU_CLEANUP_CLEANUP_SET_SHIFT	27
1725 #define IGU_CLEANUP_CLEANUP_TYPE_MASK	0x7
1726 #define IGU_CLEANUP_CLEANUP_TYPE_SHIFT	28
1727 #define IGU_CLEANUP_COMMAND_TYPE_MASK	0x1
1728 #define IGU_CLEANUP_COMMAND_TYPE_SHIFT	31
1729 	__le32 reserved1;
1730 };
1731 
1732 /* IGU firmware driver command */
1733 union igu_command {
1734 	struct igu_prod_cons_update prod_cons_update;
1735 	struct igu_cleanup cleanup;
1736 };
1737 
1738 /* IGU firmware driver command */
1739 struct igu_command_reg_ctrl {
1740 	__le16 opaque_fid;
1741 	__le16 igu_command_reg_ctrl_fields;
1742 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_MASK	0xFFF
1743 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_SHIFT	0
1744 #define IGU_COMMAND_REG_CTRL_RESERVED_MASK	0x7
1745 #define IGU_COMMAND_REG_CTRL_RESERVED_SHIFT	12
1746 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_MASK	0x1
1747 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_SHIFT	15
1748 };
1749 
1750 /* IGU mapping line structure */
1751 struct igu_mapping_line {
1752 	__le32 igu_mapping_line_fields;
1753 #define IGU_MAPPING_LINE_VALID_MASK		0x1
1754 #define IGU_MAPPING_LINE_VALID_SHIFT		0
1755 #define IGU_MAPPING_LINE_VECTOR_NUMBER_MASK	0xFF
1756 #define IGU_MAPPING_LINE_VECTOR_NUMBER_SHIFT	1
1757 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_MASK	0xFF
1758 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_SHIFT	9
1759 #define IGU_MAPPING_LINE_PF_VALID_MASK		0x1
1760 #define IGU_MAPPING_LINE_PF_VALID_SHIFT		17
1761 #define IGU_MAPPING_LINE_IPS_GROUP_MASK		0x3F
1762 #define IGU_MAPPING_LINE_IPS_GROUP_SHIFT	18
1763 #define IGU_MAPPING_LINE_RESERVED_MASK		0xFF
1764 #define IGU_MAPPING_LINE_RESERVED_SHIFT		24
1765 };
1766 
1767 /* IGU MSIX line structure */
1768 struct igu_msix_vector {
1769 	struct regpair address;
1770 	__le32 data;
1771 	__le32 msix_vector_fields;
1772 #define IGU_MSIX_VECTOR_MASK_BIT_MASK		0x1
1773 #define IGU_MSIX_VECTOR_MASK_BIT_SHIFT		0
1774 #define IGU_MSIX_VECTOR_RESERVED0_MASK		0x7FFF
1775 #define IGU_MSIX_VECTOR_RESERVED0_SHIFT		1
1776 #define IGU_MSIX_VECTOR_STEERING_TAG_MASK	0xFF
1777 #define IGU_MSIX_VECTOR_STEERING_TAG_SHIFT	16
1778 #define IGU_MSIX_VECTOR_RESERVED1_MASK		0xFF
1779 #define IGU_MSIX_VECTOR_RESERVED1_SHIFT		24
1780 };
1781 
1782 /* per encapsulation type enabling flags */
1783 struct prs_reg_encapsulation_type_en {
1784 	u8 flags;
1785 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_MASK		0x1
1786 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT		0
1787 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_MASK		0x1
1788 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT		1
1789 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_MASK			0x1
1790 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT		2
1791 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_MASK			0x1
1792 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_SHIFT		3
1793 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_MASK	0x1
1794 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT	4
1795 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_MASK	0x1
1796 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT	5
1797 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK			0x3
1798 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_SHIFT			6
1799 };
1800 
1801 enum pxp_tph_st_hint {
1802 	TPH_ST_HINT_BIDIR,
1803 	TPH_ST_HINT_REQUESTER,
1804 	TPH_ST_HINT_TARGET,
1805 	TPH_ST_HINT_TARGET_PRIO,
1806 	MAX_PXP_TPH_ST_HINT
1807 };
1808 
1809 /* QM hardware structure of enable bypass credit mask */
1810 struct qm_rf_bypass_mask {
1811 	u8 flags;
1812 #define QM_RF_BYPASS_MASK_LINEVOQ_MASK		0x1
1813 #define QM_RF_BYPASS_MASK_LINEVOQ_SHIFT		0
1814 #define QM_RF_BYPASS_MASK_RESERVED0_MASK	0x1
1815 #define QM_RF_BYPASS_MASK_RESERVED0_SHIFT	1
1816 #define QM_RF_BYPASS_MASK_PFWFQ_MASK		0x1
1817 #define QM_RF_BYPASS_MASK_PFWFQ_SHIFT		2
1818 #define QM_RF_BYPASS_MASK_VPWFQ_MASK		0x1
1819 #define QM_RF_BYPASS_MASK_VPWFQ_SHIFT		3
1820 #define QM_RF_BYPASS_MASK_PFRL_MASK		0x1
1821 #define QM_RF_BYPASS_MASK_PFRL_SHIFT		4
1822 #define QM_RF_BYPASS_MASK_VPQCNRL_MASK		0x1
1823 #define QM_RF_BYPASS_MASK_VPQCNRL_SHIFT		5
1824 #define QM_RF_BYPASS_MASK_FWPAUSE_MASK		0x1
1825 #define QM_RF_BYPASS_MASK_FWPAUSE_SHIFT		6
1826 #define QM_RF_BYPASS_MASK_RESERVED1_MASK	0x1
1827 #define QM_RF_BYPASS_MASK_RESERVED1_SHIFT	7
1828 };
1829 
1830 /* QM hardware structure of opportunistic credit mask */
1831 struct qm_rf_opportunistic_mask {
1832 	__le16 flags;
1833 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_MASK		0x1
1834 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT		0
1835 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_MASK		0x1
1836 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_SHIFT		1
1837 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_MASK		0x1
1838 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_SHIFT		2
1839 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_MASK		0x1
1840 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_SHIFT		3
1841 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_MASK		0x1
1842 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_SHIFT		4
1843 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_MASK		0x1
1844 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_SHIFT		5
1845 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_MASK		0x1
1846 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_SHIFT		6
1847 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_MASK		0x1
1848 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_SHIFT	7
1849 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_MASK	0x1
1850 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT	8
1851 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_MASK		0x7F
1852 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_SHIFT	9
1853 };
1854 
1855 /* QM hardware structure of QM map memory */
1856 struct qm_rf_pq_map {
1857 	__le32 reg;
1858 #define QM_RF_PQ_MAP_PQ_VALID_MASK		0x1
1859 #define QM_RF_PQ_MAP_PQ_VALID_SHIFT		0
1860 #define QM_RF_PQ_MAP_RL_ID_MASK		0xFF
1861 #define QM_RF_PQ_MAP_RL_ID_SHIFT		1
1862 #define QM_RF_PQ_MAP_VP_PQ_ID_MASK		0x1FF
1863 #define QM_RF_PQ_MAP_VP_PQ_ID_SHIFT		9
1864 #define QM_RF_PQ_MAP_VOQ_MASK		0x1F
1865 #define QM_RF_PQ_MAP_VOQ_SHIFT		18
1866 #define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_MASK	0x3
1867 #define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_SHIFT	23
1868 #define QM_RF_PQ_MAP_RL_VALID_MASK		0x1
1869 #define QM_RF_PQ_MAP_RL_VALID_SHIFT		25
1870 #define QM_RF_PQ_MAP_RESERVED_MASK		0x3F
1871 #define QM_RF_PQ_MAP_RESERVED_SHIFT		26
1872 };
1873 
1874 /* Completion params for aggregated interrupt completion */
1875 struct sdm_agg_int_comp_params {
1876 	__le16 params;
1877 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_MASK	0x3F
1878 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT	0
1879 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_MASK	0x1
1880 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT	6
1881 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_MASK	0x1FF
1882 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT	7
1883 };
1884 
1885 /* SDM operation gen command (generate aggregative interrupt) */
1886 struct sdm_op_gen {
1887 	__le32 command;
1888 #define SDM_OP_GEN_COMP_PARAM_MASK	0xFFFF
1889 #define SDM_OP_GEN_COMP_PARAM_SHIFT	0
1890 #define SDM_OP_GEN_COMP_TYPE_MASK	0xF
1891 #define SDM_OP_GEN_COMP_TYPE_SHIFT	16
1892 #define SDM_OP_GEN_RESERVED_MASK	0xFFF
1893 #define SDM_OP_GEN_RESERVED_SHIFT	20
1894 };
1895 
1896 /* Physical memory descriptor */
1897 struct phys_mem_desc {
1898 	dma_addr_t phys_addr;
1899 	void *virt_addr;
1900 	u32 size;		/* In bytes */
1901 };
1902 
1903 /* Virtual memory descriptor */
1904 struct virt_mem_desc {
1905 	void *ptr;
1906 	u32 size;		/* In bytes */
1907 };
1908 
1909 /********************************/
1910 /* HSI Init Functions constants */
1911 /********************************/
1912 
1913 /* Number of VLAN priorities */
1914 #define NUM_OF_VLAN_PRIORITIES	8
1915 
1916 /* BRB RAM init requirements */
1917 struct init_brb_ram_req {
1918 	u32 guranteed_per_tc;
1919 	u32 headroom_per_tc;
1920 	u32 min_pkt_size;
1921 	u32 max_ports_per_engine;
1922 	u8 num_active_tcs[MAX_NUM_PORTS];
1923 };
1924 
1925 /* ETS per-TC init requirements */
1926 struct init_ets_tc_req {
1927 	u8 use_sp;
1928 	u8 use_wfq;
1929 	u16 weight;
1930 };
1931 
1932 /* ETS init requirements */
1933 struct init_ets_req {
1934 	u32 mtu;
1935 	struct init_ets_tc_req tc_req[NUM_OF_TCS];
1936 };
1937 
1938 /* NIG LB RL init requirements */
1939 struct init_nig_lb_rl_req {
1940 	u16 lb_mac_rate;
1941 	u16 lb_rate;
1942 	u32 mtu;
1943 	u16 tc_rate[NUM_OF_PHYS_TCS];
1944 };
1945 
1946 /* NIG TC mapping for each priority */
1947 struct init_nig_pri_tc_map_entry {
1948 	u8 tc_id;
1949 	u8 valid;
1950 };
1951 
1952 /* NIG priority to TC map init requirements */
1953 struct init_nig_pri_tc_map_req {
1954 	struct init_nig_pri_tc_map_entry pri[NUM_OF_VLAN_PRIORITIES];
1955 };
1956 
1957 /* QM per global RL init parameters */
1958 struct init_qm_global_rl_params {
1959 	u8 type;
1960 	u8 reserved0;
1961 	u16 reserved1;
1962 	u32 rate_limit;
1963 };
1964 
1965 /* QM per-port init parameters */
1966 struct init_qm_port_params {
1967 	u16 active_phys_tcs;
1968 	u16 num_pbf_cmd_lines;
1969 	u16 num_btb_blocks;
1970 	u8 active;
1971 	u8 reserved;
1972 };
1973 
1974 /* QM per-PQ init parameters */
1975 struct init_qm_pq_params {
1976 	u16 vport_id;
1977 	u16 rl_id;
1978 	u8 rl_valid;
1979 	u8 tc_id;
1980 	u8 wrr_group;
1981 	u8 port_id;
1982 };
1983 
1984 /* QM per RL init parameters */
1985 struct init_qm_rl_params {
1986 	u32 vport_rl;
1987 	u8 vport_rl_type;
1988 	u8 reserved[3];
1989 };
1990 
1991 /* QM Rate Limiter types */
1992 enum init_qm_rl_type {
1993 	QM_RL_TYPE_NORMAL,
1994 	QM_RL_TYPE_QCN,
1995 	MAX_INIT_QM_RL_TYPE
1996 };
1997 
1998 /* QM per-vport init parameters */
1999 struct init_qm_vport_params {
2000 	u16 wfq;
2001 	u16 reserved;
2002 	u16 tc_wfq[NUM_OF_TCS];
2003 	u16 first_tx_pq_id[NUM_OF_TCS];
2004 };
2005 
2006 /**************************************/
2007 /* Init Tool HSI constants and macros */
2008 /**************************************/
2009 
2010 /* Width of GRC address in bits (addresses are specified in dwords) */
2011 #define GRC_ADDR_BITS	23
2012 #define MAX_GRC_ADDR	(BIT(GRC_ADDR_BITS) - 1)
2013 
2014 /* indicates an init that should be applied to any phase ID */
2015 #define ANY_PHASE_ID	0xffff
2016 
2017 /* Max size in dwords of a zipped array */
2018 #define MAX_ZIPPED_SIZE	8192
2019 enum chip_ids {
2020 	CHIP_BB,
2021 	CHIP_K2,
2022 	MAX_CHIP_IDS
2023 };
2024 
2025 struct fw_asserts_ram_section {
2026 	__le16 section_ram_line_offset;
2027 	__le16 section_ram_line_size;
2028 	u8 list_dword_offset;
2029 	u8 list_element_dword_size;
2030 	u8 list_num_elements;
2031 	u8 list_next_index_dword_offset;
2032 };
2033 
2034 struct fw_ver_num {
2035 	u8 major;
2036 	u8 minor;
2037 	u8 rev;
2038 	u8 eng;
2039 };
2040 
2041 struct fw_ver_info {
2042 	__le16 tools_ver;
2043 	u8 image_id;
2044 	u8 reserved1;
2045 	struct fw_ver_num num;
2046 	__le32 timestamp;
2047 	__le32 reserved2;
2048 };
2049 
2050 struct fw_info {
2051 	struct fw_ver_info ver;
2052 	struct fw_asserts_ram_section fw_asserts_section;
2053 };
2054 
2055 struct fw_info_location {
2056 	__le32 grc_addr;
2057 	__le32 size;
2058 };
2059 
2060 enum init_modes {
2061 	MODE_BB_A0_DEPRECATED,
2062 	MODE_BB,
2063 	MODE_K2,
2064 	MODE_ASIC,
2065 	MODE_EMUL_REDUCED,
2066 	MODE_EMUL_FULL,
2067 	MODE_FPGA,
2068 	MODE_CHIPSIM,
2069 	MODE_SF,
2070 	MODE_MF_SD,
2071 	MODE_MF_SI,
2072 	MODE_PORTS_PER_ENG_1,
2073 	MODE_PORTS_PER_ENG_2,
2074 	MODE_PORTS_PER_ENG_4,
2075 	MODE_100G,
2076 	MODE_SKIP_PRAM_INIT,
2077 	MODE_EMUL_MAC,
2078 	MAX_INIT_MODES
2079 };
2080 
2081 enum init_phases {
2082 	PHASE_ENGINE,
2083 	PHASE_PORT,
2084 	PHASE_PF,
2085 	PHASE_VF,
2086 	PHASE_QM_PF,
2087 	MAX_INIT_PHASES
2088 };
2089 
2090 enum init_split_types {
2091 	SPLIT_TYPE_NONE,
2092 	SPLIT_TYPE_PORT,
2093 	SPLIT_TYPE_PF,
2094 	SPLIT_TYPE_PORT_PF,
2095 	SPLIT_TYPE_VF,
2096 	MAX_INIT_SPLIT_TYPES
2097 };
2098 
2099 /* Binary buffer header */
2100 struct bin_buffer_hdr {
2101 	u32 offset;
2102 	u32 length;
2103 };
2104 
2105 /* Binary init buffer types */
2106 enum bin_init_buffer_type {
2107 	BIN_BUF_INIT_FW_VER_INFO,
2108 	BIN_BUF_INIT_CMD,
2109 	BIN_BUF_INIT_VAL,
2110 	BIN_BUF_INIT_MODE_TREE,
2111 	BIN_BUF_INIT_IRO,
2112 	BIN_BUF_INIT_OVERLAYS,
2113 	MAX_BIN_INIT_BUFFER_TYPE
2114 };
2115 
2116 /* FW overlay buffer header */
2117 struct fw_overlay_buf_hdr {
2118 	u32 data;
2119 #define FW_OVERLAY_BUF_HDR_STORM_ID_MASK  0xFF
2120 #define FW_OVERLAY_BUF_HDR_STORM_ID_SHIFT 0
2121 #define FW_OVERLAY_BUF_HDR_BUF_SIZE_MASK  0xFFFFFF
2122 #define FW_OVERLAY_BUF_HDR_BUF_SIZE_SHIFT 8
2123 };
2124 
2125 /* init array header: raw */
2126 struct init_array_raw_hdr {
2127 	__le32						data;
2128 #define INIT_ARRAY_RAW_HDR_TYPE_MASK			0xF
2129 #define INIT_ARRAY_RAW_HDR_TYPE_SHIFT			0
2130 #define INIT_ARRAY_RAW_HDR_PARAMS_MASK			0xFFFFFFF
2131 #define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT			4
2132 };
2133 
2134 /* init array header: standard */
2135 struct init_array_standard_hdr {
2136 	__le32						data;
2137 #define INIT_ARRAY_STANDARD_HDR_TYPE_MASK		0xF
2138 #define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT		0
2139 #define INIT_ARRAY_STANDARD_HDR_SIZE_MASK		0xFFFFFFF
2140 #define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT		4
2141 };
2142 
2143 /* init array header: zipped */
2144 struct init_array_zipped_hdr {
2145 	__le32						data;
2146 #define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK			0xF
2147 #define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT		0
2148 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK		0xFFFFFFF
2149 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT		4
2150 };
2151 
2152 /* init array header: pattern */
2153 struct init_array_pattern_hdr {
2154 	__le32						data;
2155 #define INIT_ARRAY_PATTERN_HDR_TYPE_MASK		0xF
2156 #define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT		0
2157 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK	0xF
2158 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT	4
2159 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK		0xFFFFFF
2160 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT	8
2161 };
2162 
2163 /* init array header union */
2164 union init_array_hdr {
2165 	struct init_array_raw_hdr			raw;
2166 	struct init_array_standard_hdr			standard;
2167 	struct init_array_zipped_hdr			zipped;
2168 	struct init_array_pattern_hdr			pattern;
2169 };
2170 
2171 /* init array types */
2172 enum init_array_types {
2173 	INIT_ARR_STANDARD,
2174 	INIT_ARR_ZIPPED,
2175 	INIT_ARR_PATTERN,
2176 	MAX_INIT_ARRAY_TYPES
2177 };
2178 
2179 /* init operation: callback */
2180 struct init_callback_op {
2181 	__le32						op_data;
2182 #define INIT_CALLBACK_OP_OP_MASK			0xF
2183 #define INIT_CALLBACK_OP_OP_SHIFT			0
2184 #define INIT_CALLBACK_OP_RESERVED_MASK			0xFFFFFFF
2185 #define INIT_CALLBACK_OP_RESERVED_SHIFT			4
2186 	__le16						callback_id;
2187 	__le16						block_id;
2188 };
2189 
2190 /* init operation: delay */
2191 struct init_delay_op {
2192 	__le32						op_data;
2193 #define INIT_DELAY_OP_OP_MASK				0xF
2194 #define INIT_DELAY_OP_OP_SHIFT				0
2195 #define INIT_DELAY_OP_RESERVED_MASK			0xFFFFFFF
2196 #define INIT_DELAY_OP_RESERVED_SHIFT			4
2197 	__le32						delay;
2198 };
2199 
2200 /* init operation: if_mode */
2201 struct init_if_mode_op {
2202 	__le32						op_data;
2203 #define INIT_IF_MODE_OP_OP_MASK				0xF
2204 #define INIT_IF_MODE_OP_OP_SHIFT			0
2205 #define INIT_IF_MODE_OP_RESERVED1_MASK			0xFFF
2206 #define INIT_IF_MODE_OP_RESERVED1_SHIFT			4
2207 #define INIT_IF_MODE_OP_CMD_OFFSET_MASK			0xFFFF
2208 #define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT		16
2209 	__le16						reserved2;
2210 	__le16						modes_buf_offset;
2211 };
2212 
2213 /* init operation: if_phase */
2214 struct init_if_phase_op {
2215 	__le32						op_data;
2216 #define INIT_IF_PHASE_OP_OP_MASK			0xF
2217 #define INIT_IF_PHASE_OP_OP_SHIFT			0
2218 #define INIT_IF_PHASE_OP_RESERVED1_MASK			0xFFF
2219 #define INIT_IF_PHASE_OP_RESERVED1_SHIFT		4
2220 #define INIT_IF_PHASE_OP_CMD_OFFSET_MASK		0xFFFF
2221 #define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT		16
2222 	__le32						phase_data;
2223 #define INIT_IF_PHASE_OP_PHASE_MASK			0xFF
2224 #define INIT_IF_PHASE_OP_PHASE_SHIFT			0
2225 #define INIT_IF_PHASE_OP_RESERVED2_MASK			0xFF
2226 #define INIT_IF_PHASE_OP_RESERVED2_SHIFT		8
2227 #define INIT_IF_PHASE_OP_PHASE_ID_MASK			0xFFFF
2228 #define INIT_IF_PHASE_OP_PHASE_ID_SHIFT			16
2229 };
2230 
2231 /* init mode operators */
2232 enum init_mode_ops {
2233 	INIT_MODE_OP_NOT,
2234 	INIT_MODE_OP_OR,
2235 	INIT_MODE_OP_AND,
2236 	MAX_INIT_MODE_OPS
2237 };
2238 
2239 /* init operation: raw */
2240 struct init_raw_op {
2241 	__le32						op_data;
2242 #define INIT_RAW_OP_OP_MASK				0xF
2243 #define INIT_RAW_OP_OP_SHIFT				0
2244 #define INIT_RAW_OP_PARAM1_MASK				0xFFFFFFF
2245 #define INIT_RAW_OP_PARAM1_SHIFT			4
2246 	__le32						param2;
2247 };
2248 
2249 /* init array params */
2250 struct init_op_array_params {
2251 	__le16						size;
2252 	__le16						offset;
2253 };
2254 
2255 /* Write init operation arguments */
2256 union init_write_args {
2257 	__le32						inline_val;
2258 	__le32						zeros_count;
2259 	__le32						array_offset;
2260 	struct init_op_array_params			runtime;
2261 };
2262 
2263 /* init operation: write */
2264 struct init_write_op {
2265 	__le32						data;
2266 #define INIT_WRITE_OP_OP_MASK				0xF
2267 #define INIT_WRITE_OP_OP_SHIFT				0
2268 #define INIT_WRITE_OP_SOURCE_MASK			0x7
2269 #define INIT_WRITE_OP_SOURCE_SHIFT			4
2270 #define INIT_WRITE_OP_RESERVED_MASK			0x1
2271 #define INIT_WRITE_OP_RESERVED_SHIFT			7
2272 #define INIT_WRITE_OP_WIDE_BUS_MASK			0x1
2273 #define INIT_WRITE_OP_WIDE_BUS_SHIFT			8
2274 #define INIT_WRITE_OP_ADDRESS_MASK			0x7FFFFF
2275 #define INIT_WRITE_OP_ADDRESS_SHIFT			9
2276 	union init_write_args				args;
2277 };
2278 
2279 /* init operation: read */
2280 struct init_read_op {
2281 	__le32						op_data;
2282 #define INIT_READ_OP_OP_MASK				0xF
2283 #define INIT_READ_OP_OP_SHIFT				0
2284 #define INIT_READ_OP_POLL_TYPE_MASK			0xF
2285 #define INIT_READ_OP_POLL_TYPE_SHIFT			4
2286 #define INIT_READ_OP_RESERVED_MASK			0x1
2287 #define INIT_READ_OP_RESERVED_SHIFT			8
2288 #define INIT_READ_OP_ADDRESS_MASK			0x7FFFFF
2289 #define INIT_READ_OP_ADDRESS_SHIFT			9
2290 	__le32						expected_val;
2291 };
2292 
2293 /* Init operations union */
2294 union init_op {
2295 	struct init_raw_op				raw;
2296 	struct init_write_op				write;
2297 	struct init_read_op				read;
2298 	struct init_if_mode_op				if_mode;
2299 	struct init_if_phase_op				if_phase;
2300 	struct init_callback_op				callback;
2301 	struct init_delay_op				delay;
2302 };
2303 
2304 /* Init command operation types */
2305 enum init_op_types {
2306 	INIT_OP_READ,
2307 	INIT_OP_WRITE,
2308 	INIT_OP_IF_MODE,
2309 	INIT_OP_IF_PHASE,
2310 	INIT_OP_DELAY,
2311 	INIT_OP_CALLBACK,
2312 	MAX_INIT_OP_TYPES
2313 };
2314 
2315 /* init polling types */
2316 enum init_poll_types {
2317 	INIT_POLL_NONE,
2318 	INIT_POLL_EQ,
2319 	INIT_POLL_OR,
2320 	INIT_POLL_AND,
2321 	MAX_INIT_POLL_TYPES
2322 };
2323 
2324 /* init source types */
2325 enum init_source_types {
2326 	INIT_SRC_INLINE,
2327 	INIT_SRC_ZEROS,
2328 	INIT_SRC_ARRAY,
2329 	INIT_SRC_RUNTIME,
2330 	MAX_INIT_SOURCE_TYPES
2331 };
2332 
2333 /* Internal RAM Offsets macro data */
2334 struct iro {
2335 	u32 base;
2336 	u16 m1;
2337 	u16 m2;
2338 	u16 m3;
2339 	u16 size;
2340 };
2341 
2342 /* Win 2 */
2343 #define GTT_BAR0_MAP_REG_IGU_CMD	0x00f000UL
2344 
2345 /* Win 3 */
2346 #define GTT_BAR0_MAP_REG_TSDM_RAM	0x010000UL
2347 
2348 /* Win 4 */
2349 #define GTT_BAR0_MAP_REG_MSDM_RAM	0x011000UL
2350 
2351 /* Win 5 */
2352 #define GTT_BAR0_MAP_REG_MSDM_RAM_1024	0x012000UL
2353 
2354 /* Win 6 */
2355 #define GTT_BAR0_MAP_REG_MSDM_RAM_2048	0x013000UL
2356 
2357 /* Win 7 */
2358 #define GTT_BAR0_MAP_REG_USDM_RAM	0x014000UL
2359 
2360 /* Win 8 */
2361 #define GTT_BAR0_MAP_REG_USDM_RAM_1024	0x015000UL
2362 
2363 /* Win 9 */
2364 #define GTT_BAR0_MAP_REG_USDM_RAM_2048	0x016000UL
2365 
2366 /* Win 10 */
2367 #define GTT_BAR0_MAP_REG_XSDM_RAM	0x017000UL
2368 
2369 /* Win 11 */
2370 #define GTT_BAR0_MAP_REG_XSDM_RAM_1024	0x018000UL
2371 
2372 /* Win 12 */
2373 #define GTT_BAR0_MAP_REG_YSDM_RAM	0x019000UL
2374 
2375 /* Win 13 */
2376 #define GTT_BAR0_MAP_REG_PSDM_RAM	0x01a000UL
2377 
2378 /* Returns the VOQ based on port and TC */
2379 #define VOQ(port, tc, max_phys_tcs_per_port)   ((tc) ==                       \
2380 						PURE_LB_TC ? NUM_OF_PHYS_TCS *\
2381 						MAX_NUM_PORTS_BB +            \
2382 						(port) : (port) *             \
2383 						(max_phys_tcs_per_port) + (tc))
2384 
2385 struct init_qm_pq_params;
2386 
2387 /**
2388  * qed_qm_pf_mem_size(): Prepare QM ILT sizes.
2389  *
2390  * @num_pf_cids: Number of connections used by this PF.
2391  * @num_vf_cids: Number of connections used by VFs of this PF.
2392  * @num_tids: Number of tasks used by this PF.
2393  * @num_pf_pqs: Number of PQs used by this PF.
2394  * @num_vf_pqs: Number of PQs used by VFs of this PF.
2395  *
2396  * Return: The required host memory size in 4KB units.
2397  *
2398  * Returns the required host memory size in 4KB units.
2399  * Must be called before all QM init HSI functions.
2400  */
2401 u32 qed_qm_pf_mem_size(u32 num_pf_cids,
2402 		       u32 num_vf_cids,
2403 		       u32 num_tids, u16 num_pf_pqs, u16 num_vf_pqs);
2404 
2405 struct qed_qm_common_rt_init_params {
2406 	u8 max_ports_per_engine;
2407 	u8 max_phys_tcs_per_port;
2408 	bool pf_rl_en;
2409 	bool pf_wfq_en;
2410 	bool global_rl_en;
2411 	bool vport_wfq_en;
2412 	struct init_qm_port_params *port_params;
2413 	struct init_qm_global_rl_params
2414 	global_rl_params[COMMON_MAX_QM_GLOBAL_RLS];
2415 };
2416 
2417 /**
2418  * qed_qm_common_rt_init(): Prepare QM runtime init values for the
2419  *                          engine phase.
2420  *
2421  * @p_hwfn: HW device data.
2422  * @p_params: Parameters.
2423  *
2424  * Return: 0 on success, -1 on error.
2425  */
2426 int qed_qm_common_rt_init(struct qed_hwfn *p_hwfn,
2427 			  struct qed_qm_common_rt_init_params *p_params);
2428 
2429 struct qed_qm_pf_rt_init_params {
2430 	u8 port_id;
2431 	u8 pf_id;
2432 	u8 max_phys_tcs_per_port;
2433 	bool is_pf_loading;
2434 	u32 num_pf_cids;
2435 	u32 num_vf_cids;
2436 	u32 num_tids;
2437 	u16 start_pq;
2438 	u16 num_pf_pqs;
2439 	u16 num_vf_pqs;
2440 	u16 start_vport;
2441 	u16 num_vports;
2442 	u16 start_rl;
2443 	u16 num_rls;
2444 	u16 pf_wfq;
2445 	u32 pf_rl;
2446 	u32 link_speed;
2447 	struct init_qm_pq_params *pq_params;
2448 	struct init_qm_vport_params *vport_params;
2449 	struct init_qm_rl_params *rl_params;
2450 };
2451 
2452 /**
2453  * qed_qm_pf_rt_init(): Prepare QM runtime init values for the PF phase.
2454  *
2455  * @p_hwfn:  HW device data.
2456  * @p_ptt: Ptt window used for writing the registers
2457  * @p_params: Parameters.
2458  *
2459  * Return: 0 on success, -1 on error.
2460  */
2461 int qed_qm_pf_rt_init(struct qed_hwfn *p_hwfn,
2462 		      struct qed_ptt *p_ptt,
2463 		      struct qed_qm_pf_rt_init_params *p_params);
2464 
2465 /**
2466  * qed_init_pf_wfq(): Initializes the WFQ weight of the specified PF.
2467  *
2468  * @p_hwfn: HW device data.
2469  * @p_ptt: Ptt window used for writing the registers
2470  * @pf_id: PF ID
2471  * @pf_wfq: WFQ weight. Must be non-zero.
2472  *
2473  * Return: 0 on success, -1 on error.
2474  */
2475 int qed_init_pf_wfq(struct qed_hwfn *p_hwfn,
2476 		    struct qed_ptt *p_ptt, u8 pf_id, u16 pf_wfq);
2477 
2478 /**
2479  * qed_init_pf_rl(): Initializes the rate limit of the specified PF
2480  *
2481  * @p_hwfn: HW device data.
2482  * @p_ptt: Ptt window used for writing the registers.
2483  * @pf_id: PF ID.
2484  * @pf_rl: rate limit in Mb/sec units
2485  *
2486  * Return: 0 on success, -1 on error.
2487  */
2488 int qed_init_pf_rl(struct qed_hwfn *p_hwfn,
2489 		   struct qed_ptt *p_ptt, u8 pf_id, u32 pf_rl);
2490 
2491 /**
2492  * qed_init_vport_wfq(): Initializes the WFQ weight of the specified VPORT
2493  *
2494  * @p_hwfn: HW device data.
2495  * @p_ptt: Ptt window used for writing the registers
2496  * @first_tx_pq_id: An array containing the first Tx PQ ID associated
2497  *                  with the VPORT for each TC. This array is filled by
2498  *                  qed_qm_pf_rt_init
2499  * @wfq: WFQ weight. Must be non-zero.
2500  *
2501  * Return: 0 on success, -1 on error.
2502  */
2503 int qed_init_vport_wfq(struct qed_hwfn *p_hwfn,
2504 		       struct qed_ptt *p_ptt,
2505 		       u16 first_tx_pq_id[NUM_OF_TCS], u16 wfq);
2506 
2507 /**
2508  * qed_init_vport_tc_wfq(): Initializes the WFQ weight of the specified
2509  *                          VPORT and TC.
2510  *
2511  * @p_hwfn: HW device data.
2512  * @p_ptt: Ptt window used for writing the registers.
2513  * @first_tx_pq_id: The first Tx PQ ID associated with the VPORT and TC.
2514  *                  (filled by qed_qm_pf_rt_init).
2515  * @weight: VPORT+TC WFQ weight.
2516  *
2517  * Return: 0 on success, -1 on error.
2518  */
2519 int qed_init_vport_tc_wfq(struct qed_hwfn *p_hwfn,
2520 			  struct qed_ptt *p_ptt,
2521 			  u16 first_tx_pq_id, u16 weight);
2522 
2523 /**
2524  * qed_init_global_rl():  Initializes the rate limit of the specified
2525  * rate limiter.
2526  *
2527  * @p_hwfn: HW device data.
2528  * @p_ptt: Ptt window used for writing the registers.
2529  * @rl_id: RL ID.
2530  * @rate_limit: Rate limit in Mb/sec units
2531  * @vport_rl_type: Vport RL type.
2532  *
2533  * Return: 0 on success, -1 on error.
2534  */
2535 int qed_init_global_rl(struct qed_hwfn *p_hwfn,
2536 		       struct qed_ptt *p_ptt,
2537 		       u16 rl_id, u32 rate_limit,
2538 		       enum init_qm_rl_type vport_rl_type);
2539 
2540 /**
2541  * qed_send_qm_stop_cmd(): Sends a stop command to the QM.
2542  *
2543  * @p_hwfn: HW device data.
2544  * @p_ptt: Ptt window used for writing the registers.
2545  * @is_release_cmd: true for release, false for stop.
2546  * @is_tx_pq: true for Tx PQs, false for Other PQs.
2547  * @start_pq: first PQ ID to stop
2548  * @num_pqs: Number of PQs to stop, starting from start_pq.
2549  *
2550  * Return: Bool, true if successful, false if timeout occurred while waiting
2551  *         for QM command done.
2552  */
2553 bool qed_send_qm_stop_cmd(struct qed_hwfn *p_hwfn,
2554 			  struct qed_ptt *p_ptt,
2555 			  bool is_release_cmd,
2556 			  bool is_tx_pq, u16 start_pq, u16 num_pqs);
2557 
2558 /**
2559  * qed_set_vxlan_dest_port(): Initializes vxlan tunnel destination udp port.
2560  *
2561  * @p_hwfn: HW device data.
2562  * @p_ptt: Ptt window used for writing the registers.
2563  * @dest_port: vxlan destination udp port.
2564  *
2565  * Return: Void.
2566  */
2567 void qed_set_vxlan_dest_port(struct qed_hwfn *p_hwfn,
2568 			     struct qed_ptt *p_ptt, u16 dest_port);
2569 
2570 /**
2571  * qed_set_vxlan_enable(): Enable or disable VXLAN tunnel in HW.
2572  *
2573  * @p_hwfn: HW device data.
2574  * @p_ptt: Ptt window used for writing the registers.
2575  * @vxlan_enable: vxlan enable flag.
2576  *
2577  * Return: Void.
2578  */
2579 void qed_set_vxlan_enable(struct qed_hwfn *p_hwfn,
2580 			  struct qed_ptt *p_ptt, bool vxlan_enable);
2581 
2582 /**
2583  * qed_set_gre_enable(): Enable or disable GRE tunnel in HW.
2584  *
2585  * @p_hwfn: HW device data.
2586  * @p_ptt: Ptt window used for writing the registers.
2587  * @eth_gre_enable: Eth GRE enable flag.
2588  * @ip_gre_enable: IP GRE enable flag.
2589  *
2590  * Return: Void.
2591  */
2592 void qed_set_gre_enable(struct qed_hwfn *p_hwfn,
2593 			struct qed_ptt *p_ptt,
2594 			bool eth_gre_enable, bool ip_gre_enable);
2595 
2596 /**
2597  * qed_set_geneve_dest_port(): Initializes geneve tunnel destination udp port
2598  *
2599  * @p_hwfn: HW device data.
2600  * @p_ptt: Ptt window used for writing the registers.
2601  * @dest_port: Geneve destination udp port.
2602  *
2603  * Retur: Void.
2604  */
2605 void qed_set_geneve_dest_port(struct qed_hwfn *p_hwfn,
2606 			      struct qed_ptt *p_ptt, u16 dest_port);
2607 
2608 /**
2609  * qed_set_geneve_enable(): Enable or disable GRE tunnel in HW.
2610  *
2611  * @p_hwfn: HW device data.
2612  * @p_ptt: Ptt window used for writing the registers.
2613  * @eth_geneve_enable: Eth GENEVE enable flag.
2614  * @ip_geneve_enable: IP GENEVE enable flag.
2615  *
2616  * Return: Void.
2617  */
2618 void qed_set_geneve_enable(struct qed_hwfn *p_hwfn,
2619 			   struct qed_ptt *p_ptt,
2620 			   bool eth_geneve_enable, bool ip_geneve_enable);
2621 
2622 void qed_set_vxlan_no_l2_enable(struct qed_hwfn *p_hwfn,
2623 				struct qed_ptt *p_ptt, bool enable);
2624 
2625 /**
2626  * qed_gft_disable(): Disable GFT.
2627  *
2628  * @p_hwfn: HW device data.
2629  * @p_ptt: Ptt window used for writing the registers.
2630  * @pf_id: PF on which to disable GFT.
2631  *
2632  * Return: Void.
2633  */
2634 void qed_gft_disable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u16 pf_id);
2635 
2636 /**
2637  * qed_gft_config(): Enable and configure HW for GFT.
2638  *
2639  * @p_hwfn: HW device data.
2640  * @p_ptt: Ptt window used for writing the registers.
2641  * @pf_id: PF on which to enable GFT.
2642  * @tcp: Set profile tcp packets.
2643  * @udp: Set profile udp  packet.
2644  * @ipv4: Set profile ipv4 packet.
2645  * @ipv6: Set profile ipv6 packet.
2646  * @profile_type: Define packet same fields. Use enum gft_profile_type.
2647  *
2648  * Return: Void.
2649  */
2650 void qed_gft_config(struct qed_hwfn *p_hwfn,
2651 		    struct qed_ptt *p_ptt,
2652 		    u16 pf_id,
2653 		    bool tcp,
2654 		    bool udp,
2655 		    bool ipv4, bool ipv6, enum gft_profile_type profile_type);
2656 
2657 /**
2658  * qed_enable_context_validation(): Enable and configure context
2659  *                                  validation.
2660  *
2661  * @p_hwfn: HW device data.
2662  * @p_ptt: Ptt window used for writing the registers.
2663  *
2664  * Return: Void.
2665  */
2666 void qed_enable_context_validation(struct qed_hwfn *p_hwfn,
2667 				   struct qed_ptt *p_ptt);
2668 
2669 /**
2670  * qed_calc_session_ctx_validation(): Calcualte validation byte for
2671  *                                    session context.
2672  *
2673  * @p_ctx_mem: Pointer to context memory.
2674  * @ctx_size: Context size.
2675  * @ctx_type: Context type.
2676  * @cid: Context cid.
2677  *
2678  * Return: Void.
2679  */
2680 void qed_calc_session_ctx_validation(void *p_ctx_mem,
2681 				     u16 ctx_size, u8 ctx_type, u32 cid);
2682 
2683 /**
2684  * qed_calc_task_ctx_validation(): Calcualte validation byte for task
2685  *                                 context.
2686  *
2687  * @p_ctx_mem: Pointer to context memory.
2688  * @ctx_size: Context size.
2689  * @ctx_type: Context type.
2690  * @tid: Context tid.
2691  *
2692  * Return: Void.
2693  */
2694 void qed_calc_task_ctx_validation(void *p_ctx_mem,
2695 				  u16 ctx_size, u8 ctx_type, u32 tid);
2696 
2697 /**
2698  * qed_memset_session_ctx(): Memset session context to 0 while
2699  *                            preserving validation bytes.
2700  *
2701  * @p_ctx_mem: Pointer to context memory.
2702  * @ctx_size: Size to initialzie.
2703  * @ctx_type: Context type.
2704  *
2705  * Return: Void.
2706  */
2707 void qed_memset_session_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type);
2708 
2709 /**
2710  * qed_memset_task_ctx(): Memset task context to 0 while preserving
2711  *                        validation bytes.
2712  *
2713  * @p_ctx_mem: Pointer to context memory.
2714  * @ctx_size: size to initialzie.
2715  * @ctx_type: context type.
2716  *
2717  * Return: Void.
2718  */
2719 void qed_memset_task_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type);
2720 
2721 #define NUM_STORMS 6
2722 
2723 /**
2724  * qed_get_protocol_type_str(): Get a string for Protocol type.
2725  *
2726  * @protocol_type: Protocol type (using enum protocol_type).
2727  *
2728  * Return: String.
2729  */
2730 const char *qed_get_protocol_type_str(u32 protocol_type);
2731 
2732 /**
2733  * qed_get_ramrod_cmd_id_str(): Get a string for Ramrod command ID.
2734  *
2735  * @protocol_type: Protocol type (using enum protocol_type).
2736  * @ramrod_cmd_id: Ramrod command ID (using per-protocol enum <protocol>_ramrod_cmd_id).
2737  *
2738  * Return: String.
2739  */
2740 const char *qed_get_ramrod_cmd_id_str(u32 protocol_type, u32 ramrod_cmd_id);
2741 
2742 /**
2743  * qed_set_rdma_error_level(): Sets the RDMA assert level.
2744  *                             If the severity of the error will be
2745  *                             above the level, the FW will assert.
2746  * @p_hwfn: HW device data.
2747  * @p_ptt: Ptt window used for writing the registers.
2748  * @assert_level: An array of assert levels for each storm.
2749  *
2750  * Return: Void.
2751  */
2752 void qed_set_rdma_error_level(struct qed_hwfn *p_hwfn,
2753 			      struct qed_ptt *p_ptt,
2754 			      u8 assert_level[NUM_STORMS]);
2755 /**
2756  * qed_fw_overlay_mem_alloc(): Allocates and fills the FW overlay memory.
2757  *
2758  * @p_hwfn: HW device data.
2759  * @fw_overlay_in_buf: The input FW overlay buffer.
2760  * @buf_size_in_bytes: The size of the input FW overlay buffer in bytes.
2761  *		        must be aligned to dwords.
2762  *
2763  * Return: A pointer to the allocated overlays memory,
2764  * or NULL in case of failures.
2765  */
2766 struct phys_mem_desc *
2767 qed_fw_overlay_mem_alloc(struct qed_hwfn *p_hwfn,
2768 			 const u32 *const fw_overlay_in_buf,
2769 			 u32 buf_size_in_bytes);
2770 
2771 /**
2772  * qed_fw_overlay_init_ram(): Initializes the FW overlay RAM.
2773  *
2774  * @p_hwfn: HW device data.
2775  * @p_ptt: Ptt window used for writing the registers.
2776  * @fw_overlay_mem: the allocated FW overlay memory.
2777  *
2778  * Return: Void.
2779  */
2780 void qed_fw_overlay_init_ram(struct qed_hwfn *p_hwfn,
2781 			     struct qed_ptt *p_ptt,
2782 			     struct phys_mem_desc *fw_overlay_mem);
2783 
2784 /**
2785  * qed_fw_overlay_mem_free(): Frees the FW overlay memory.
2786  *
2787  * @p_hwfn: HW device data.
2788  * @fw_overlay_mem: The allocated FW overlay memory to free.
2789  *
2790  * Return: Void.
2791  */
2792 void qed_fw_overlay_mem_free(struct qed_hwfn *p_hwfn,
2793 			     struct phys_mem_desc **fw_overlay_mem);
2794 
2795 #define PCICFG_OFFSET					0x2000
2796 #define GRC_CONFIG_REG_PF_INIT_VF			0x624
2797 
2798 /* First VF_NUM for PF is encoded in this register.
2799  * The number of VFs assigned to a PF is assumed to be a multiple of 8.
2800  * Software should program these bits based on Total Number of VFs programmed
2801  * for each PF.
2802  * Since registers from 0x000-0x7ff are spilt across functions, each PF will
2803  * have the same location for the same 4 bits
2804  */
2805 #define GRC_CR_PF_INIT_VF_PF_FIRST_VF_NUM_MASK		0xff
2806 
2807 /* Runtime array offsets */
2808 #define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET				0
2809 #define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET				1
2810 #define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET				2
2811 #define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET				3
2812 #define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET				4
2813 #define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET				5
2814 #define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET				6
2815 #define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET				7
2816 #define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET				8
2817 #define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET				9
2818 #define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET				10
2819 #define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET				11
2820 #define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET				12
2821 #define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET				13
2822 #define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET				14
2823 #define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET				15
2824 #define DORQ_REG_VF_ICID_BIT_SHIFT_NORM_RT_OFFSET			16
2825 #define DORQ_REG_PF_WAKE_ALL_RT_OFFSET					17
2826 #define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET				18
2827 #define IGU_REG_PF_CONFIGURATION_RT_OFFSET				19
2828 #define IGU_REG_VF_CONFIGURATION_RT_OFFSET				20
2829 #define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET				21
2830 #define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET				22
2831 #define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET				23
2832 #define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET				24
2833 #define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET				25
2834 #define CAU_REG_SB_VAR_MEMORY_RT_OFFSET					26
2835 #define CAU_REG_SB_VAR_MEMORY_RT_SIZE					736
2836 #define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET				762
2837 #define CAU_REG_SB_ADDR_MEMORY_RT_SIZE					736
2838 #define CAU_REG_PI_MEMORY_RT_OFFSET					1498
2839 #define CAU_REG_PI_MEMORY_RT_SIZE					4416
2840 #define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET			5914
2841 #define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET			5915
2842 #define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET			5916
2843 #define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET				5917
2844 #define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET				5918
2845 #define PRS_REG_SEARCH_TCP_RT_OFFSET					5919
2846 #define PRS_REG_SEARCH_FCOE_RT_OFFSET					5920
2847 #define PRS_REG_SEARCH_ROCE_RT_OFFSET					5921
2848 #define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET				5922
2849 #define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET				5923
2850 #define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET				5924
2851 #define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET			5925
2852 #define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET		5926
2853 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET			5927
2854 #define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET				5928
2855 #define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET				5929
2856 #define SRC_REG_FIRSTFREE_RT_OFFSET					5930
2857 #define SRC_REG_FIRSTFREE_RT_SIZE					2
2858 #define SRC_REG_LASTFREE_RT_OFFSET					5932
2859 #define SRC_REG_LASTFREE_RT_SIZE					2
2860 #define SRC_REG_COUNTFREE_RT_OFFSET					5934
2861 #define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET				5935
2862 #define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET				5936
2863 #define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET				5937
2864 #define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET					5938
2865 #define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET					5939
2866 #define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET					5940
2867 #define PSWRQ2_REG_TSDM_P_SIZE_RT_OFFSET				5941
2868 #define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET				5942
2869 #define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET				5943
2870 #define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET				5944
2871 #define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET				5945
2872 #define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET				5946
2873 #define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET				5947
2874 #define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET				5948
2875 #define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET				5949
2876 #define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET				5950
2877 #define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET				5951
2878 #define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET				5952
2879 #define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET				5953
2880 #define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET			5954
2881 #define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET			5955
2882 #define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET			5956
2883 #define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET				5957
2884 #define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET				5958
2885 #define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET				5959
2886 #define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET				5960
2887 #define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET				5961
2888 #define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET				5962
2889 #define PSWRQ2_REG_VF_BASE_RT_OFFSET					5963
2890 #define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET				5964
2891 #define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET				5965
2892 #define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET				5966
2893 #define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET					5967
2894 #define PSWRQ2_REG_ILT_MEMORY_RT_SIZE					22000
2895 #define PGLUE_REG_B_VF_BASE_RT_OFFSET					27967
2896 #define PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET			27968
2897 #define PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET				27969
2898 #define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET				27970
2899 #define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET				27971
2900 #define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET				27972
2901 #define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET				27973
2902 #define TM_REG_VF_ENABLE_CONN_RT_OFFSET					27974
2903 #define TM_REG_PF_ENABLE_CONN_RT_OFFSET					27975
2904 #define TM_REG_PF_ENABLE_TASK_RT_OFFSET					27976
2905 #define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET			27977
2906 #define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET			27978
2907 #define TM_REG_CONFIG_CONN_MEM_RT_OFFSET				27979
2908 #define TM_REG_CONFIG_CONN_MEM_RT_SIZE					416
2909 #define TM_REG_CONFIG_TASK_MEM_RT_OFFSET				28395
2910 #define TM_REG_CONFIG_TASK_MEM_RT_SIZE					512
2911 #define QM_REG_MAXPQSIZE_0_RT_OFFSET					28907
2912 #define QM_REG_MAXPQSIZE_1_RT_OFFSET					28908
2913 #define QM_REG_MAXPQSIZE_2_RT_OFFSET					28909
2914 #define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET				28910
2915 #define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET				28911
2916 #define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET				28912
2917 #define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET				28913
2918 #define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET				28914
2919 #define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET				28915
2920 #define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET				28916
2921 #define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET				28917
2922 #define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET				28918
2923 #define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET				28919
2924 #define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET				28920
2925 #define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET				28921
2926 #define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET				28922
2927 #define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET				28923
2928 #define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET				28924
2929 #define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET				28925
2930 #define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET				28926
2931 #define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET				28927
2932 #define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET				28928
2933 #define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET				28929
2934 #define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET				28930
2935 #define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET				28931
2936 #define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET				28932
2937 #define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET				28933
2938 #define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET				28934
2939 #define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET				28935
2940 #define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET				28936
2941 #define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET				28937
2942 #define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET				28938
2943 #define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET				28939
2944 #define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET				28940
2945 #define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET				28941
2946 #define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET				28942
2947 #define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET				28943
2948 #define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET				28944
2949 #define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET				28945
2950 #define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET				28946
2951 #define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET				28947
2952 #define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET				28948
2953 #define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET				28949
2954 #define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET				28950
2955 #define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET				28951
2956 #define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET				28952
2957 #define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET				28953
2958 #define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET				28954
2959 #define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET				28955
2960 #define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET				28956
2961 #define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET				28957
2962 #define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET				28958
2963 #define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET				28959
2964 #define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET				28960
2965 #define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET				28961
2966 #define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET				28962
2967 #define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET				28963
2968 #define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET				28964
2969 #define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET				28965
2970 #define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET				28966
2971 #define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET				28967
2972 #define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET				28968
2973 #define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET				28969
2974 #define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET				28970
2975 #define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET				28971
2976 #define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET				28972
2977 #define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET				28973
2978 #define QM_REG_BASEADDROTHERPQ_RT_OFFSET				28974
2979 #define QM_REG_BASEADDROTHERPQ_RT_SIZE					128
2980 #define QM_REG_PTRTBLOTHER_RT_OFFSET					29102
2981 #define QM_REG_PTRTBLOTHER_RT_SIZE					256
2982 #define QM_REG_VOQCRDLINE_RT_OFFSET					29358
2983 #define QM_REG_VOQCRDLINE_RT_SIZE					20
2984 #define QM_REG_VOQINITCRDLINE_RT_OFFSET					29378
2985 #define QM_REG_VOQINITCRDLINE_RT_SIZE					20
2986 #define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET				29398
2987 #define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET				29399
2988 #define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET				29400
2989 #define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET				29401
2990 #define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET				29402
2991 #define QM_REG_WRROTHERPQGRP_0_RT_OFFSET				29403
2992 #define QM_REG_WRROTHERPQGRP_1_RT_OFFSET				29404
2993 #define QM_REG_WRROTHERPQGRP_2_RT_OFFSET				29405
2994 #define QM_REG_WRROTHERPQGRP_3_RT_OFFSET				29406
2995 #define QM_REG_WRROTHERPQGRP_4_RT_OFFSET				29407
2996 #define QM_REG_WRROTHERPQGRP_5_RT_OFFSET				29408
2997 #define QM_REG_WRROTHERPQGRP_6_RT_OFFSET				29409
2998 #define QM_REG_WRROTHERPQGRP_7_RT_OFFSET				29410
2999 #define QM_REG_WRROTHERPQGRP_8_RT_OFFSET				29411
3000 #define QM_REG_WRROTHERPQGRP_9_RT_OFFSET				29412
3001 #define QM_REG_WRROTHERPQGRP_10_RT_OFFSET				29413
3002 #define QM_REG_WRROTHERPQGRP_11_RT_OFFSET				29414
3003 #define QM_REG_WRROTHERPQGRP_12_RT_OFFSET				29415
3004 #define QM_REG_WRROTHERPQGRP_13_RT_OFFSET				29416
3005 #define QM_REG_WRROTHERPQGRP_14_RT_OFFSET				29417
3006 #define QM_REG_WRROTHERPQGRP_15_RT_OFFSET				29418
3007 #define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET				29419
3008 #define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET				29420
3009 #define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET				29421
3010 #define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET				29422
3011 #define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET				29423
3012 #define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET				29424
3013 #define QM_REG_PQTX2PF_0_RT_OFFSET					29425
3014 #define QM_REG_PQTX2PF_1_RT_OFFSET					29426
3015 #define QM_REG_PQTX2PF_2_RT_OFFSET					29427
3016 #define QM_REG_PQTX2PF_3_RT_OFFSET					29428
3017 #define QM_REG_PQTX2PF_4_RT_OFFSET					29429
3018 #define QM_REG_PQTX2PF_5_RT_OFFSET					29430
3019 #define QM_REG_PQTX2PF_6_RT_OFFSET					29431
3020 #define QM_REG_PQTX2PF_7_RT_OFFSET					29432
3021 #define QM_REG_PQTX2PF_8_RT_OFFSET					29433
3022 #define QM_REG_PQTX2PF_9_RT_OFFSET					29434
3023 #define QM_REG_PQTX2PF_10_RT_OFFSET					29435
3024 #define QM_REG_PQTX2PF_11_RT_OFFSET					29436
3025 #define QM_REG_PQTX2PF_12_RT_OFFSET					29437
3026 #define QM_REG_PQTX2PF_13_RT_OFFSET					29438
3027 #define QM_REG_PQTX2PF_14_RT_OFFSET					29439
3028 #define QM_REG_PQTX2PF_15_RT_OFFSET					29440
3029 #define QM_REG_PQTX2PF_16_RT_OFFSET					29441
3030 #define QM_REG_PQTX2PF_17_RT_OFFSET					29442
3031 #define QM_REG_PQTX2PF_18_RT_OFFSET					29443
3032 #define QM_REG_PQTX2PF_19_RT_OFFSET					29444
3033 #define QM_REG_PQTX2PF_20_RT_OFFSET					29445
3034 #define QM_REG_PQTX2PF_21_RT_OFFSET					29446
3035 #define QM_REG_PQTX2PF_22_RT_OFFSET					29447
3036 #define QM_REG_PQTX2PF_23_RT_OFFSET					29448
3037 #define QM_REG_PQTX2PF_24_RT_OFFSET					29449
3038 #define QM_REG_PQTX2PF_25_RT_OFFSET					29450
3039 #define QM_REG_PQTX2PF_26_RT_OFFSET					29451
3040 #define QM_REG_PQTX2PF_27_RT_OFFSET					29452
3041 #define QM_REG_PQTX2PF_28_RT_OFFSET					29453
3042 #define QM_REG_PQTX2PF_29_RT_OFFSET					29454
3043 #define QM_REG_PQTX2PF_30_RT_OFFSET					29455
3044 #define QM_REG_PQTX2PF_31_RT_OFFSET					29456
3045 #define QM_REG_PQTX2PF_32_RT_OFFSET					29457
3046 #define QM_REG_PQTX2PF_33_RT_OFFSET					29458
3047 #define QM_REG_PQTX2PF_34_RT_OFFSET					29459
3048 #define QM_REG_PQTX2PF_35_RT_OFFSET					29460
3049 #define QM_REG_PQTX2PF_36_RT_OFFSET					29461
3050 #define QM_REG_PQTX2PF_37_RT_OFFSET					29462
3051 #define QM_REG_PQTX2PF_38_RT_OFFSET					29463
3052 #define QM_REG_PQTX2PF_39_RT_OFFSET					29464
3053 #define QM_REG_PQTX2PF_40_RT_OFFSET					29465
3054 #define QM_REG_PQTX2PF_41_RT_OFFSET					29466
3055 #define QM_REG_PQTX2PF_42_RT_OFFSET					29467
3056 #define QM_REG_PQTX2PF_43_RT_OFFSET					29468
3057 #define QM_REG_PQTX2PF_44_RT_OFFSET					29469
3058 #define QM_REG_PQTX2PF_45_RT_OFFSET					29470
3059 #define QM_REG_PQTX2PF_46_RT_OFFSET					29471
3060 #define QM_REG_PQTX2PF_47_RT_OFFSET					29472
3061 #define QM_REG_PQTX2PF_48_RT_OFFSET					29473
3062 #define QM_REG_PQTX2PF_49_RT_OFFSET					29474
3063 #define QM_REG_PQTX2PF_50_RT_OFFSET					29475
3064 #define QM_REG_PQTX2PF_51_RT_OFFSET					29476
3065 #define QM_REG_PQTX2PF_52_RT_OFFSET					29477
3066 #define QM_REG_PQTX2PF_53_RT_OFFSET					29478
3067 #define QM_REG_PQTX2PF_54_RT_OFFSET					29479
3068 #define QM_REG_PQTX2PF_55_RT_OFFSET					29480
3069 #define QM_REG_PQTX2PF_56_RT_OFFSET					29481
3070 #define QM_REG_PQTX2PF_57_RT_OFFSET					29482
3071 #define QM_REG_PQTX2PF_58_RT_OFFSET					29483
3072 #define QM_REG_PQTX2PF_59_RT_OFFSET					29484
3073 #define QM_REG_PQTX2PF_60_RT_OFFSET					29485
3074 #define QM_REG_PQTX2PF_61_RT_OFFSET					29486
3075 #define QM_REG_PQTX2PF_62_RT_OFFSET					29487
3076 #define QM_REG_PQTX2PF_63_RT_OFFSET					29488
3077 #define QM_REG_PQOTHER2PF_0_RT_OFFSET					29489
3078 #define QM_REG_PQOTHER2PF_1_RT_OFFSET					29490
3079 #define QM_REG_PQOTHER2PF_2_RT_OFFSET					29491
3080 #define QM_REG_PQOTHER2PF_3_RT_OFFSET					29492
3081 #define QM_REG_PQOTHER2PF_4_RT_OFFSET					29493
3082 #define QM_REG_PQOTHER2PF_5_RT_OFFSET					29494
3083 #define QM_REG_PQOTHER2PF_6_RT_OFFSET					29495
3084 #define QM_REG_PQOTHER2PF_7_RT_OFFSET					29496
3085 #define QM_REG_PQOTHER2PF_8_RT_OFFSET					29497
3086 #define QM_REG_PQOTHER2PF_9_RT_OFFSET					29498
3087 #define QM_REG_PQOTHER2PF_10_RT_OFFSET					29499
3088 #define QM_REG_PQOTHER2PF_11_RT_OFFSET					29500
3089 #define QM_REG_PQOTHER2PF_12_RT_OFFSET					29501
3090 #define QM_REG_PQOTHER2PF_13_RT_OFFSET					29502
3091 #define QM_REG_PQOTHER2PF_14_RT_OFFSET					29503
3092 #define QM_REG_PQOTHER2PF_15_RT_OFFSET					29504
3093 #define QM_REG_RLGLBLPERIOD_0_RT_OFFSET					29505
3094 #define QM_REG_RLGLBLPERIOD_1_RT_OFFSET					29506
3095 #define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET				29507
3096 #define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET				29508
3097 #define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET				29509
3098 #define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET				29510
3099 #define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET				29511
3100 #define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET				29512
3101 #define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET				29513
3102 #define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET				29514
3103 #define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET				29515
3104 #define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET				29516
3105 #define QM_REG_RLGLBLINCVAL_RT_OFFSET					29517
3106 #define QM_REG_RLGLBLINCVAL_RT_SIZE					256
3107 #define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET				29773
3108 #define QM_REG_RLGLBLUPPERBOUND_RT_SIZE					256
3109 #define QM_REG_RLGLBLCRD_RT_OFFSET					30029
3110 #define QM_REG_RLGLBLCRD_RT_SIZE					256
3111 #define QM_REG_RLGLBLENABLE_RT_OFFSET					30285
3112 #define QM_REG_RLPFPERIOD_RT_OFFSET					30286
3113 #define QM_REG_RLPFPERIODTIMER_RT_OFFSET				30287
3114 #define QM_REG_RLPFINCVAL_RT_OFFSET					30288
3115 #define QM_REG_RLPFINCVAL_RT_SIZE					16
3116 #define QM_REG_RLPFUPPERBOUND_RT_OFFSET					30304
3117 #define QM_REG_RLPFUPPERBOUND_RT_SIZE					16
3118 #define QM_REG_RLPFCRD_RT_OFFSET					30320
3119 #define QM_REG_RLPFCRD_RT_SIZE						16
3120 #define QM_REG_RLPFENABLE_RT_OFFSET					30336
3121 #define QM_REG_RLPFVOQENABLE_RT_OFFSET					30337
3122 #define QM_REG_WFQPFWEIGHT_RT_OFFSET					30338
3123 #define QM_REG_WFQPFWEIGHT_RT_SIZE					16
3124 #define QM_REG_WFQPFUPPERBOUND_RT_OFFSET				30354
3125 #define QM_REG_WFQPFUPPERBOUND_RT_SIZE					16
3126 #define QM_REG_WFQPFCRD_RT_OFFSET					30370
3127 #define QM_REG_WFQPFCRD_RT_SIZE						160
3128 #define QM_REG_WFQPFENABLE_RT_OFFSET					30530
3129 #define QM_REG_WFQVPENABLE_RT_OFFSET					30531
3130 #define QM_REG_BASEADDRTXPQ_RT_OFFSET					30532
3131 #define QM_REG_BASEADDRTXPQ_RT_SIZE					512
3132 #define QM_REG_TXPQMAP_RT_OFFSET					31044
3133 #define QM_REG_TXPQMAP_RT_SIZE						512
3134 #define QM_REG_WFQVPWEIGHT_RT_OFFSET					31556
3135 #define QM_REG_WFQVPWEIGHT_RT_SIZE					512
3136 #define QM_REG_WFQVPUPPERBOUND_RT_OFFSET				32068
3137 #define QM_REG_WFQVPUPPERBOUND_RT_SIZE					512
3138 #define QM_REG_WFQVPCRD_RT_OFFSET					32580
3139 #define QM_REG_WFQVPCRD_RT_SIZE						512
3140 #define QM_REG_WFQVPMAP_RT_OFFSET					33092
3141 #define QM_REG_WFQVPMAP_RT_SIZE						512
3142 #define QM_REG_PTRTBLTX_RT_OFFSET					33604
3143 #define QM_REG_PTRTBLTX_RT_SIZE						1024
3144 #define QM_REG_WFQPFCRD_MSB_RT_OFFSET					34628
3145 #define QM_REG_WFQPFCRD_MSB_RT_SIZE					160
3146 #define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET				34788
3147 #define NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET				34789
3148 #define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET				34790
3149 #define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET				34791
3150 #define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET				34792
3151 #define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET				34793
3152 #define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET			34794
3153 #define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET				34795
3154 #define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE					4
3155 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET				34799
3156 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE				4
3157 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET				34803
3158 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE				32
3159 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET				34835
3160 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE				16
3161 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET				34851
3162 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE				16
3163 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET			34867
3164 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE			16
3165 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET			34883
3166 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE				16
3167 #define NIG_REG_TX_EDPM_CTRL_RT_OFFSET					34899
3168 #define NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET				34900
3169 #define NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE				8
3170 #define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET				34908
3171 #define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET				34909
3172 #define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET				34910
3173 #define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET				34911
3174 #define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET				34912
3175 #define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET				34913
3176 #define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET				34914
3177 #define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET			34915
3178 #define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET			34916
3179 #define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET			34917
3180 #define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET			34918
3181 #define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET				34919
3182 #define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET				34920
3183 #define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET				34921
3184 #define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET				34922
3185 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET			34923
3186 #define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET				34924
3187 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET			34925
3188 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET			34926
3189 #define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET				34927
3190 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET			34928
3191 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET			34929
3192 #define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET				34930
3193 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET			34931
3194 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET			34932
3195 #define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET				34933
3196 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET			34934
3197 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET			34935
3198 #define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET				34936
3199 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET			34937
3200 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET			34938
3201 #define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET				34939
3202 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET			34940
3203 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET			34941
3204 #define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET				34942
3205 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET			34943
3206 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET			34944
3207 #define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET				34945
3208 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET			34946
3209 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET			34947
3210 #define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET				34948
3211 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET			34949
3212 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET			34950
3213 #define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET				34951
3214 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET			34952
3215 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET			34953
3216 #define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET				34954
3217 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET			34955
3218 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET			34956
3219 #define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET				34957
3220 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET			34958
3221 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET			34959
3222 #define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET				34960
3223 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET			34961
3224 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET			34962
3225 #define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET				34963
3226 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET			34964
3227 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET			34965
3228 #define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET				34966
3229 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET			34967
3230 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET			34968
3231 #define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET				34969
3232 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET			34970
3233 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET			34971
3234 #define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET				34972
3235 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET			34973
3236 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET			34974
3237 #define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET				34975
3238 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET			34976
3239 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET			34977
3240 #define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET				34978
3241 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET			34979
3242 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET			34980
3243 #define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET				34981
3244 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET			34982
3245 #define XCM_REG_CON_PHY_Q3_RT_OFFSET					34983
3246 
3247 #define RUNTIME_ARRAY_SIZE						34984
3248 
3249 /* Init Callbacks */
3250 #define DMAE_READY_CB	0
3251 
3252 /* The eth storm context for the Tstorm */
3253 struct tstorm_eth_conn_st_ctx {
3254 	__le32 reserved[4];
3255 };
3256 
3257 /* The eth storm context for the Pstorm */
3258 struct pstorm_eth_conn_st_ctx {
3259 	__le32 reserved[8];
3260 };
3261 
3262 /* The eth storm context for the Xstorm */
3263 struct xstorm_eth_conn_st_ctx {
3264 	__le32 reserved[60];
3265 };
3266 
3267 struct xstorm_eth_conn_ag_ctx {
3268 	u8 reserved0;
3269 	u8 state;
3270 	u8 flags0;
3271 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
3272 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
3273 #define XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK	0x1
3274 #define XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT	1
3275 #define XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK	0x1
3276 #define XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT	2
3277 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK	0x1
3278 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT	3
3279 #define XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK	0x1
3280 #define XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT	4
3281 #define XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK	0x1
3282 #define XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT	5
3283 #define XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK	0x1
3284 #define XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT	6
3285 #define XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK	0x1
3286 #define XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT	7
3287 		u8 flags1;
3288 #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK	0x1
3289 #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT	0
3290 #define XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK	0x1
3291 #define XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT	1
3292 #define XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK	0x1
3293 #define XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT	2
3294 #define XSTORM_ETH_CONN_AG_CTX_BIT11_MASK		0x1
3295 #define XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT		3
3296 #define XSTORM_ETH_CONN_AG_CTX_E5_RESERVED2_MASK	0x1
3297 #define XSTORM_ETH_CONN_AG_CTX_E5_RESERVED2_SHIFT	4
3298 #define XSTORM_ETH_CONN_AG_CTX_E5_RESERVED3_MASK	0x1
3299 #define XSTORM_ETH_CONN_AG_CTX_E5_RESERVED3_SHIFT	5
3300 #define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK	0x1
3301 #define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT	6
3302 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK	0x1
3303 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT	7
3304 	u8 flags2;
3305 #define XSTORM_ETH_CONN_AG_CTX_CF0_MASK	0x3
3306 #define XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT	0
3307 #define XSTORM_ETH_CONN_AG_CTX_CF1_MASK	0x3
3308 #define XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT	2
3309 #define XSTORM_ETH_CONN_AG_CTX_CF2_MASK	0x3
3310 #define XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT	4
3311 #define XSTORM_ETH_CONN_AG_CTX_CF3_MASK	0x3
3312 #define XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT	6
3313 	u8 flags3;
3314 #define XSTORM_ETH_CONN_AG_CTX_CF4_MASK	0x3
3315 #define XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT	0
3316 #define XSTORM_ETH_CONN_AG_CTX_CF5_MASK	0x3
3317 #define XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT	2
3318 #define XSTORM_ETH_CONN_AG_CTX_CF6_MASK	0x3
3319 #define XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT	4
3320 #define XSTORM_ETH_CONN_AG_CTX_CF7_MASK	0x3
3321 #define XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT	6
3322 		u8 flags4;
3323 #define XSTORM_ETH_CONN_AG_CTX_CF8_MASK	0x3
3324 #define XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT	0
3325 #define XSTORM_ETH_CONN_AG_CTX_CF9_MASK	0x3
3326 #define XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT	2
3327 #define XSTORM_ETH_CONN_AG_CTX_CF10_MASK	0x3
3328 #define XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT	4
3329 #define XSTORM_ETH_CONN_AG_CTX_CF11_MASK	0x3
3330 #define XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT	6
3331 	u8 flags5;
3332 #define XSTORM_ETH_CONN_AG_CTX_CF12_MASK	0x3
3333 #define XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT	0
3334 #define XSTORM_ETH_CONN_AG_CTX_CF13_MASK	0x3
3335 #define XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT	2
3336 #define XSTORM_ETH_CONN_AG_CTX_CF14_MASK	0x3
3337 #define XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT	4
3338 #define XSTORM_ETH_CONN_AG_CTX_CF15_MASK	0x3
3339 #define XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT	6
3340 	u8 flags6;
3341 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK		0x3
3342 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT	0
3343 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK		0x3
3344 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT	2
3345 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK			0x3
3346 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT			4
3347 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK		0x3
3348 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT		6
3349 	u8 flags7;
3350 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK		0x3
3351 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT	0
3352 #define XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK	0x3
3353 #define XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT	2
3354 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK	0x3
3355 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT	4
3356 #define XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK		0x1
3357 #define XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT		6
3358 #define XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK		0x1
3359 #define XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT		7
3360 	u8 flags8;
3361 #define XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK	0x1
3362 #define XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT	0
3363 #define XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK	0x1
3364 #define XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT	1
3365 #define XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK	0x1
3366 #define XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT	2
3367 #define XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK	0x1
3368 #define XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT	3
3369 #define XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK	0x1
3370 #define XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT	4
3371 #define XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK	0x1
3372 #define XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT	5
3373 #define XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK	0x1
3374 #define XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT	6
3375 #define XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK	0x1
3376 #define XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT	7
3377 	u8 flags9;
3378 #define XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK			0x1
3379 #define XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT			0
3380 #define XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK			0x1
3381 #define XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT			1
3382 #define XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK			0x1
3383 #define XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT			2
3384 #define XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK			0x1
3385 #define XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT			3
3386 #define XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK			0x1
3387 #define XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT			4
3388 #define XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK			0x1
3389 #define XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT			5
3390 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK	0x1
3391 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT	6
3392 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK	0x1
3393 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT	7
3394 	u8 flags10;
3395 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK			0x1
3396 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT		0
3397 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK		0x1
3398 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT		1
3399 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK		0x1
3400 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT		2
3401 #define XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK		0x1
3402 #define XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT		3
3403 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK		0x1
3404 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT		4
3405 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK	0x1
3406 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT	5
3407 #define XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK		0x1
3408 #define XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT		6
3409 #define XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK		0x1
3410 #define XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT		7
3411 	u8 flags11;
3412 #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK	0x1
3413 #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT	0
3414 #define XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK	0x1
3415 #define XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT	1
3416 #define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK	0x1
3417 #define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT	2
3418 #define XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK		0x1
3419 #define XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT		3
3420 #define XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK		0x1
3421 #define XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT		4
3422 #define XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK		0x1
3423 #define XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT		5
3424 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK	0x1
3425 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT	6
3426 #define XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK		0x1
3427 #define XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT		7
3428 	u8 flags12;
3429 #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK		0x1
3430 #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT	0
3431 #define XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK		0x1
3432 #define XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT	1
3433 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK	0x1
3434 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT	2
3435 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK	0x1
3436 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT	3
3437 #define XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK		0x1
3438 #define XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT	4
3439 #define XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK		0x1
3440 #define XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT	5
3441 #define XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK		0x1
3442 #define XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT	6
3443 #define XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK		0x1
3444 #define XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT	7
3445 	u8 flags13;
3446 #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK		0x1
3447 #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT	0
3448 #define XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK		0x1
3449 #define XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT	1
3450 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK	0x1
3451 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT	2
3452 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK	0x1
3453 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT	3
3454 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK	0x1
3455 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT	4
3456 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK	0x1
3457 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT	5
3458 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK	0x1
3459 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT	6
3460 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK	0x1
3461 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT	7
3462 	u8 flags14;
3463 #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK		0x1
3464 #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT	0
3465 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK	0x1
3466 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT	1
3467 #define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK	0x1
3468 #define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT	2
3469 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK	0x1
3470 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT	3
3471 #define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK		0x1
3472 #define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT		4
3473 #define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK		0x1
3474 #define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT	5
3475 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK		0x3
3476 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT		6
3477 	u8 edpm_event_id;
3478 	__le16 physical_q0;
3479 	__le16 e5_reserved1;
3480 	__le16 edpm_num_bds;
3481 	__le16 tx_bd_cons;
3482 	__le16 tx_bd_prod;
3483 	__le16 updated_qm_pq_id;
3484 	__le16 conn_dpi;
3485 	u8 byte3;
3486 	u8 byte4;
3487 	u8 byte5;
3488 	u8 byte6;
3489 	__le32 reg0;
3490 	__le32 reg1;
3491 	__le32 reg2;
3492 	__le32 reg3;
3493 	__le32 reg4;
3494 	__le32 reg5;
3495 	__le32 reg6;
3496 	__le16 word7;
3497 	__le16 word8;
3498 	__le16 word9;
3499 	__le16 word10;
3500 	__le32 reg7;
3501 	__le32 reg8;
3502 	__le32 reg9;
3503 	u8 byte7;
3504 	u8 byte8;
3505 	u8 byte9;
3506 	u8 byte10;
3507 	u8 byte11;
3508 	u8 byte12;
3509 	u8 byte13;
3510 	u8 byte14;
3511 	u8 byte15;
3512 	u8 e5_reserved;
3513 	__le16 word11;
3514 	__le32 reg10;
3515 	__le32 reg11;
3516 	__le32 reg12;
3517 	__le32 reg13;
3518 	__le32 reg14;
3519 	__le32 reg15;
3520 	__le32 reg16;
3521 	__le32 reg17;
3522 	__le32 reg18;
3523 	__le32 reg19;
3524 	__le16 word12;
3525 	__le16 word13;
3526 	__le16 word14;
3527 	__le16 word15;
3528 };
3529 
3530 /* The eth storm context for the Ystorm */
3531 struct ystorm_eth_conn_st_ctx {
3532 	__le32 reserved[8];
3533 };
3534 
3535 struct ystorm_eth_conn_ag_ctx {
3536 	u8 byte0;
3537 	u8 state;
3538 	u8 flags0;
3539 #define YSTORM_ETH_CONN_AG_CTX_BIT0_MASK			0x1
3540 #define YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT			0
3541 #define YSTORM_ETH_CONN_AG_CTX_BIT1_MASK			0x1
3542 #define YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT			1
3543 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK	0x3
3544 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT	2
3545 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK		0x3
3546 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT	4
3547 #define YSTORM_ETH_CONN_AG_CTX_CF2_MASK			0x3
3548 #define YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT			6
3549 	u8 flags1;
3550 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK	0x1
3551 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT	0
3552 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK	0x1
3553 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT	1
3554 #define YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK			0x1
3555 #define YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT			2
3556 #define YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK			0x1
3557 #define YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT			3
3558 #define YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK			0x1
3559 #define YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT			4
3560 #define YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK			0x1
3561 #define YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT			5
3562 #define YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK			0x1
3563 #define YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT			6
3564 #define YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK			0x1
3565 #define YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT			7
3566 	u8 tx_q0_int_coallecing_timeset;
3567 	u8 byte3;
3568 	__le16 word0;
3569 	__le32 terminate_spqe;
3570 	__le32 reg1;
3571 	__le16 tx_bd_cons_upd;
3572 	__le16 word2;
3573 	__le16 word3;
3574 	__le16 word4;
3575 	__le32 reg2;
3576 	__le32 reg3;
3577 };
3578 
3579 struct tstorm_eth_conn_ag_ctx {
3580 	u8 byte0;
3581 	u8 byte1;
3582 	u8 flags0;
3583 #define TSTORM_ETH_CONN_AG_CTX_BIT0_MASK	0x1
3584 #define TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT	0
3585 #define TSTORM_ETH_CONN_AG_CTX_BIT1_MASK	0x1
3586 #define TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT	1
3587 #define TSTORM_ETH_CONN_AG_CTX_BIT2_MASK	0x1
3588 #define TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT	2
3589 #define TSTORM_ETH_CONN_AG_CTX_BIT3_MASK	0x1
3590 #define TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT	3
3591 #define TSTORM_ETH_CONN_AG_CTX_BIT4_MASK	0x1
3592 #define TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT	4
3593 #define TSTORM_ETH_CONN_AG_CTX_BIT5_MASK	0x1
3594 #define TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT	5
3595 #define TSTORM_ETH_CONN_AG_CTX_CF0_MASK	0x3
3596 #define TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT	6
3597 	u8 flags1;
3598 #define TSTORM_ETH_CONN_AG_CTX_CF1_MASK	0x3
3599 #define TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT	0
3600 #define TSTORM_ETH_CONN_AG_CTX_CF2_MASK	0x3
3601 #define TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT	2
3602 #define TSTORM_ETH_CONN_AG_CTX_CF3_MASK	0x3
3603 #define TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT	4
3604 #define TSTORM_ETH_CONN_AG_CTX_CF4_MASK	0x3
3605 #define TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT	6
3606 	u8 flags2;
3607 #define TSTORM_ETH_CONN_AG_CTX_CF5_MASK	0x3
3608 #define TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT	0
3609 #define TSTORM_ETH_CONN_AG_CTX_CF6_MASK	0x3
3610 #define TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT	2
3611 #define TSTORM_ETH_CONN_AG_CTX_CF7_MASK	0x3
3612 #define TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT	4
3613 #define TSTORM_ETH_CONN_AG_CTX_CF8_MASK	0x3
3614 #define TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT	6
3615 	u8 flags3;
3616 #define TSTORM_ETH_CONN_AG_CTX_CF9_MASK	0x3
3617 #define TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT	0
3618 #define TSTORM_ETH_CONN_AG_CTX_CF10_MASK	0x3
3619 #define TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT	2
3620 #define TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK	0x1
3621 #define TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT	4
3622 #define TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK	0x1
3623 #define TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT	5
3624 #define TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK	0x1
3625 #define TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT	6
3626 #define TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK	0x1
3627 #define TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT	7
3628 	u8 flags4;
3629 #define TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK	0x1
3630 #define TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT	0
3631 #define TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK	0x1
3632 #define TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT	1
3633 #define TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK	0x1
3634 #define TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT	2
3635 #define TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK	0x1
3636 #define TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT	3
3637 #define TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK	0x1
3638 #define TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT	4
3639 #define TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK	0x1
3640 #define TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT	5
3641 #define TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK	0x1
3642 #define TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT	6
3643 #define TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK	0x1
3644 #define TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT	7
3645 	u8 flags5;
3646 #define TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK		0x1
3647 #define TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT		0
3648 #define TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK		0x1
3649 #define TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT		1
3650 #define TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK		0x1
3651 #define TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT		2
3652 #define TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK		0x1
3653 #define TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT		3
3654 #define TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK		0x1
3655 #define TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT		4
3656 #define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK		0x1
3657 #define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT	5
3658 #define TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK		0x1
3659 #define TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT		6
3660 #define TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK		0x1
3661 #define TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT		7
3662 	__le32 reg0;
3663 	__le32 reg1;
3664 	__le32 reg2;
3665 	__le32 reg3;
3666 	__le32 reg4;
3667 	__le32 reg5;
3668 	__le32 reg6;
3669 	__le32 reg7;
3670 	__le32 reg8;
3671 	u8 byte2;
3672 	u8 byte3;
3673 	__le16 rx_bd_cons;
3674 	u8 byte4;
3675 	u8 byte5;
3676 	__le16 rx_bd_prod;
3677 	__le16 word2;
3678 	__le16 word3;
3679 	__le32 reg9;
3680 	__le32 reg10;
3681 };
3682 
3683 struct ustorm_eth_conn_ag_ctx {
3684 	u8 byte0;
3685 	u8 byte1;
3686 	u8 flags0;
3687 #define USTORM_ETH_CONN_AG_CTX_BIT0_MASK			0x1
3688 #define USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT			0
3689 #define USTORM_ETH_CONN_AG_CTX_BIT1_MASK			0x1
3690 #define USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT			1
3691 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK	0x3
3692 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT	2
3693 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK	0x3
3694 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT	4
3695 #define USTORM_ETH_CONN_AG_CTX_CF2_MASK			0x3
3696 #define USTORM_ETH_CONN_AG_CTX_CF2_SHIFT			6
3697 	u8 flags1;
3698 #define USTORM_ETH_CONN_AG_CTX_CF3_MASK			0x3
3699 #define USTORM_ETH_CONN_AG_CTX_CF3_SHIFT			0
3700 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK		0x3
3701 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT		2
3702 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK		0x3
3703 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT		4
3704 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK	0x3
3705 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT	6
3706 	u8 flags2;
3707 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK	0x1
3708 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT	0
3709 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK	0x1
3710 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT	1
3711 #define USTORM_ETH_CONN_AG_CTX_CF2EN_MASK			0x1
3712 #define USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT			2
3713 #define USTORM_ETH_CONN_AG_CTX_CF3EN_MASK			0x1
3714 #define USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT			3
3715 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK		0x1
3716 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT		4
3717 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK		0x1
3718 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT		5
3719 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK	0x1
3720 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT	6
3721 #define USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK			0x1
3722 #define USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT			7
3723 	u8 flags3;
3724 #define USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK	0x1
3725 #define USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT	0
3726 #define USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK	0x1
3727 #define USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT	1
3728 #define USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK	0x1
3729 #define USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT	2
3730 #define USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK	0x1
3731 #define USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT	3
3732 #define USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK	0x1
3733 #define USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT	4
3734 #define USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK	0x1
3735 #define USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT	5
3736 #define USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK	0x1
3737 #define USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT	6
3738 #define USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK	0x1
3739 #define USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT	7
3740 	u8 byte2;
3741 	u8 byte3;
3742 	__le16 word0;
3743 	__le16 tx_bd_cons;
3744 	__le32 reg0;
3745 	__le32 reg1;
3746 	__le32 reg2;
3747 	__le32 tx_int_coallecing_timeset;
3748 	__le16 tx_drv_bd_cons;
3749 	__le16 rx_drv_cqe_cons;
3750 };
3751 
3752 /* The eth storm context for the Ustorm */
3753 struct ustorm_eth_conn_st_ctx {
3754 	__le32 reserved[40];
3755 };
3756 
3757 /* The eth storm context for the Mstorm */
3758 struct mstorm_eth_conn_st_ctx {
3759 	__le32 reserved[8];
3760 };
3761 
3762 /* eth connection context */
3763 struct eth_conn_context {
3764 	struct tstorm_eth_conn_st_ctx tstorm_st_context;
3765 	struct regpair tstorm_st_padding[2];
3766 	struct pstorm_eth_conn_st_ctx pstorm_st_context;
3767 	struct xstorm_eth_conn_st_ctx xstorm_st_context;
3768 	struct xstorm_eth_conn_ag_ctx xstorm_ag_context;
3769 	struct tstorm_eth_conn_ag_ctx tstorm_ag_context;
3770 	struct ystorm_eth_conn_st_ctx ystorm_st_context;
3771 	struct ystorm_eth_conn_ag_ctx ystorm_ag_context;
3772 	struct ustorm_eth_conn_ag_ctx ustorm_ag_context;
3773 	struct ustorm_eth_conn_st_ctx ustorm_st_context;
3774 	struct mstorm_eth_conn_st_ctx mstorm_st_context;
3775 };
3776 
3777 /* Ethernet filter types: mac/vlan/pair */
3778 enum eth_error_code {
3779 	ETH_OK = 0x00,
3780 	ETH_FILTERS_MAC_ADD_FAIL_FULL,
3781 	ETH_FILTERS_MAC_ADD_FAIL_FULL_MTT2,
3782 	ETH_FILTERS_MAC_ADD_FAIL_DUP_MTT2,
3783 	ETH_FILTERS_MAC_ADD_FAIL_DUP_STT2,
3784 	ETH_FILTERS_MAC_DEL_FAIL_NOF,
3785 	ETH_FILTERS_MAC_DEL_FAIL_NOF_MTT2,
3786 	ETH_FILTERS_MAC_DEL_FAIL_NOF_STT2,
3787 	ETH_FILTERS_MAC_ADD_FAIL_ZERO_MAC,
3788 	ETH_FILTERS_VLAN_ADD_FAIL_FULL,
3789 	ETH_FILTERS_VLAN_ADD_FAIL_DUP,
3790 	ETH_FILTERS_VLAN_DEL_FAIL_NOF,
3791 	ETH_FILTERS_VLAN_DEL_FAIL_NOF_TT1,
3792 	ETH_FILTERS_PAIR_ADD_FAIL_DUP,
3793 	ETH_FILTERS_PAIR_ADD_FAIL_FULL,
3794 	ETH_FILTERS_PAIR_ADD_FAIL_FULL_MAC,
3795 	ETH_FILTERS_PAIR_DEL_FAIL_NOF,
3796 	ETH_FILTERS_PAIR_DEL_FAIL_NOF_TT1,
3797 	ETH_FILTERS_PAIR_ADD_FAIL_ZERO_MAC,
3798 	ETH_FILTERS_VNI_ADD_FAIL_FULL,
3799 	ETH_FILTERS_VNI_ADD_FAIL_DUP,
3800 	ETH_FILTERS_GFT_UPDATE_FAIL,
3801 	ETH_RX_QUEUE_FAIL_LOAD_VF_DATA,
3802 	ETH_FILTERS_GFS_ADD_FILTER_FAIL_MAX_HOPS,
3803 	ETH_FILTERS_GFS_ADD_FILTER_FAIL_NO_FREE_ENRTY,
3804 	ETH_FILTERS_GFS_ADD_FILTER_FAIL_ALREADY_EXISTS,
3805 	ETH_FILTERS_GFS_ADD_FILTER_FAIL_PCI_ERROR,
3806 	ETH_FILTERS_GFS_ADD_FINLER_FAIL_MAGIC_NUM_ERROR,
3807 	ETH_FILTERS_GFS_DEL_FILTER_FAIL_MAX_HOPS,
3808 	ETH_FILTERS_GFS_DEL_FILTER_FAIL_NO_MATCH_ENRTY,
3809 	ETH_FILTERS_GFS_DEL_FILTER_FAIL_PCI_ERROR,
3810 	ETH_FILTERS_GFS_DEL_FILTER_FAIL_MAGIC_NUM_ERROR,
3811 	MAX_ETH_ERROR_CODE
3812 };
3813 
3814 /* Opcodes for the event ring */
3815 enum eth_event_opcode {
3816 	ETH_EVENT_UNUSED,
3817 	ETH_EVENT_VPORT_START,
3818 	ETH_EVENT_VPORT_UPDATE,
3819 	ETH_EVENT_VPORT_STOP,
3820 	ETH_EVENT_TX_QUEUE_START,
3821 	ETH_EVENT_TX_QUEUE_STOP,
3822 	ETH_EVENT_RX_QUEUE_START,
3823 	ETH_EVENT_RX_QUEUE_UPDATE,
3824 	ETH_EVENT_RX_QUEUE_STOP,
3825 	ETH_EVENT_FILTERS_UPDATE,
3826 	ETH_EVENT_RX_ADD_OPENFLOW_FILTER,
3827 	ETH_EVENT_RX_DELETE_OPENFLOW_FILTER,
3828 	ETH_EVENT_RX_CREATE_OPENFLOW_ACTION,
3829 	ETH_EVENT_RX_ADD_UDP_FILTER,
3830 	ETH_EVENT_RX_DELETE_UDP_FILTER,
3831 	ETH_EVENT_RX_CREATE_GFT_ACTION,
3832 	ETH_EVENT_RX_GFT_UPDATE_FILTER,
3833 	ETH_EVENT_TX_QUEUE_UPDATE,
3834 	ETH_EVENT_RGFS_ADD_FILTER,
3835 	ETH_EVENT_RGFS_DEL_FILTER,
3836 	ETH_EVENT_TGFS_ADD_FILTER,
3837 	ETH_EVENT_TGFS_DEL_FILTER,
3838 	ETH_EVENT_GFS_COUNTERS_REPORT_REQUEST,
3839 	MAX_ETH_EVENT_OPCODE
3840 };
3841 
3842 /* Classify rule types in E2/E3 */
3843 enum eth_filter_action {
3844 	ETH_FILTER_ACTION_UNUSED,
3845 	ETH_FILTER_ACTION_REMOVE,
3846 	ETH_FILTER_ACTION_ADD,
3847 	ETH_FILTER_ACTION_REMOVE_ALL,
3848 	MAX_ETH_FILTER_ACTION
3849 };
3850 
3851 /* Command for adding/removing a classification rule $$KEEP_ENDIANNESS$$ */
3852 struct eth_filter_cmd {
3853 	u8 type;
3854 	u8 vport_id;
3855 	u8 action;
3856 	u8 reserved0;
3857 	__le32 vni;
3858 	__le16 mac_lsb;
3859 	__le16 mac_mid;
3860 	__le16 mac_msb;
3861 	__le16 vlan_id;
3862 };
3863 
3864 /*	$$KEEP_ENDIANNESS$$ */
3865 struct eth_filter_cmd_header {
3866 	u8 rx;
3867 	u8 tx;
3868 	u8 cmd_cnt;
3869 	u8 assert_on_error;
3870 	u8 reserved1[4];
3871 };
3872 
3873 /* Ethernet filter types: mac/vlan/pair */
3874 enum eth_filter_type {
3875 	ETH_FILTER_TYPE_UNUSED,
3876 	ETH_FILTER_TYPE_MAC,
3877 	ETH_FILTER_TYPE_VLAN,
3878 	ETH_FILTER_TYPE_PAIR,
3879 	ETH_FILTER_TYPE_INNER_MAC,
3880 	ETH_FILTER_TYPE_INNER_VLAN,
3881 	ETH_FILTER_TYPE_INNER_PAIR,
3882 	ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR,
3883 	ETH_FILTER_TYPE_MAC_VNI_PAIR,
3884 	ETH_FILTER_TYPE_VNI,
3885 	MAX_ETH_FILTER_TYPE
3886 };
3887 
3888 /* inner to inner vlan priority translation configurations */
3889 struct eth_in_to_in_pri_map_cfg {
3890 	u8 inner_vlan_pri_remap_en;
3891 	u8 reserved[7];
3892 	u8 non_rdma_in_to_in_pri_map[8];
3893 	u8 rdma_in_to_in_pri_map[8];
3894 };
3895 
3896 /* Eth IPv4 Fragment Type */
3897 enum eth_ipv4_frag_type {
3898 	ETH_IPV4_NOT_FRAG,
3899 	ETH_IPV4_FIRST_FRAG,
3900 	ETH_IPV4_NON_FIRST_FRAG,
3901 	MAX_ETH_IPV4_FRAG_TYPE
3902 };
3903 
3904 /* eth IPv4 Fragment Type */
3905 enum eth_ip_type {
3906 	ETH_IPV4,
3907 	ETH_IPV6,
3908 	MAX_ETH_IP_TYPE
3909 };
3910 
3911 /* Ethernet Ramrod Command IDs */
3912 enum eth_ramrod_cmd_id {
3913 	ETH_RAMROD_UNUSED,
3914 	ETH_RAMROD_VPORT_START,
3915 	ETH_RAMROD_VPORT_UPDATE,
3916 	ETH_RAMROD_VPORT_STOP,
3917 	ETH_RAMROD_RX_QUEUE_START,
3918 	ETH_RAMROD_RX_QUEUE_STOP,
3919 	ETH_RAMROD_TX_QUEUE_START,
3920 	ETH_RAMROD_TX_QUEUE_STOP,
3921 	ETH_RAMROD_FILTERS_UPDATE,
3922 	ETH_RAMROD_RX_QUEUE_UPDATE,
3923 	ETH_RAMROD_RX_CREATE_OPENFLOW_ACTION,
3924 	ETH_RAMROD_RX_ADD_OPENFLOW_FILTER,
3925 	ETH_RAMROD_RX_DELETE_OPENFLOW_FILTER,
3926 	ETH_RAMROD_RX_ADD_UDP_FILTER,
3927 	ETH_RAMROD_RX_DELETE_UDP_FILTER,
3928 	ETH_RAMROD_RX_CREATE_GFT_ACTION,
3929 	ETH_RAMROD_RX_UPDATE_GFT_FILTER,
3930 	ETH_RAMROD_TX_QUEUE_UPDATE,
3931 	ETH_RAMROD_RGFS_FILTER_ADD,
3932 	ETH_RAMROD_RGFS_FILTER_DEL,
3933 	ETH_RAMROD_TGFS_FILTER_ADD,
3934 	ETH_RAMROD_TGFS_FILTER_DEL,
3935 	ETH_RAMROD_GFS_COUNTERS_REPORT_REQUEST,
3936 	MAX_ETH_RAMROD_CMD_ID
3937 };
3938 
3939 /* Return code from eth sp ramrods */
3940 struct eth_return_code {
3941 	u8 value;
3942 #define ETH_RETURN_CODE_ERR_CODE_MASK  0x3F
3943 #define ETH_RETURN_CODE_ERR_CODE_SHIFT 0
3944 #define ETH_RETURN_CODE_RESERVED_MASK  0x1
3945 #define ETH_RETURN_CODE_RESERVED_SHIFT 6
3946 #define ETH_RETURN_CODE_RX_TX_MASK     0x1
3947 #define ETH_RETURN_CODE_RX_TX_SHIFT    7
3948 };
3949 
3950 /* tx destination enum */
3951 enum eth_tx_dst_mode_config_enum {
3952 	ETH_TX_DST_MODE_CONFIG_DISABLE,
3953 	ETH_TX_DST_MODE_CONFIG_FORWARD_DATA_IN_BD,
3954 	ETH_TX_DST_MODE_CONFIG_FORWARD_DATA_IN_VPORT,
3955 	MAX_ETH_TX_DST_MODE_CONFIG_ENUM
3956 };
3957 
3958 /* What to do in case an error occurs */
3959 enum eth_tx_err {
3960 	ETH_TX_ERR_DROP,
3961 	ETH_TX_ERR_ASSERT_MALICIOUS,
3962 	MAX_ETH_TX_ERR
3963 };
3964 
3965 /* Array of the different error type behaviors */
3966 struct eth_tx_err_vals {
3967 	__le16 values;
3968 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_MASK			0x1
3969 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_SHIFT			0
3970 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_MASK			0x1
3971 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_SHIFT			1
3972 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_MASK			0x1
3973 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_SHIFT			2
3974 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_MASK		0x1
3975 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_SHIFT		3
3976 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_MASK	0x1
3977 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_SHIFT	4
3978 #define ETH_TX_ERR_VALS_MTU_VIOLATION_MASK			0x1
3979 #define ETH_TX_ERR_VALS_MTU_VIOLATION_SHIFT			5
3980 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK		0x1
3981 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_SHIFT		6
3982 #define ETH_TX_ERR_VALS_ILLEGAL_BD_FLAGS_MASK			0x1
3983 #define ETH_TX_ERR_VALS_ILLEGAL_BD_FLAGS_SHIFT			7
3984 #define ETH_TX_ERR_VALS_RESERVED_MASK				0xFF
3985 #define ETH_TX_ERR_VALS_RESERVED_SHIFT				8
3986 };
3987 
3988 /* vport rss configuration data */
3989 struct eth_vport_rss_config {
3990 	__le16 capabilities;
3991 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK		0x1
3992 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT		0
3993 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK		0x1
3994 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_SHIFT		1
3995 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK		0x1
3996 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_SHIFT		2
3997 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK		0x1
3998 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_SHIFT		3
3999 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK		0x1
4000 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_SHIFT		4
4001 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK		0x1
4002 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_SHIFT		5
4003 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK		0x1
4004 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_SHIFT	6
4005 #define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK			0x1FF
4006 #define ETH_VPORT_RSS_CONFIG_RESERVED0_SHIFT			7
4007 	u8 rss_id;
4008 	u8 rss_mode;
4009 	u8 update_rss_key;
4010 	u8 update_rss_ind_table;
4011 	u8 update_rss_capabilities;
4012 	u8 tbl_size;
4013 	u8 ind_table_mask_valid;
4014 	u8 reserved2[3];
4015 	__le16 indirection_table[ETH_RSS_IND_TABLE_ENTRIES_NUM];
4016 	__le32 ind_table_mask[ETH_RSS_IND_TABLE_MASK_SIZE_REGS];
4017 	__le32 rss_key[ETH_RSS_KEY_SIZE_REGS];
4018 	__le32 reserved3;
4019 };
4020 
4021 /* eth vport RSS mode */
4022 enum eth_vport_rss_mode {
4023 	ETH_VPORT_RSS_MODE_DISABLED,
4024 	ETH_VPORT_RSS_MODE_REGULAR,
4025 	MAX_ETH_VPORT_RSS_MODE
4026 };
4027 
4028 /* Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ */
4029 struct eth_vport_rx_mode {
4030 	__le16 state;
4031 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK		0x1
4032 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT		0
4033 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK		0x1
4034 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_SHIFT	1
4035 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK	0x1
4036 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_SHIFT	2
4037 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK		0x1
4038 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_SHIFT		3
4039 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK		0x1
4040 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_SHIFT	4
4041 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK		0x1
4042 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT	5
4043 #define ETH_VPORT_RX_MODE_ACCEPT_ANY_VNI_MASK		0x1
4044 #define ETH_VPORT_RX_MODE_ACCEPT_ANY_VNI_SHIFT		6
4045 #define ETH_VPORT_RX_MODE_RESERVED1_MASK		0x1FF
4046 #define ETH_VPORT_RX_MODE_RESERVED1_SHIFT		7
4047 };
4048 
4049 /* Command for setting tpa parameters */
4050 struct eth_vport_tpa_param {
4051 	u8 tpa_ipv4_en_flg;
4052 	u8 tpa_ipv6_en_flg;
4053 	u8 tpa_ipv4_tunn_en_flg;
4054 	u8 tpa_ipv6_tunn_en_flg;
4055 	u8 tpa_pkt_split_flg;
4056 	u8 tpa_hdr_data_split_flg;
4057 	u8 tpa_gro_consistent_flg;
4058 
4059 	u8 tpa_max_aggs_num;
4060 
4061 	__le16 tpa_max_size;
4062 	__le16 tpa_min_size_to_start;
4063 
4064 	__le16 tpa_min_size_to_cont;
4065 	u8 max_buff_num;
4066 	u8 reserved;
4067 };
4068 
4069 /* Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ */
4070 struct eth_vport_tx_mode {
4071 	__le16 state;
4072 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK		0x1
4073 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT		0
4074 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK		0x1
4075 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_SHIFT	1
4076 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK		0x1
4077 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_SHIFT		2
4078 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK		0x1
4079 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_SHIFT	3
4080 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK		0x1
4081 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_SHIFT	4
4082 #define ETH_VPORT_TX_MODE_RESERVED1_MASK		0x7FF
4083 #define ETH_VPORT_TX_MODE_RESERVED1_SHIFT		5
4084 };
4085 
4086 /* GFT filter update action type */
4087 enum gft_filter_update_action {
4088 	GFT_ADD_FILTER,
4089 	GFT_DELETE_FILTER,
4090 	MAX_GFT_FILTER_UPDATE_ACTION
4091 };
4092 
4093 /* Ramrod data for rx create gft action */
4094 struct rx_create_gft_action_ramrod_data {
4095 	u8 vport_id;
4096 	u8 reserved[7];
4097 };
4098 
4099 /* Ramrod data for rx create openflow action */
4100 struct rx_create_openflow_action_ramrod_data {
4101 	u8 vport_id;
4102 	u8 reserved[7];
4103 };
4104 
4105 /* Ramrod data for rx add openflow filter */
4106 struct rx_openflow_filter_ramrod_data {
4107 	__le16 action_icid;
4108 	u8 priority;
4109 	u8 reserved0;
4110 	__le32 tenant_id;
4111 	__le16 dst_mac_hi;
4112 	__le16 dst_mac_mid;
4113 	__le16 dst_mac_lo;
4114 	__le16 src_mac_hi;
4115 	__le16 src_mac_mid;
4116 	__le16 src_mac_lo;
4117 	__le16 vlan_id;
4118 	__le16 l2_eth_type;
4119 	u8 ipv4_dscp;
4120 	u8 ipv4_frag_type;
4121 	u8 ipv4_over_ip;
4122 	u8 tenant_id_exists;
4123 	__le32 ipv4_dst_addr;
4124 	__le32 ipv4_src_addr;
4125 	__le16 l4_dst_port;
4126 	__le16 l4_src_port;
4127 };
4128 
4129 /* Ramrod data for rx queue start ramrod */
4130 struct rx_queue_start_ramrod_data {
4131 	__le16 rx_queue_id;
4132 	__le16 num_of_pbl_pages;
4133 	__le16 bd_max_bytes;
4134 	__le16 sb_id;
4135 	u8 sb_index;
4136 	u8 vport_id;
4137 	u8 default_rss_queue_flg;
4138 	u8 complete_cqe_flg;
4139 	u8 complete_event_flg;
4140 	u8 stats_counter_id;
4141 	u8 pin_context;
4142 	u8 pxp_tph_valid_bd;
4143 	u8 pxp_tph_valid_pkt;
4144 	u8 pxp_st_hint;
4145 
4146 	__le16 pxp_st_index;
4147 	u8 pmd_mode;
4148 
4149 	u8 notify_en;
4150 	u8 toggle_val;
4151 
4152 	u8 vf_rx_prod_index;
4153 	u8 vf_rx_prod_use_zone_a;
4154 	u8 reserved[5];
4155 	__le16 reserved1;
4156 	struct regpair cqe_pbl_addr;
4157 	struct regpair bd_base;
4158 	struct regpair reserved2;
4159 };
4160 
4161 /* Ramrod data for rx queue stop ramrod */
4162 struct rx_queue_stop_ramrod_data {
4163 	__le16 rx_queue_id;
4164 	u8 complete_cqe_flg;
4165 	u8 complete_event_flg;
4166 	u8 vport_id;
4167 	u8 reserved[3];
4168 };
4169 
4170 /* Ramrod data for rx queue update ramrod */
4171 struct rx_queue_update_ramrod_data {
4172 	__le16 rx_queue_id;
4173 	u8 complete_cqe_flg;
4174 	u8 complete_event_flg;
4175 	u8 vport_id;
4176 	u8 set_default_rss_queue;
4177 	u8 reserved[3];
4178 	u8 reserved1;
4179 	u8 reserved2;
4180 	u8 reserved3;
4181 	__le16 reserved4;
4182 	__le16 reserved5;
4183 	struct regpair reserved6;
4184 };
4185 
4186 /* Ramrod data for rx Add UDP Filter */
4187 struct rx_udp_filter_ramrod_data {
4188 	__le16 action_icid;
4189 	__le16 vlan_id;
4190 	u8 ip_type;
4191 	u8 tenant_id_exists;
4192 	__le16 reserved1;
4193 	__le32 ip_dst_addr[4];
4194 	__le32 ip_src_addr[4];
4195 	__le16 udp_dst_port;
4196 	__le16 udp_src_port;
4197 	__le32 tenant_id;
4198 };
4199 
4200 /* Add or delete GFT filter - filter is packet header of type of packet wished
4201  * to pass certain FW flow.
4202  */
4203 struct rx_update_gft_filter_ramrod_data {
4204 	struct regpair pkt_hdr_addr;
4205 	__le16 pkt_hdr_length;
4206 	__le16 action_icid;
4207 	__le16 rx_qid;
4208 	__le16 flow_id;
4209 	__le16 vport_id;
4210 	u8 action_icid_valid;
4211 	u8 rx_qid_valid;
4212 	u8 flow_id_valid;
4213 	u8 filter_action;
4214 	u8 assert_on_error;
4215 	u8 inner_vlan_removal_en;
4216 };
4217 
4218 /* Ramrod data for tx queue start ramrod */
4219 struct tx_queue_start_ramrod_data {
4220 	__le16 sb_id;
4221 	u8 sb_index;
4222 	u8 vport_id;
4223 	u8 reserved0;
4224 	u8 stats_counter_id;
4225 	__le16 qm_pq_id;
4226 	u8 flags;
4227 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK	0x1
4228 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT	0
4229 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK	0x1
4230 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_SHIFT	1
4231 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK		0x1
4232 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_SHIFT		2
4233 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK		0x1
4234 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_SHIFT		3
4235 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK		0x1
4236 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_SHIFT		4
4237 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK		0x7
4238 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_SHIFT		5
4239 	u8 pxp_st_hint;
4240 	u8 pxp_tph_valid_bd;
4241 	u8 pxp_tph_valid_pkt;
4242 	__le16 pxp_st_index;
4243 	u8 comp_agg_size;
4244 	u8 reserved3;
4245 	__le16 queue_zone_id;
4246 	__le16 reserved2;
4247 	__le16 pbl_size;
4248 	__le16 tx_queue_id;
4249 	__le16 same_as_last_id;
4250 	__le16 reserved[3];
4251 	struct regpair pbl_base_addr;
4252 	struct regpair bd_cons_address;
4253 };
4254 
4255 /* Ramrod data for tx queue stop ramrod */
4256 struct tx_queue_stop_ramrod_data {
4257 	__le16 reserved[4];
4258 };
4259 
4260 /* Ramrod data for tx queue update ramrod */
4261 struct tx_queue_update_ramrod_data {
4262 	__le16 update_qm_pq_id_flg;
4263 	__le16 qm_pq_id;
4264 	__le32 reserved0;
4265 	struct regpair reserved1[5];
4266 };
4267 
4268 /* Inner to Inner VLAN priority map update mode */
4269 enum update_in_to_in_pri_map_mode_enum {
4270 	ETH_IN_TO_IN_PRI_MAP_UPDATE_DISABLED,
4271 	ETH_IN_TO_IN_PRI_MAP_UPDATE_NON_RDMA_TBL,
4272 	ETH_IN_TO_IN_PRI_MAP_UPDATE_RDMA_TBL,
4273 	MAX_UPDATE_IN_TO_IN_PRI_MAP_MODE_ENUM
4274 };
4275 
4276 /* Ramrod data for vport update ramrod */
4277 struct vport_filter_update_ramrod_data {
4278 	struct eth_filter_cmd_header filter_cmd_hdr;
4279 	struct eth_filter_cmd filter_cmds[ETH_FILTER_RULES_COUNT];
4280 };
4281 
4282 /* Ramrod data for vport start ramrod */
4283 struct vport_start_ramrod_data {
4284 	u8 vport_id;
4285 	u8 sw_fid;
4286 	__le16 mtu;
4287 	u8 drop_ttl0_en;
4288 	u8 inner_vlan_removal_en;
4289 	struct eth_vport_rx_mode rx_mode;
4290 	struct eth_vport_tx_mode tx_mode;
4291 	struct eth_vport_tpa_param tpa_param;
4292 	__le16 default_vlan;
4293 	u8 tx_switching_en;
4294 	u8 anti_spoofing_en;
4295 	u8 default_vlan_en;
4296 	u8 handle_ptp_pkts;
4297 	u8 silent_vlan_removal_en;
4298 	u8 untagged;
4299 	struct eth_tx_err_vals tx_err_behav;
4300 	u8 zero_placement_offset;
4301 	u8 ctl_frame_mac_check_en;
4302 	u8 ctl_frame_ethtype_check_en;
4303 	u8 reserved0;
4304 	u8 reserved1;
4305 	u8 tx_dst_port_mode_config;
4306 	u8 dst_vport_id;
4307 	u8 tx_dst_port_mode;
4308 	u8 dst_vport_id_valid;
4309 	u8 wipe_inner_vlan_pri_en;
4310 	u8 reserved2[2];
4311 	struct eth_in_to_in_pri_map_cfg in_to_in_vlan_pri_map_cfg;
4312 };
4313 
4314 /* Ramrod data for vport stop ramrod */
4315 struct vport_stop_ramrod_data {
4316 	u8 vport_id;
4317 	u8 reserved[7];
4318 };
4319 
4320 /* Ramrod data for vport update ramrod */
4321 struct vport_update_ramrod_data_cmn {
4322 	u8 vport_id;
4323 	u8 update_rx_active_flg;
4324 	u8 rx_active_flg;
4325 	u8 update_tx_active_flg;
4326 	u8 tx_active_flg;
4327 	u8 update_rx_mode_flg;
4328 	u8 update_tx_mode_flg;
4329 	u8 update_approx_mcast_flg;
4330 
4331 	u8 update_rss_flg;
4332 	u8 update_inner_vlan_removal_en_flg;
4333 
4334 	u8 inner_vlan_removal_en;
4335 	u8 update_tpa_param_flg;
4336 	u8 update_tpa_en_flg;
4337 	u8 update_tx_switching_en_flg;
4338 
4339 	u8 tx_switching_en;
4340 	u8 update_anti_spoofing_en_flg;
4341 
4342 	u8 anti_spoofing_en;
4343 	u8 update_handle_ptp_pkts;
4344 
4345 	u8 handle_ptp_pkts;
4346 	u8 update_default_vlan_en_flg;
4347 
4348 	u8 default_vlan_en;
4349 
4350 	u8 update_default_vlan_flg;
4351 
4352 	__le16 default_vlan;
4353 	u8 update_accept_any_vlan_flg;
4354 
4355 	u8 accept_any_vlan;
4356 	u8 silent_vlan_removal_en;
4357 	u8 update_mtu_flg;
4358 
4359 	__le16 mtu;
4360 	u8 update_ctl_frame_checks_en_flg;
4361 	u8 ctl_frame_mac_check_en;
4362 	u8 ctl_frame_ethtype_check_en;
4363 	u8 update_in_to_in_pri_map_mode;
4364 	u8 in_to_in_pri_map[8];
4365 	u8 update_tx_dst_port_mode_flg;
4366 	u8 tx_dst_port_mode_config;
4367 	u8 dst_vport_id;
4368 	u8 tx_dst_port_mode;
4369 	u8 dst_vport_id_valid;
4370 	u8 reserved[1];
4371 };
4372 
4373 struct vport_update_ramrod_mcast {
4374 	__le32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
4375 };
4376 
4377 /* Ramrod data for vport update ramrod */
4378 struct vport_update_ramrod_data {
4379 	struct vport_update_ramrod_data_cmn common;
4380 
4381 	struct eth_vport_rx_mode rx_mode;
4382 	struct eth_vport_tx_mode tx_mode;
4383 	__le32 reserved[3];
4384 	struct eth_vport_tpa_param tpa_param;
4385 	struct vport_update_ramrod_mcast approx_mcast;
4386 	struct eth_vport_rss_config rss_config;
4387 };
4388 
4389 struct xstorm_eth_conn_ag_ctx_dq_ext_ldpart {
4390 	u8 reserved0;
4391 	u8 state;
4392 	u8 flags0;
4393 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK	0x1
4394 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT	0
4395 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK		0x1
4396 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_SHIFT		1
4397 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK		0x1
4398 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_SHIFT		2
4399 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK	0x1
4400 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT	3
4401 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK		0x1
4402 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_SHIFT		4
4403 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK		0x1
4404 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_SHIFT		5
4405 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK		0x1
4406 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_SHIFT		6
4407 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK		0x1
4408 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_SHIFT		7
4409 	u8 flags1;
4410 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK		0x1
4411 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT		0
4412 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK		0x1
4413 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_SHIFT		1
4414 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK		0x1
4415 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_SHIFT		2
4416 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK		0x1
4417 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_SHIFT		3
4418 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED2_MASK	0x1
4419 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED2_SHIFT	4
4420 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED3_MASK	0x1
4421 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED3_SHIFT	5
4422 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK	0x1
4423 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_SHIFT	6
4424 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK	0x1
4425 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_SHIFT	7
4426 	u8 flags2;
4427 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK	0x3
4428 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT	0
4429 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK	0x3
4430 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_SHIFT	2
4431 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK	0x3
4432 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_SHIFT	4
4433 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK	0x3
4434 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_SHIFT	6
4435 	u8 flags3;
4436 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK	0x3
4437 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT	0
4438 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK	0x3
4439 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_SHIFT	2
4440 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK	0x3
4441 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_SHIFT	4
4442 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK	0x3
4443 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_SHIFT	6
4444 	u8 flags4;
4445 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK	0x3
4446 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT	0
4447 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK	0x3
4448 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_SHIFT	2
4449 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK	0x3
4450 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_SHIFT	4
4451 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK	0x3
4452 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_SHIFT	6
4453 	u8 flags5;
4454 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK	0x3
4455 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT	0
4456 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK	0x3
4457 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_SHIFT	2
4458 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK	0x3
4459 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_SHIFT	4
4460 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK	0x3
4461 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_SHIFT	6
4462 	u8 flags6;
4463 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK	0x3
4464 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT	0
4465 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK	0x3
4466 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_SHIFT	2
4467 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK		0x3
4468 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_SHIFT		4
4469 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK	0x3
4470 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_SHIFT	6
4471 	u8 flags7;
4472 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK		0x3
4473 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT		0
4474 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK		0x3
4475 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_SHIFT	2
4476 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK		0x3
4477 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT		4
4478 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK		0x1
4479 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_SHIFT		6
4480 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK		0x1
4481 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_SHIFT		7
4482 	u8 flags8;
4483 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK	0x1
4484 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT	0
4485 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK	0x1
4486 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_SHIFT	1
4487 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK	0x1
4488 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_SHIFT	2
4489 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK	0x1
4490 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_SHIFT	3
4491 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK	0x1
4492 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_SHIFT	4
4493 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK	0x1
4494 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_SHIFT	5
4495 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK	0x1
4496 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_SHIFT	6
4497 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK	0x1
4498 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_SHIFT	7
4499 	u8 flags9;
4500 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK			0x1
4501 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT			0
4502 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK			0x1
4503 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_SHIFT			1
4504 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK			0x1
4505 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_SHIFT			2
4506 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK			0x1
4507 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_SHIFT			3
4508 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK			0x1
4509 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_SHIFT			4
4510 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK			0x1
4511 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_SHIFT			5
4512 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK	0x1
4513 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_SHIFT	6
4514 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK	0x1
4515 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_SHIFT	7
4516 	u8 flags10;
4517 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK			0x1
4518 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT			0
4519 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK		0x1
4520 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_SHIFT		1
4521 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK		0x1
4522 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_SHIFT		2
4523 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK			0x1
4524 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_SHIFT		3
4525 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK		0x1
4526 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT		4
4527 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK	0x1
4528 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_SHIFT	5
4529 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK			0x1
4530 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_SHIFT		6
4531 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK			0x1
4532 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_SHIFT		7
4533 	u8 flags11;
4534 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK		0x1
4535 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT	0
4536 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK		0x1
4537 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_SHIFT	1
4538 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK	0x1
4539 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_SHIFT	2
4540 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK		0x1
4541 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_SHIFT		3
4542 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK		0x1
4543 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_SHIFT		4
4544 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK		0x1
4545 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_SHIFT		5
4546 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK	0x1
4547 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT	6
4548 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK		0x1
4549 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_SHIFT		7
4550 	u8 flags12;
4551 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK		0x1
4552 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT		0
4553 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK		0x1
4554 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_SHIFT		1
4555 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK	0x1
4556 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT	2
4557 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK	0x1
4558 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT	3
4559 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK		0x1
4560 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_SHIFT		4
4561 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK		0x1
4562 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_SHIFT		5
4563 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK		0x1
4564 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_SHIFT		6
4565 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK		0x1
4566 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_SHIFT		7
4567 	u8 flags13;
4568 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK		0x1
4569 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT		0
4570 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK		0x1
4571 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_SHIFT		1
4572 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK	0x1
4573 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT	2
4574 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK	0x1
4575 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT	3
4576 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK	0x1
4577 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT	4
4578 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK	0x1
4579 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT	5
4580 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK	0x1
4581 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT	6
4582 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK	0x1
4583 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT	7
4584 	u8 flags14;
4585 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK		0x1
4586 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT		0
4587 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK		0x1
4588 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_SHIFT	1
4589 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK	0x1
4590 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_SHIFT	2
4591 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK	0x1
4592 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_SHIFT	3
4593 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK		0x1
4594 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_SHIFT		4
4595 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK		0x1
4596 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT		5
4597 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK			0x3
4598 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_SHIFT		6
4599 	u8 edpm_event_id;
4600 	__le16 physical_q0;
4601 	__le16 e5_reserved1;
4602 	__le16 edpm_num_bds;
4603 	__le16 tx_bd_cons;
4604 	__le16 tx_bd_prod;
4605 	__le16 updated_qm_pq_id;
4606 	__le16 conn_dpi;
4607 	u8 byte3;
4608 	u8 byte4;
4609 	u8 byte5;
4610 	u8 byte6;
4611 	__le32 reg0;
4612 	__le32 reg1;
4613 	__le32 reg2;
4614 	__le32 reg3;
4615 	__le32 reg4;
4616 };
4617 
4618 struct mstorm_eth_conn_ag_ctx {
4619 	u8 byte0;
4620 	u8 byte1;
4621 	u8 flags0;
4622 #define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
4623 #define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	 0
4624 #define MSTORM_ETH_CONN_AG_CTX_BIT1_MASK		0x1
4625 #define MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT		1
4626 #define MSTORM_ETH_CONN_AG_CTX_CF0_MASK		0x3
4627 #define MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT		2
4628 #define MSTORM_ETH_CONN_AG_CTX_CF1_MASK		0x3
4629 #define MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT		4
4630 #define MSTORM_ETH_CONN_AG_CTX_CF2_MASK		0x3
4631 #define MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT		6
4632 	u8 flags1;
4633 #define MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK	0x1
4634 #define MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT	0
4635 #define MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK	0x1
4636 #define MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT	1
4637 #define MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK	0x1
4638 #define MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT	2
4639 #define MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK	0x1
4640 #define MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT	3
4641 #define MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK	0x1
4642 #define MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT	4
4643 #define MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK	0x1
4644 #define MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT	5
4645 #define MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK	0x1
4646 #define MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT	6
4647 #define MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK	0x1
4648 #define MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT	7
4649 	__le16 word0;
4650 	__le16 word1;
4651 	__le32 reg0;
4652 	__le32 reg1;
4653 };
4654 
4655 struct xstorm_eth_hw_conn_ag_ctx {
4656 	u8 reserved0;
4657 	u8 state;
4658 	u8 flags0;
4659 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
4660 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
4661 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK	0x1
4662 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT	1
4663 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK	0x1
4664 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT	2
4665 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK	0x1
4666 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT	3
4667 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK	0x1
4668 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT	4
4669 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK	0x1
4670 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT	5
4671 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK	0x1
4672 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT	6
4673 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK	0x1
4674 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT	7
4675 	u8 flags1;
4676 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK		0x1
4677 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT		0
4678 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK		0x1
4679 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT		1
4680 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK		0x1
4681 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT		2
4682 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK			0x1
4683 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT		3
4684 #define XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED2_MASK		0x1
4685 #define XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED2_SHIFT		4
4686 #define XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED3_MASK		0x1
4687 #define XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED3_SHIFT		5
4688 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK	0x1
4689 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT	6
4690 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK		0x1
4691 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT		7
4692 	u8 flags2;
4693 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK	0x3
4694 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT	0
4695 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK	0x3
4696 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT	2
4697 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK	0x3
4698 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT	4
4699 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK	0x3
4700 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT	6
4701 	u8 flags3;
4702 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK	0x3
4703 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT	0
4704 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK	0x3
4705 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT	2
4706 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK	0x3
4707 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT	4
4708 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK	0x3
4709 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT	6
4710 	u8 flags4;
4711 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK	0x3
4712 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT	0
4713 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK	0x3
4714 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT	2
4715 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK	0x3
4716 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT	4
4717 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK	0x3
4718 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT	6
4719 	u8 flags5;
4720 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK	0x3
4721 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT	0
4722 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK	0x3
4723 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT	2
4724 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK	0x3
4725 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT	4
4726 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK	0x3
4727 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT	6
4728 	u8 flags6;
4729 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK	0x3
4730 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT	0
4731 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK	0x3
4732 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT	2
4733 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK			0x3
4734 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT		4
4735 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK		0x3
4736 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT		6
4737 	u8 flags7;
4738 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK	0x3
4739 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT	0
4740 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK	0x3
4741 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT	2
4742 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK	0x3
4743 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT	4
4744 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK		0x1
4745 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT	6
4746 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK		0x1
4747 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT	7
4748 	u8 flags8;
4749 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK		0x1
4750 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT	0
4751 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK		0x1
4752 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT	1
4753 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK		0x1
4754 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT	2
4755 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK		0x1
4756 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT	3
4757 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK		0x1
4758 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT	4
4759 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK		0x1
4760 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT	5
4761 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK		0x1
4762 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT	6
4763 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK		0x1
4764 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT	7
4765 	u8 flags9;
4766 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK		0x1
4767 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT		0
4768 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK		0x1
4769 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT		1
4770 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK		0x1
4771 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT		2
4772 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK		0x1
4773 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT		3
4774 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK		0x1
4775 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT		4
4776 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK		0x1
4777 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT		5
4778 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK	0x1
4779 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT	6
4780 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK	0x1
4781 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT	7
4782 	u8 flags10;
4783 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK			0x1
4784 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT			0
4785 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK		0x1
4786 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT		1
4787 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK			0x1
4788 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT			2
4789 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK			0x1
4790 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT			3
4791 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK			0x1
4792 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT			4
4793 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK	0x1
4794 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT	5
4795 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK			0x1
4796 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT			6
4797 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK			0x1
4798 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT			7
4799 	u8 flags11;
4800 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK		0x1
4801 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT		0
4802 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK		0x1
4803 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT		1
4804 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK	0x1
4805 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT	2
4806 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK		0x1
4807 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT		3
4808 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK		0x1
4809 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT		4
4810 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK		0x1
4811 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT		5
4812 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK		0x1
4813 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT		6
4814 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK		0x1
4815 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT		7
4816 	u8 flags12;
4817 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK	0x1
4818 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT	0
4819 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK	0x1
4820 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT	1
4821 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK	0x1
4822 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT	2
4823 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK	0x1
4824 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT	3
4825 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK	0x1
4826 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT	4
4827 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK	0x1
4828 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT	5
4829 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK	0x1
4830 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT	6
4831 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK	0x1
4832 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT	7
4833 	u8 flags13;
4834 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK	0x1
4835 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT	0
4836 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK	0x1
4837 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT	1
4838 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK	0x1
4839 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT	2
4840 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK	0x1
4841 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT	3
4842 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK	0x1
4843 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT	4
4844 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK	0x1
4845 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT	5
4846 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK	0x1
4847 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT	6
4848 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK	0x1
4849 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT	7
4850 	u8 flags14;
4851 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK	0x1
4852 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT	0
4853 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK	0x1
4854 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT	1
4855 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK	0x1
4856 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT	2
4857 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK	0x1
4858 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT	3
4859 #define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK	0x1
4860 #define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT	4
4861 #define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK	0x1
4862 #define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT	5
4863 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK		0x3
4864 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT		6
4865 	u8 edpm_event_id;
4866 	__le16 physical_q0;
4867 	__le16 e5_reserved1;
4868 	__le16 edpm_num_bds;
4869 	__le16 tx_bd_cons;
4870 	__le16 tx_bd_prod;
4871 	__le16 updated_qm_pq_id;
4872 	__le16 conn_dpi;
4873 };
4874 
4875 /* GFT CAM line struct with fields breakout */
4876 struct gft_cam_line_mapped {
4877 	__le32 camline;
4878 #define GFT_CAM_LINE_MAPPED_VALID_MASK				0x1
4879 #define GFT_CAM_LINE_MAPPED_VALID_SHIFT				0
4880 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK			0x1
4881 #define GFT_CAM_LINE_MAPPED_IP_VERSION_SHIFT			1
4882 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK		0x1
4883 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_SHIFT		2
4884 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK		0xF
4885 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_SHIFT		3
4886 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK			0xF
4887 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_SHIFT			7
4888 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK				0xF
4889 #define GFT_CAM_LINE_MAPPED_PF_ID_SHIFT				11
4890 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_MASK		0x1
4891 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_SHIFT		15
4892 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_MASK		0x1
4893 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_SHIFT	16
4894 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK	0xF
4895 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_SHIFT	17
4896 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_MASK		0xF
4897 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_SHIFT		21
4898 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK			0xF
4899 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_SHIFT			25
4900 #define GFT_CAM_LINE_MAPPED_RESERVED1_MASK			0x7
4901 #define GFT_CAM_LINE_MAPPED_RESERVED1_SHIFT			29
4902 };
4903 
4904 /* Used in gft_profile_key: Indication for ip version */
4905 enum gft_profile_ip_version {
4906 	GFT_PROFILE_IPV4 = 0,
4907 	GFT_PROFILE_IPV6 = 1,
4908 	MAX_GFT_PROFILE_IP_VERSION
4909 };
4910 
4911 /* Profile key stucr fot GFT logic in Prs */
4912 struct gft_profile_key {
4913 	__le16 profile_key;
4914 #define GFT_PROFILE_KEY_IP_VERSION_MASK			0x1
4915 #define GFT_PROFILE_KEY_IP_VERSION_SHIFT		0
4916 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_MASK		0x1
4917 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_SHIFT		1
4918 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_MASK	0xF
4919 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_SHIFT	2
4920 #define GFT_PROFILE_KEY_TUNNEL_TYPE_MASK		0xF
4921 #define GFT_PROFILE_KEY_TUNNEL_TYPE_SHIFT		6
4922 #define GFT_PROFILE_KEY_PF_ID_MASK			0xF
4923 #define GFT_PROFILE_KEY_PF_ID_SHIFT			10
4924 #define GFT_PROFILE_KEY_RESERVED0_MASK			0x3
4925 #define GFT_PROFILE_KEY_RESERVED0_SHIFT			14
4926 };
4927 
4928 /* Used in gft_profile_key: Indication for tunnel type */
4929 enum gft_profile_tunnel_type {
4930 	GFT_PROFILE_NO_TUNNEL = 0,
4931 	GFT_PROFILE_VXLAN_TUNNEL = 1,
4932 	GFT_PROFILE_GRE_MAC_OR_NVGRE_TUNNEL = 2,
4933 	GFT_PROFILE_GRE_IP_TUNNEL = 3,
4934 	GFT_PROFILE_GENEVE_MAC_TUNNEL = 4,
4935 	GFT_PROFILE_GENEVE_IP_TUNNEL = 5,
4936 	MAX_GFT_PROFILE_TUNNEL_TYPE
4937 };
4938 
4939 /* Used in gft_profile_key: Indication for protocol type */
4940 enum gft_profile_upper_protocol_type {
4941 	GFT_PROFILE_ROCE_PROTOCOL = 0,
4942 	GFT_PROFILE_RROCE_PROTOCOL = 1,
4943 	GFT_PROFILE_FCOE_PROTOCOL = 2,
4944 	GFT_PROFILE_ICMP_PROTOCOL = 3,
4945 	GFT_PROFILE_ARP_PROTOCOL = 4,
4946 	GFT_PROFILE_USER_TCP_SRC_PORT_1_INNER = 5,
4947 	GFT_PROFILE_USER_TCP_DST_PORT_1_INNER = 6,
4948 	GFT_PROFILE_TCP_PROTOCOL = 7,
4949 	GFT_PROFILE_USER_UDP_DST_PORT_1_INNER = 8,
4950 	GFT_PROFILE_USER_UDP_DST_PORT_2_OUTER = 9,
4951 	GFT_PROFILE_UDP_PROTOCOL = 10,
4952 	GFT_PROFILE_USER_IP_1_INNER = 11,
4953 	GFT_PROFILE_USER_IP_2_OUTER = 12,
4954 	GFT_PROFILE_USER_ETH_1_INNER = 13,
4955 	GFT_PROFILE_USER_ETH_2_OUTER = 14,
4956 	GFT_PROFILE_RAW = 15,
4957 	MAX_GFT_PROFILE_UPPER_PROTOCOL_TYPE
4958 };
4959 
4960 /* GFT RAM line struct */
4961 struct gft_ram_line {
4962 	__le32 lo;
4963 #define GFT_RAM_LINE_VLAN_SELECT_MASK			0x3
4964 #define GFT_RAM_LINE_VLAN_SELECT_SHIFT			0
4965 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_MASK		0x1
4966 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_SHIFT		2
4967 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_MASK		0x1
4968 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_SHIFT		3
4969 #define GFT_RAM_LINE_TUNNEL_TTL_MASK			0x1
4970 #define GFT_RAM_LINE_TUNNEL_TTL_SHIFT			4
4971 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_MASK		0x1
4972 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_SHIFT		5
4973 #define GFT_RAM_LINE_TUNNEL_DST_PORT_MASK		0x1
4974 #define GFT_RAM_LINE_TUNNEL_DST_PORT_SHIFT		6
4975 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_MASK		0x1
4976 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_SHIFT		7
4977 #define GFT_RAM_LINE_TUNNEL_DSCP_MASK			0x1
4978 #define GFT_RAM_LINE_TUNNEL_DSCP_SHIFT			8
4979 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_MASK	0x1
4980 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_SHIFT	9
4981 #define GFT_RAM_LINE_TUNNEL_DST_IP_MASK			0x1
4982 #define GFT_RAM_LINE_TUNNEL_DST_IP_SHIFT		10
4983 #define GFT_RAM_LINE_TUNNEL_SRC_IP_MASK			0x1
4984 #define GFT_RAM_LINE_TUNNEL_SRC_IP_SHIFT		11
4985 #define GFT_RAM_LINE_TUNNEL_PRIORITY_MASK		0x1
4986 #define GFT_RAM_LINE_TUNNEL_PRIORITY_SHIFT		12
4987 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_MASK		0x1
4988 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_SHIFT		13
4989 #define GFT_RAM_LINE_TUNNEL_VLAN_MASK			0x1
4990 #define GFT_RAM_LINE_TUNNEL_VLAN_SHIFT			14
4991 #define GFT_RAM_LINE_TUNNEL_DST_MAC_MASK		0x1
4992 #define GFT_RAM_LINE_TUNNEL_DST_MAC_SHIFT		15
4993 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_MASK		0x1
4994 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_SHIFT		16
4995 #define GFT_RAM_LINE_TTL_EQUAL_ONE_MASK			0x1
4996 #define GFT_RAM_LINE_TTL_EQUAL_ONE_SHIFT		17
4997 #define GFT_RAM_LINE_TTL_MASK				0x1
4998 #define GFT_RAM_LINE_TTL_SHIFT				18
4999 #define GFT_RAM_LINE_ETHERTYPE_MASK			0x1
5000 #define GFT_RAM_LINE_ETHERTYPE_SHIFT			19
5001 #define GFT_RAM_LINE_RESERVED0_MASK			0x1
5002 #define GFT_RAM_LINE_RESERVED0_SHIFT			20
5003 #define GFT_RAM_LINE_TCP_FLAG_FIN_MASK			0x1
5004 #define GFT_RAM_LINE_TCP_FLAG_FIN_SHIFT			21
5005 #define GFT_RAM_LINE_TCP_FLAG_SYN_MASK			0x1
5006 #define GFT_RAM_LINE_TCP_FLAG_SYN_SHIFT			22
5007 #define GFT_RAM_LINE_TCP_FLAG_RST_MASK			0x1
5008 #define GFT_RAM_LINE_TCP_FLAG_RST_SHIFT			23
5009 #define GFT_RAM_LINE_TCP_FLAG_PSH_MASK			0x1
5010 #define GFT_RAM_LINE_TCP_FLAG_PSH_SHIFT			24
5011 #define GFT_RAM_LINE_TCP_FLAG_ACK_MASK			0x1
5012 #define GFT_RAM_LINE_TCP_FLAG_ACK_SHIFT			25
5013 #define GFT_RAM_LINE_TCP_FLAG_URG_MASK			0x1
5014 #define GFT_RAM_LINE_TCP_FLAG_URG_SHIFT			26
5015 #define GFT_RAM_LINE_TCP_FLAG_ECE_MASK			0x1
5016 #define GFT_RAM_LINE_TCP_FLAG_ECE_SHIFT			27
5017 #define GFT_RAM_LINE_TCP_FLAG_CWR_MASK			0x1
5018 #define GFT_RAM_LINE_TCP_FLAG_CWR_SHIFT			28
5019 #define GFT_RAM_LINE_TCP_FLAG_NS_MASK			0x1
5020 #define GFT_RAM_LINE_TCP_FLAG_NS_SHIFT			29
5021 #define GFT_RAM_LINE_DST_PORT_MASK			0x1
5022 #define GFT_RAM_LINE_DST_PORT_SHIFT			30
5023 #define GFT_RAM_LINE_SRC_PORT_MASK			0x1
5024 #define GFT_RAM_LINE_SRC_PORT_SHIFT			31
5025 	__le32 hi;
5026 #define GFT_RAM_LINE_DSCP_MASK				0x1
5027 #define GFT_RAM_LINE_DSCP_SHIFT				0
5028 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_MASK		0x1
5029 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_SHIFT		1
5030 #define GFT_RAM_LINE_DST_IP_MASK			0x1
5031 #define GFT_RAM_LINE_DST_IP_SHIFT			2
5032 #define GFT_RAM_LINE_SRC_IP_MASK			0x1
5033 #define GFT_RAM_LINE_SRC_IP_SHIFT			3
5034 #define GFT_RAM_LINE_PRIORITY_MASK			0x1
5035 #define GFT_RAM_LINE_PRIORITY_SHIFT			4
5036 #define GFT_RAM_LINE_PROVIDER_VLAN_MASK			0x1
5037 #define GFT_RAM_LINE_PROVIDER_VLAN_SHIFT		5
5038 #define GFT_RAM_LINE_VLAN_MASK				0x1
5039 #define GFT_RAM_LINE_VLAN_SHIFT				6
5040 #define GFT_RAM_LINE_DST_MAC_MASK			0x1
5041 #define GFT_RAM_LINE_DST_MAC_SHIFT			7
5042 #define GFT_RAM_LINE_SRC_MAC_MASK			0x1
5043 #define GFT_RAM_LINE_SRC_MAC_SHIFT			8
5044 #define GFT_RAM_LINE_TENANT_ID_MASK			0x1
5045 #define GFT_RAM_LINE_TENANT_ID_SHIFT			9
5046 #define GFT_RAM_LINE_RESERVED1_MASK			0x3FFFFF
5047 #define GFT_RAM_LINE_RESERVED1_SHIFT			10
5048 };
5049 
5050 /* Used in the first 2 bits for gft_ram_line: Indication for vlan mask */
5051 enum gft_vlan_select {
5052 	INNER_PROVIDER_VLAN = 0,
5053 	INNER_VLAN = 1,
5054 	OUTER_PROVIDER_VLAN = 2,
5055 	OUTER_VLAN = 3,
5056 	MAX_GFT_VLAN_SELECT
5057 };
5058 
5059 /* The rdma task context of Mstorm */
5060 struct ystorm_rdma_task_st_ctx {
5061 	struct regpair temp[4];
5062 };
5063 
5064 struct ystorm_rdma_task_ag_ctx {
5065 	u8 reserved;
5066 	u8 byte1;
5067 	__le16 msem_ctx_upd_seq;
5068 	u8 flags0;
5069 #define YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK		0xF
5070 #define YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT	0
5071 #define YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK		0x1
5072 #define YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT		4
5073 #define YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK			0x1
5074 #define YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT			5
5075 #define YSTORM_RDMA_TASK_AG_CTX_VALID_MASK			0x1
5076 #define YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT			6
5077 #define YSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_MASK		0x1
5078 #define YSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_SHIFT		7
5079 	u8 flags1;
5080 #define YSTORM_RDMA_TASK_AG_CTX_CF0_MASK		0x3
5081 #define YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT		0
5082 #define YSTORM_RDMA_TASK_AG_CTX_CF1_MASK		0x3
5083 #define YSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT		2
5084 #define YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK	0x3
5085 #define YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_SHIFT	4
5086 #define YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK		0x1
5087 #define YSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT		6
5088 #define YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK		0x1
5089 #define YSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT		7
5090 	u8 flags2;
5091 #define YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK		0x1
5092 #define YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT		0
5093 #define YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK		0x1
5094 #define YSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT	1
5095 #define YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK		0x1
5096 #define YSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT	2
5097 #define YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK		0x1
5098 #define YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT	3
5099 #define YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK		0x1
5100 #define YSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT	4
5101 #define YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK		0x1
5102 #define YSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT	5
5103 #define YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK		0x1
5104 #define YSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT	6
5105 #define YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK		0x1
5106 #define YSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT	7
5107 	u8 key;
5108 	__le32 mw_cnt_or_qp_id;
5109 	u8 ref_cnt_seq;
5110 	u8 ctx_upd_seq;
5111 	__le16 dif_flags;
5112 	__le16 tx_ref_count;
5113 	__le16 last_used_ltid;
5114 	__le16 parent_mr_lo;
5115 	__le16 parent_mr_hi;
5116 	__le32 fbo_lo;
5117 	__le32 fbo_hi;
5118 };
5119 
5120 struct mstorm_rdma_task_ag_ctx {
5121 	u8 reserved;
5122 	u8 byte1;
5123 	__le16 icid;
5124 	u8 flags0;
5125 #define MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK		0xF
5126 #define MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT	0
5127 #define MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK		0x1
5128 #define MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT		4
5129 #define MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK			0x1
5130 #define MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT			5
5131 #define MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK			0x1
5132 #define MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT			6
5133 #define MSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_MASK		0x1
5134 #define MSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_SHIFT		7
5135 	u8 flags1;
5136 #define MSTORM_RDMA_TASK_AG_CTX_CF0_MASK	0x3
5137 #define MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT	0
5138 #define MSTORM_RDMA_TASK_AG_CTX_CF1_MASK	0x3
5139 #define MSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT	2
5140 #define MSTORM_RDMA_TASK_AG_CTX_CF2_MASK	0x3
5141 #define MSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT	4
5142 #define MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK	0x1
5143 #define MSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT	6
5144 #define MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK	0x1
5145 #define MSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT	7
5146 	u8 flags2;
5147 #define MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK		0x1
5148 #define MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT		0
5149 #define MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK		0x1
5150 #define MSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT	1
5151 #define MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK		0x1
5152 #define MSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT	2
5153 #define MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK		0x1
5154 #define MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT	3
5155 #define MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK		0x1
5156 #define MSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT	4
5157 #define MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK		0x1
5158 #define MSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT	5
5159 #define MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK		0x1
5160 #define MSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT	6
5161 #define MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK		0x1
5162 #define MSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT	7
5163 	u8 key;
5164 	__le32 mw_cnt_or_qp_id;
5165 	u8 ref_cnt_seq;
5166 	u8 ctx_upd_seq;
5167 	__le16 dif_flags;
5168 	__le16 tx_ref_count;
5169 	__le16 last_used_ltid;
5170 	__le16 parent_mr_lo;
5171 	__le16 parent_mr_hi;
5172 	__le32 fbo_lo;
5173 	__le32 fbo_hi;
5174 };
5175 
5176 /* The roce task context of Mstorm */
5177 struct mstorm_rdma_task_st_ctx {
5178 	struct regpair temp[4];
5179 };
5180 
5181 /* The roce task context of Ustorm */
5182 struct ustorm_rdma_task_st_ctx {
5183 	struct regpair temp[6];
5184 };
5185 
5186 struct ustorm_rdma_task_ag_ctx {
5187 	u8 reserved;
5188 	u8 state;
5189 	__le16 icid;
5190 	u8 flags0;
5191 #define USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK		0xF
5192 #define USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT	0
5193 #define USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK		0x1
5194 #define USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT		4
5195 #define USTORM_RDMA_TASK_AG_CTX_BIT1_MASK			0x1
5196 #define USTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT			5
5197 #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK	0x3
5198 #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT	6
5199 	u8 flags1;
5200 #define USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK	0x3
5201 #define USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT	0
5202 #define USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK		0x3
5203 #define USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT		2
5204 #define USTORM_RDMA_TASK_AG_CTX_DIF_BLOCK_SIZE_MASK          0x3
5205 #define USTORM_RDMA_TASK_AG_CTX_DIF_BLOCK_SIZE_SHIFT         4
5206 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK		0x3
5207 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT		6
5208 	u8 flags2;
5209 #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK	0x1
5210 #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT	0
5211 #define USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK		0x1
5212 #define USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT		1
5213 #define USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK		0x1
5214 #define USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT		2
5215 #define USTORM_RDMA_TASK_AG_CTX_RESERVED4_MASK               0x1
5216 #define USTORM_RDMA_TASK_AG_CTX_RESERVED4_SHIFT              3
5217 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK		0x1
5218 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT	4
5219 #define USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK			0x1
5220 #define USTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT		5
5221 #define USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK			0x1
5222 #define USTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT		6
5223 #define USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK			0x1
5224 #define USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT		7
5225 	u8 flags3;
5226 #define USTORM_RDMA_TASK_AG_CTX_DIF_RXMIT_PROD_CONS_EN_MASK	0x1
5227 #define USTORM_RDMA_TASK_AG_CTX_DIF_RXMIT_PROD_CONS_EN_SHIFT	0
5228 #define USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK			0x1
5229 #define USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT		1
5230 #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_PROD_CONS_EN_MASK	0x1
5231 #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_PROD_CONS_EN_SHIFT	2
5232 #define USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK			0x1
5233 #define USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT		3
5234 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK		0xF
5235 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT		4
5236 	__le32 dif_err_intervals;
5237 	__le32 dif_error_1st_interval;
5238 	__le32 dif_rxmit_cons;
5239 	__le32 dif_rxmit_prod;
5240 	__le32 sge_index;
5241 	__le32 sq_cons;
5242 	u8 byte2;
5243 	u8 byte3;
5244 	__le16 dif_write_cons;
5245 	__le16 dif_write_prod;
5246 	__le16 word3;
5247 	__le32 dif_error_buffer_address_lo;
5248 	__le32 dif_error_buffer_address_hi;
5249 };
5250 
5251 /* RDMA task context */
5252 struct rdma_task_context {
5253 	struct ystorm_rdma_task_st_ctx ystorm_st_context;
5254 	struct ystorm_rdma_task_ag_ctx ystorm_ag_context;
5255 	struct tdif_task_context tdif_context;
5256 	struct mstorm_rdma_task_ag_ctx mstorm_ag_context;
5257 	struct mstorm_rdma_task_st_ctx mstorm_st_context;
5258 	struct rdif_task_context rdif_context;
5259 	struct ustorm_rdma_task_st_ctx ustorm_st_context;
5260 	struct regpair ustorm_st_padding[2];
5261 	struct ustorm_rdma_task_ag_ctx ustorm_ag_context;
5262 };
5263 
5264 #define TOE_MAX_RAMROD_PER_PF			8
5265 #define TOE_TX_PAGE_SIZE_BYTES			4096
5266 #define TOE_GRQ_PAGE_SIZE_BYTES			4096
5267 #define TOE_RX_CQ_PAGE_SIZE_BYTES		4096
5268 
5269 #define TOE_RX_MAX_RSS_CHAINS			64
5270 #define TOE_TX_MAX_TSS_CHAINS			64
5271 #define TOE_RSS_INDIRECTION_TABLE_SIZE		128
5272 
5273 /* The toe storm context of Mstorm */
5274 struct mstorm_toe_conn_st_ctx {
5275 	__le32 reserved[24];
5276 };
5277 
5278 /* The toe storm context of Pstorm */
5279 struct pstorm_toe_conn_st_ctx {
5280 	__le32 reserved[36];
5281 };
5282 
5283 /* The toe storm context of Ystorm */
5284 struct ystorm_toe_conn_st_ctx {
5285 	__le32 reserved[8];
5286 };
5287 
5288 /* The toe storm context of Xstorm */
5289 struct xstorm_toe_conn_st_ctx {
5290 	__le32 reserved[44];
5291 };
5292 
5293 struct ystorm_toe_conn_ag_ctx {
5294 	u8 byte0;
5295 	u8 byte1;
5296 	u8 flags0;
5297 #define YSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_MASK		0x1
5298 #define YSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT		0
5299 #define YSTORM_TOE_CONN_AG_CTX_BIT1_MASK			0x1
5300 #define YSTORM_TOE_CONN_AG_CTX_BIT1_SHIFT			1
5301 #define YSTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_MASK		0x3
5302 #define YSTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_SHIFT		2
5303 #define YSTORM_TOE_CONN_AG_CTX_RESET_RECEIVED_CF_MASK		0x3
5304 #define YSTORM_TOE_CONN_AG_CTX_RESET_RECEIVED_CF_SHIFT		4
5305 #define YSTORM_TOE_CONN_AG_CTX_CF2_MASK				0x3
5306 #define YSTORM_TOE_CONN_AG_CTX_CF2_SHIFT			6
5307 	u8 flags1;
5308 #define YSTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_EN_MASK		0x1
5309 #define YSTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_EN_SHIFT		0
5310 #define YSTORM_TOE_CONN_AG_CTX_RESET_RECEIVED_CF_EN_MASK	0x1
5311 #define YSTORM_TOE_CONN_AG_CTX_RESET_RECEIVED_CF_EN_SHIFT	1
5312 #define YSTORM_TOE_CONN_AG_CTX_CF2EN_MASK			0x1
5313 #define YSTORM_TOE_CONN_AG_CTX_CF2EN_SHIFT			2
5314 #define YSTORM_TOE_CONN_AG_CTX_REL_SEQ_EN_MASK			0x1
5315 #define YSTORM_TOE_CONN_AG_CTX_REL_SEQ_EN_SHIFT			3
5316 #define YSTORM_TOE_CONN_AG_CTX_RULE1EN_MASK			0x1
5317 #define YSTORM_TOE_CONN_AG_CTX_RULE1EN_SHIFT			4
5318 #define YSTORM_TOE_CONN_AG_CTX_RULE2EN_MASK			0x1
5319 #define YSTORM_TOE_CONN_AG_CTX_RULE2EN_SHIFT			5
5320 #define YSTORM_TOE_CONN_AG_CTX_RULE3EN_MASK			0x1
5321 #define YSTORM_TOE_CONN_AG_CTX_RULE3EN_SHIFT			6
5322 #define YSTORM_TOE_CONN_AG_CTX_CONS_PROD_EN_MASK		0x1
5323 #define YSTORM_TOE_CONN_AG_CTX_CONS_PROD_EN_SHIFT		7
5324 	u8 completion_opcode;
5325 	u8 byte3;
5326 	__le16 word0;
5327 	__le32 rel_seq;
5328 	__le32 rel_seq_threshold;
5329 	__le16 app_prod;
5330 	__le16 app_cons;
5331 	__le16 word3;
5332 	__le16 word4;
5333 	__le32 reg2;
5334 	__le32 reg3;
5335 };
5336 
5337 struct xstorm_toe_conn_ag_ctx {
5338 	u8 reserved0;
5339 	u8 state;
5340 	u8 flags0;
5341 #define XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_MASK		0x1
5342 #define XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT		0
5343 #define XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM1_MASK		0x1
5344 #define XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM1_SHIFT		1
5345 #define XSTORM_TOE_CONN_AG_CTX_RESERVED1_MASK			0x1
5346 #define XSTORM_TOE_CONN_AG_CTX_RESERVED1_SHIFT			2
5347 #define XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM3_MASK		0x1
5348 #define XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT		3
5349 #define XSTORM_TOE_CONN_AG_CTX_TX_DEC_RULE_RES_MASK		0x1
5350 #define XSTORM_TOE_CONN_AG_CTX_TX_DEC_RULE_RES_SHIFT		4
5351 #define XSTORM_TOE_CONN_AG_CTX_RESERVED2_MASK			0x1
5352 #define XSTORM_TOE_CONN_AG_CTX_RESERVED2_SHIFT			5
5353 #define XSTORM_TOE_CONN_AG_CTX_BIT6_MASK			0x1
5354 #define XSTORM_TOE_CONN_AG_CTX_BIT6_SHIFT			6
5355 #define XSTORM_TOE_CONN_AG_CTX_BIT7_MASK			0x1
5356 #define XSTORM_TOE_CONN_AG_CTX_BIT7_SHIFT			7
5357 	u8 flags1;
5358 #define XSTORM_TOE_CONN_AG_CTX_BIT8_MASK			0x1
5359 #define XSTORM_TOE_CONN_AG_CTX_BIT8_SHIFT			0
5360 #define XSTORM_TOE_CONN_AG_CTX_BIT9_MASK			0x1
5361 #define XSTORM_TOE_CONN_AG_CTX_BIT9_SHIFT			1
5362 #define XSTORM_TOE_CONN_AG_CTX_BIT10_MASK			0x1
5363 #define XSTORM_TOE_CONN_AG_CTX_BIT10_SHIFT			2
5364 #define XSTORM_TOE_CONN_AG_CTX_BIT11_MASK			0x1
5365 #define XSTORM_TOE_CONN_AG_CTX_BIT11_SHIFT			3
5366 #define XSTORM_TOE_CONN_AG_CTX_BIT12_MASK			0x1
5367 #define XSTORM_TOE_CONN_AG_CTX_BIT12_SHIFT			4
5368 #define XSTORM_TOE_CONN_AG_CTX_BIT13_MASK			0x1
5369 #define XSTORM_TOE_CONN_AG_CTX_BIT13_SHIFT			5
5370 #define XSTORM_TOE_CONN_AG_CTX_BIT14_MASK			0x1
5371 #define XSTORM_TOE_CONN_AG_CTX_BIT14_SHIFT			6
5372 #define XSTORM_TOE_CONN_AG_CTX_BIT15_MASK			0x1
5373 #define XSTORM_TOE_CONN_AG_CTX_BIT15_SHIFT			7
5374 	u8 flags2;
5375 #define XSTORM_TOE_CONN_AG_CTX_CF0_MASK				0x3
5376 #define XSTORM_TOE_CONN_AG_CTX_CF0_SHIFT			0
5377 #define XSTORM_TOE_CONN_AG_CTX_CF1_MASK				0x3
5378 #define XSTORM_TOE_CONN_AG_CTX_CF1_SHIFT			2
5379 #define XSTORM_TOE_CONN_AG_CTX_CF2_MASK				0x3
5380 #define XSTORM_TOE_CONN_AG_CTX_CF2_SHIFT			4
5381 #define XSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_MASK		0x3
5382 #define XSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT		6
5383 	u8 flags3;
5384 #define XSTORM_TOE_CONN_AG_CTX_CF4_MASK				0x3
5385 #define XSTORM_TOE_CONN_AG_CTX_CF4_SHIFT			0
5386 #define XSTORM_TOE_CONN_AG_CTX_CF5_MASK				0x3
5387 #define XSTORM_TOE_CONN_AG_CTX_CF5_SHIFT			2
5388 #define XSTORM_TOE_CONN_AG_CTX_CF6_MASK				0x3
5389 #define XSTORM_TOE_CONN_AG_CTX_CF6_SHIFT			4
5390 #define XSTORM_TOE_CONN_AG_CTX_CF7_MASK				0x3
5391 #define XSTORM_TOE_CONN_AG_CTX_CF7_SHIFT			6
5392 	u8 flags4;
5393 #define XSTORM_TOE_CONN_AG_CTX_CF8_MASK				0x3
5394 #define XSTORM_TOE_CONN_AG_CTX_CF8_SHIFT			0
5395 #define XSTORM_TOE_CONN_AG_CTX_CF9_MASK				0x3
5396 #define XSTORM_TOE_CONN_AG_CTX_CF9_SHIFT			2
5397 #define XSTORM_TOE_CONN_AG_CTX_CF10_MASK			0x3
5398 #define XSTORM_TOE_CONN_AG_CTX_CF10_SHIFT			4
5399 #define XSTORM_TOE_CONN_AG_CTX_CF11_MASK			0x3
5400 #define XSTORM_TOE_CONN_AG_CTX_CF11_SHIFT			6
5401 	u8 flags5;
5402 #define XSTORM_TOE_CONN_AG_CTX_CF12_MASK			0x3
5403 #define XSTORM_TOE_CONN_AG_CTX_CF12_SHIFT			0
5404 #define XSTORM_TOE_CONN_AG_CTX_CF13_MASK			0x3
5405 #define XSTORM_TOE_CONN_AG_CTX_CF13_SHIFT			2
5406 #define XSTORM_TOE_CONN_AG_CTX_CF14_MASK			0x3
5407 #define XSTORM_TOE_CONN_AG_CTX_CF14_SHIFT			4
5408 #define XSTORM_TOE_CONN_AG_CTX_CF15_MASK			0x3
5409 #define XSTORM_TOE_CONN_AG_CTX_CF15_SHIFT			6
5410 	u8 flags6;
5411 #define XSTORM_TOE_CONN_AG_CTX_CF16_MASK			0x3
5412 #define XSTORM_TOE_CONN_AG_CTX_CF16_SHIFT			0
5413 #define XSTORM_TOE_CONN_AG_CTX_CF17_MASK			0x3
5414 #define XSTORM_TOE_CONN_AG_CTX_CF17_SHIFT			2
5415 #define XSTORM_TOE_CONN_AG_CTX_CF18_MASK			0x3
5416 #define XSTORM_TOE_CONN_AG_CTX_CF18_SHIFT			4
5417 #define XSTORM_TOE_CONN_AG_CTX_DQ_FLUSH_MASK			0x3
5418 #define XSTORM_TOE_CONN_AG_CTX_DQ_FLUSH_SHIFT			6
5419 	u8 flags7;
5420 #define XSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_MASK			0x3
5421 #define XSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_SHIFT			0
5422 #define XSTORM_TOE_CONN_AG_CTX_FLUSH_Q1_MASK			0x3
5423 #define XSTORM_TOE_CONN_AG_CTX_FLUSH_Q1_SHIFT			2
5424 #define XSTORM_TOE_CONN_AG_CTX_SLOW_PATH_MASK			0x3
5425 #define XSTORM_TOE_CONN_AG_CTX_SLOW_PATH_SHIFT			4
5426 #define XSTORM_TOE_CONN_AG_CTX_CF0EN_MASK			0x1
5427 #define XSTORM_TOE_CONN_AG_CTX_CF0EN_SHIFT			6
5428 #define XSTORM_TOE_CONN_AG_CTX_CF1EN_MASK			0x1
5429 #define XSTORM_TOE_CONN_AG_CTX_CF1EN_SHIFT			7
5430 	u8 flags8;
5431 #define XSTORM_TOE_CONN_AG_CTX_CF2EN_MASK			0x1
5432 #define XSTORM_TOE_CONN_AG_CTX_CF2EN_SHIFT			0
5433 #define XSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK		0x1
5434 #define XSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT		1
5435 #define XSTORM_TOE_CONN_AG_CTX_CF4EN_MASK			0x1
5436 #define XSTORM_TOE_CONN_AG_CTX_CF4EN_SHIFT			2
5437 #define XSTORM_TOE_CONN_AG_CTX_CF5EN_MASK			0x1
5438 #define XSTORM_TOE_CONN_AG_CTX_CF5EN_SHIFT			3
5439 #define XSTORM_TOE_CONN_AG_CTX_CF6EN_MASK			0x1
5440 #define XSTORM_TOE_CONN_AG_CTX_CF6EN_SHIFT			4
5441 #define XSTORM_TOE_CONN_AG_CTX_CF7EN_MASK			0x1
5442 #define XSTORM_TOE_CONN_AG_CTX_CF7EN_SHIFT			5
5443 #define XSTORM_TOE_CONN_AG_CTX_CF8EN_MASK			0x1
5444 #define XSTORM_TOE_CONN_AG_CTX_CF8EN_SHIFT			6
5445 #define XSTORM_TOE_CONN_AG_CTX_CF9EN_MASK			0x1
5446 #define XSTORM_TOE_CONN_AG_CTX_CF9EN_SHIFT			7
5447 	u8 flags9;
5448 #define XSTORM_TOE_CONN_AG_CTX_CF10EN_MASK			0x1
5449 #define XSTORM_TOE_CONN_AG_CTX_CF10EN_SHIFT			0
5450 #define XSTORM_TOE_CONN_AG_CTX_CF11EN_MASK			0x1
5451 #define XSTORM_TOE_CONN_AG_CTX_CF11EN_SHIFT			1
5452 #define XSTORM_TOE_CONN_AG_CTX_CF12EN_MASK			0x1
5453 #define XSTORM_TOE_CONN_AG_CTX_CF12EN_SHIFT			2
5454 #define XSTORM_TOE_CONN_AG_CTX_CF13EN_MASK			0x1
5455 #define XSTORM_TOE_CONN_AG_CTX_CF13EN_SHIFT			3
5456 #define XSTORM_TOE_CONN_AG_CTX_CF14EN_MASK			0x1
5457 #define XSTORM_TOE_CONN_AG_CTX_CF14EN_SHIFT			4
5458 #define XSTORM_TOE_CONN_AG_CTX_CF15EN_MASK			0x1
5459 #define XSTORM_TOE_CONN_AG_CTX_CF15EN_SHIFT			5
5460 #define XSTORM_TOE_CONN_AG_CTX_CF16EN_MASK			0x1
5461 #define XSTORM_TOE_CONN_AG_CTX_CF16EN_SHIFT			6
5462 #define XSTORM_TOE_CONN_AG_CTX_CF17EN_MASK			0x1
5463 #define XSTORM_TOE_CONN_AG_CTX_CF17EN_SHIFT			7
5464 	u8 flags10;
5465 #define XSTORM_TOE_CONN_AG_CTX_CF18EN_MASK			0x1
5466 #define XSTORM_TOE_CONN_AG_CTX_CF18EN_SHIFT			0
5467 #define XSTORM_TOE_CONN_AG_CTX_DQ_FLUSH_EN_MASK			0x1
5468 #define XSTORM_TOE_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT		1
5469 #define XSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK			0x1
5470 #define XSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT		2
5471 #define XSTORM_TOE_CONN_AG_CTX_FLUSH_Q1_EN_MASK			0x1
5472 #define XSTORM_TOE_CONN_AG_CTX_FLUSH_Q1_EN_SHIFT		3
5473 #define XSTORM_TOE_CONN_AG_CTX_SLOW_PATH_EN_MASK		0x1
5474 #define XSTORM_TOE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT		4
5475 #define XSTORM_TOE_CONN_AG_CTX_CF23EN_MASK			0x1
5476 #define XSTORM_TOE_CONN_AG_CTX_CF23EN_SHIFT			5
5477 #define XSTORM_TOE_CONN_AG_CTX_RULE0EN_MASK			0x1
5478 #define XSTORM_TOE_CONN_AG_CTX_RULE0EN_SHIFT			6
5479 #define XSTORM_TOE_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_MASK	0x1
5480 #define XSTORM_TOE_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_SHIFT	7
5481 	u8 flags11;
5482 #define XSTORM_TOE_CONN_AG_CTX_TX_BLOCKED_EN_MASK		0x1
5483 #define XSTORM_TOE_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT		0
5484 #define XSTORM_TOE_CONN_AG_CTX_RULE3EN_MASK			0x1
5485 #define XSTORM_TOE_CONN_AG_CTX_RULE3EN_SHIFT			1
5486 #define XSTORM_TOE_CONN_AG_CTX_RESERVED3_MASK			0x1
5487 #define XSTORM_TOE_CONN_AG_CTX_RESERVED3_SHIFT			2
5488 #define XSTORM_TOE_CONN_AG_CTX_RULE5EN_MASK			0x1
5489 #define XSTORM_TOE_CONN_AG_CTX_RULE5EN_SHIFT			3
5490 #define XSTORM_TOE_CONN_AG_CTX_RULE6EN_MASK			0x1
5491 #define XSTORM_TOE_CONN_AG_CTX_RULE6EN_SHIFT			4
5492 #define XSTORM_TOE_CONN_AG_CTX_RULE7EN_MASK			0x1
5493 #define XSTORM_TOE_CONN_AG_CTX_RULE7EN_SHIFT			5
5494 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED1_MASK		0x1
5495 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED1_SHIFT		6
5496 #define XSTORM_TOE_CONN_AG_CTX_RULE9EN_MASK			0x1
5497 #define XSTORM_TOE_CONN_AG_CTX_RULE9EN_SHIFT			7
5498 	u8 flags12;
5499 #define XSTORM_TOE_CONN_AG_CTX_RULE10EN_MASK			0x1
5500 #define XSTORM_TOE_CONN_AG_CTX_RULE10EN_SHIFT			0
5501 #define XSTORM_TOE_CONN_AG_CTX_RULE11EN_MASK			0x1
5502 #define XSTORM_TOE_CONN_AG_CTX_RULE11EN_SHIFT			1
5503 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED2_MASK		0x1
5504 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED2_SHIFT		2
5505 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED3_MASK		0x1
5506 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED3_SHIFT		3
5507 #define XSTORM_TOE_CONN_AG_CTX_RULE14EN_MASK			0x1
5508 #define XSTORM_TOE_CONN_AG_CTX_RULE14EN_SHIFT			4
5509 #define XSTORM_TOE_CONN_AG_CTX_RULE15EN_MASK			0x1
5510 #define XSTORM_TOE_CONN_AG_CTX_RULE15EN_SHIFT			5
5511 #define XSTORM_TOE_CONN_AG_CTX_RULE16EN_MASK			0x1
5512 #define XSTORM_TOE_CONN_AG_CTX_RULE16EN_SHIFT			6
5513 #define XSTORM_TOE_CONN_AG_CTX_RULE17EN_MASK			0x1
5514 #define XSTORM_TOE_CONN_AG_CTX_RULE17EN_SHIFT			7
5515 	u8 flags13;
5516 #define XSTORM_TOE_CONN_AG_CTX_RULE18EN_MASK			0x1
5517 #define XSTORM_TOE_CONN_AG_CTX_RULE18EN_SHIFT			0
5518 #define XSTORM_TOE_CONN_AG_CTX_RULE19EN_MASK			0x1
5519 #define XSTORM_TOE_CONN_AG_CTX_RULE19EN_SHIFT			1
5520 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED4_MASK		0x1
5521 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED4_SHIFT		2
5522 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED5_MASK		0x1
5523 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED5_SHIFT		3
5524 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED6_MASK		0x1
5525 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED6_SHIFT		4
5526 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED7_MASK		0x1
5527 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED7_SHIFT		5
5528 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED8_MASK		0x1
5529 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED8_SHIFT		6
5530 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED9_MASK		0x1
5531 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED9_SHIFT		7
5532 	u8 flags14;
5533 #define XSTORM_TOE_CONN_AG_CTX_BIT16_MASK			0x1
5534 #define XSTORM_TOE_CONN_AG_CTX_BIT16_SHIFT			0
5535 #define XSTORM_TOE_CONN_AG_CTX_BIT17_MASK			0x1
5536 #define XSTORM_TOE_CONN_AG_CTX_BIT17_SHIFT			1
5537 #define XSTORM_TOE_CONN_AG_CTX_BIT18_MASK			0x1
5538 #define XSTORM_TOE_CONN_AG_CTX_BIT18_SHIFT			2
5539 #define XSTORM_TOE_CONN_AG_CTX_BIT19_MASK			0x1
5540 #define XSTORM_TOE_CONN_AG_CTX_BIT19_SHIFT			3
5541 #define XSTORM_TOE_CONN_AG_CTX_BIT20_MASK			0x1
5542 #define XSTORM_TOE_CONN_AG_CTX_BIT20_SHIFT			4
5543 #define XSTORM_TOE_CONN_AG_CTX_BIT21_MASK			0x1
5544 #define XSTORM_TOE_CONN_AG_CTX_BIT21_SHIFT			5
5545 #define XSTORM_TOE_CONN_AG_CTX_CF23_MASK			0x3
5546 #define XSTORM_TOE_CONN_AG_CTX_CF23_SHIFT			6
5547 	u8 byte2;
5548 	__le16 physical_q0;
5549 	__le16 physical_q1;
5550 	__le16 word2;
5551 	__le16 word3;
5552 	__le16 bd_prod;
5553 	__le16 word5;
5554 	__le16 word6;
5555 	u8 byte3;
5556 	u8 byte4;
5557 	u8 byte5;
5558 	u8 byte6;
5559 	__le32 reg0;
5560 	__le32 reg1;
5561 	__le32 reg2;
5562 	__le32 more_to_send_seq;
5563 	__le32 local_adv_wnd_seq;
5564 	__le32 reg5;
5565 	__le32 reg6;
5566 	__le16 word7;
5567 	__le16 word8;
5568 	__le16 word9;
5569 	__le16 word10;
5570 	__le32 reg7;
5571 	__le32 reg8;
5572 	__le32 reg9;
5573 	u8 byte7;
5574 	u8 byte8;
5575 	u8 byte9;
5576 	u8 byte10;
5577 	u8 byte11;
5578 	u8 byte12;
5579 	u8 byte13;
5580 	u8 byte14;
5581 	u8 byte15;
5582 	u8 e5_reserved;
5583 	__le16 word11;
5584 	__le32 reg10;
5585 	__le32 reg11;
5586 	__le32 reg12;
5587 	__le32 reg13;
5588 	__le32 reg14;
5589 	__le32 reg15;
5590 	__le32 reg16;
5591 	__le32 reg17;
5592 };
5593 
5594 struct tstorm_toe_conn_ag_ctx {
5595 	u8 reserved0;
5596 	u8 byte1;
5597 	u8 flags0;
5598 #define TSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_MASK		0x1
5599 #define TSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT		0
5600 #define TSTORM_TOE_CONN_AG_CTX_BIT1_MASK			0x1
5601 #define TSTORM_TOE_CONN_AG_CTX_BIT1_SHIFT			1
5602 #define TSTORM_TOE_CONN_AG_CTX_BIT2_MASK			0x1
5603 #define TSTORM_TOE_CONN_AG_CTX_BIT2_SHIFT			2
5604 #define TSTORM_TOE_CONN_AG_CTX_BIT3_MASK			0x1
5605 #define TSTORM_TOE_CONN_AG_CTX_BIT3_SHIFT			3
5606 #define TSTORM_TOE_CONN_AG_CTX_BIT4_MASK			0x1
5607 #define TSTORM_TOE_CONN_AG_CTX_BIT4_SHIFT			4
5608 #define TSTORM_TOE_CONN_AG_CTX_BIT5_MASK			0x1
5609 #define TSTORM_TOE_CONN_AG_CTX_BIT5_SHIFT			5
5610 #define TSTORM_TOE_CONN_AG_CTX_TIMEOUT_CF_MASK			0x3
5611 #define TSTORM_TOE_CONN_AG_CTX_TIMEOUT_CF_SHIFT			6
5612 	u8 flags1;
5613 #define TSTORM_TOE_CONN_AG_CTX_CF1_MASK				0x3
5614 #define TSTORM_TOE_CONN_AG_CTX_CF1_SHIFT			0
5615 #define TSTORM_TOE_CONN_AG_CTX_CF2_MASK				0x3
5616 #define TSTORM_TOE_CONN_AG_CTX_CF2_SHIFT			2
5617 #define TSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_MASK		0x3
5618 #define TSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT		4
5619 #define TSTORM_TOE_CONN_AG_CTX_CF4_MASK				0x3
5620 #define TSTORM_TOE_CONN_AG_CTX_CF4_SHIFT			6
5621 	u8 flags2;
5622 #define TSTORM_TOE_CONN_AG_CTX_CF5_MASK				0x3
5623 #define TSTORM_TOE_CONN_AG_CTX_CF5_SHIFT			0
5624 #define TSTORM_TOE_CONN_AG_CTX_CF6_MASK				0x3
5625 #define TSTORM_TOE_CONN_AG_CTX_CF6_SHIFT			2
5626 #define TSTORM_TOE_CONN_AG_CTX_CF7_MASK				0x3
5627 #define TSTORM_TOE_CONN_AG_CTX_CF7_SHIFT			4
5628 #define TSTORM_TOE_CONN_AG_CTX_CF8_MASK				0x3
5629 #define TSTORM_TOE_CONN_AG_CTX_CF8_SHIFT			6
5630 	u8 flags3;
5631 #define TSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_MASK			0x3
5632 #define TSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_SHIFT			0
5633 #define TSTORM_TOE_CONN_AG_CTX_CF10_MASK			0x3
5634 #define TSTORM_TOE_CONN_AG_CTX_CF10_SHIFT			2
5635 #define TSTORM_TOE_CONN_AG_CTX_TIMEOUT_CF_EN_MASK		0x1
5636 #define TSTORM_TOE_CONN_AG_CTX_TIMEOUT_CF_EN_SHIFT		4
5637 #define TSTORM_TOE_CONN_AG_CTX_CF1EN_MASK			0x1
5638 #define TSTORM_TOE_CONN_AG_CTX_CF1EN_SHIFT			5
5639 #define TSTORM_TOE_CONN_AG_CTX_CF2EN_MASK			0x1
5640 #define TSTORM_TOE_CONN_AG_CTX_CF2EN_SHIFT			6
5641 #define TSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK		0x1
5642 #define TSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT		7
5643 	u8 flags4;
5644 #define TSTORM_TOE_CONN_AG_CTX_CF4EN_MASK			0x1
5645 #define TSTORM_TOE_CONN_AG_CTX_CF4EN_SHIFT			0
5646 #define TSTORM_TOE_CONN_AG_CTX_CF5EN_MASK			0x1
5647 #define TSTORM_TOE_CONN_AG_CTX_CF5EN_SHIFT			1
5648 #define TSTORM_TOE_CONN_AG_CTX_CF6EN_MASK			0x1
5649 #define TSTORM_TOE_CONN_AG_CTX_CF6EN_SHIFT			2
5650 #define TSTORM_TOE_CONN_AG_CTX_CF7EN_MASK			0x1
5651 #define TSTORM_TOE_CONN_AG_CTX_CF7EN_SHIFT			3
5652 #define TSTORM_TOE_CONN_AG_CTX_CF8EN_MASK			0x1
5653 #define TSTORM_TOE_CONN_AG_CTX_CF8EN_SHIFT			4
5654 #define TSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK			0x1
5655 #define TSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT		5
5656 #define TSTORM_TOE_CONN_AG_CTX_CF10EN_MASK			0x1
5657 #define TSTORM_TOE_CONN_AG_CTX_CF10EN_SHIFT			6
5658 #define TSTORM_TOE_CONN_AG_CTX_RULE0EN_MASK			0x1
5659 #define TSTORM_TOE_CONN_AG_CTX_RULE0EN_SHIFT			7
5660 	u8 flags5;
5661 #define TSTORM_TOE_CONN_AG_CTX_RULE1EN_MASK			0x1
5662 #define TSTORM_TOE_CONN_AG_CTX_RULE1EN_SHIFT			0
5663 #define TSTORM_TOE_CONN_AG_CTX_RULE2EN_MASK			0x1
5664 #define TSTORM_TOE_CONN_AG_CTX_RULE2EN_SHIFT			1
5665 #define TSTORM_TOE_CONN_AG_CTX_RULE3EN_MASK			0x1
5666 #define TSTORM_TOE_CONN_AG_CTX_RULE3EN_SHIFT			2
5667 #define TSTORM_TOE_CONN_AG_CTX_RULE4EN_MASK			0x1
5668 #define TSTORM_TOE_CONN_AG_CTX_RULE4EN_SHIFT			3
5669 #define TSTORM_TOE_CONN_AG_CTX_RULE5EN_MASK			0x1
5670 #define TSTORM_TOE_CONN_AG_CTX_RULE5EN_SHIFT			4
5671 #define TSTORM_TOE_CONN_AG_CTX_RULE6EN_MASK			0x1
5672 #define TSTORM_TOE_CONN_AG_CTX_RULE6EN_SHIFT			5
5673 #define TSTORM_TOE_CONN_AG_CTX_RULE7EN_MASK			0x1
5674 #define TSTORM_TOE_CONN_AG_CTX_RULE7EN_SHIFT			6
5675 #define TSTORM_TOE_CONN_AG_CTX_RULE8EN_MASK			0x1
5676 #define TSTORM_TOE_CONN_AG_CTX_RULE8EN_SHIFT			7
5677 	__le32 reg0;
5678 	__le32 reg1;
5679 	__le32 reg2;
5680 	__le32 reg3;
5681 	__le32 reg4;
5682 	__le32 reg5;
5683 	__le32 reg6;
5684 	__le32 reg7;
5685 	__le32 reg8;
5686 	u8 byte2;
5687 	u8 byte3;
5688 	__le16 word0;
5689 };
5690 
5691 struct ustorm_toe_conn_ag_ctx {
5692 	u8 reserved;
5693 	u8 byte1;
5694 	u8 flags0;
5695 #define USTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_MASK		0x1
5696 #define USTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT		0
5697 #define USTORM_TOE_CONN_AG_CTX_BIT1_MASK			0x1
5698 #define USTORM_TOE_CONN_AG_CTX_BIT1_SHIFT			1
5699 #define USTORM_TOE_CONN_AG_CTX_CF0_MASK				0x3
5700 #define USTORM_TOE_CONN_AG_CTX_CF0_SHIFT			2
5701 #define USTORM_TOE_CONN_AG_CTX_CF1_MASK				0x3
5702 #define USTORM_TOE_CONN_AG_CTX_CF1_SHIFT			4
5703 #define USTORM_TOE_CONN_AG_CTX_PUSH_TIMER_CF_MASK		0x3
5704 #define USTORM_TOE_CONN_AG_CTX_PUSH_TIMER_CF_SHIFT		6
5705 	u8 flags1;
5706 #define USTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_MASK		0x3
5707 #define USTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT		0
5708 #define USTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_MASK		0x3
5709 #define USTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_SHIFT		2
5710 #define USTORM_TOE_CONN_AG_CTX_DQ_CF_MASK			0x3
5711 #define USTORM_TOE_CONN_AG_CTX_DQ_CF_SHIFT			4
5712 #define USTORM_TOE_CONN_AG_CTX_CF6_MASK				0x3
5713 #define USTORM_TOE_CONN_AG_CTX_CF6_SHIFT			6
5714 	u8 flags2;
5715 #define USTORM_TOE_CONN_AG_CTX_CF0EN_MASK			0x1
5716 #define USTORM_TOE_CONN_AG_CTX_CF0EN_SHIFT			0
5717 #define USTORM_TOE_CONN_AG_CTX_CF1EN_MASK			0x1
5718 #define USTORM_TOE_CONN_AG_CTX_CF1EN_SHIFT			1
5719 #define USTORM_TOE_CONN_AG_CTX_PUSH_TIMER_CF_EN_MASK		0x1
5720 #define USTORM_TOE_CONN_AG_CTX_PUSH_TIMER_CF_EN_SHIFT		2
5721 #define USTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK		0x1
5722 #define USTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT		3
5723 #define USTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_EN_MASK		0x1
5724 #define USTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_EN_SHIFT		4
5725 #define USTORM_TOE_CONN_AG_CTX_DQ_CF_EN_MASK			0x1
5726 #define USTORM_TOE_CONN_AG_CTX_DQ_CF_EN_SHIFT			5
5727 #define USTORM_TOE_CONN_AG_CTX_CF6EN_MASK			0x1
5728 #define USTORM_TOE_CONN_AG_CTX_CF6EN_SHIFT			6
5729 #define USTORM_TOE_CONN_AG_CTX_RULE0EN_MASK			0x1
5730 #define USTORM_TOE_CONN_AG_CTX_RULE0EN_SHIFT			7
5731 	u8 flags3;
5732 #define USTORM_TOE_CONN_AG_CTX_RULE1EN_MASK			0x1
5733 #define USTORM_TOE_CONN_AG_CTX_RULE1EN_SHIFT			0
5734 #define USTORM_TOE_CONN_AG_CTX_RULE2EN_MASK			0x1
5735 #define USTORM_TOE_CONN_AG_CTX_RULE2EN_SHIFT			1
5736 #define USTORM_TOE_CONN_AG_CTX_RULE3EN_MASK			0x1
5737 #define USTORM_TOE_CONN_AG_CTX_RULE3EN_SHIFT			2
5738 #define USTORM_TOE_CONN_AG_CTX_RULE4EN_MASK			0x1
5739 #define USTORM_TOE_CONN_AG_CTX_RULE4EN_SHIFT			3
5740 #define USTORM_TOE_CONN_AG_CTX_RULE5EN_MASK			0x1
5741 #define USTORM_TOE_CONN_AG_CTX_RULE5EN_SHIFT			4
5742 #define USTORM_TOE_CONN_AG_CTX_RULE6EN_MASK			0x1
5743 #define USTORM_TOE_CONN_AG_CTX_RULE6EN_SHIFT			5
5744 #define USTORM_TOE_CONN_AG_CTX_RULE7EN_MASK			0x1
5745 #define USTORM_TOE_CONN_AG_CTX_RULE7EN_SHIFT			6
5746 #define USTORM_TOE_CONN_AG_CTX_RULE8EN_MASK			0x1
5747 #define USTORM_TOE_CONN_AG_CTX_RULE8EN_SHIFT			7
5748 	u8 byte2;
5749 	u8 byte3;
5750 	__le16 word0;
5751 	__le16 word1;
5752 	__le32 reg0;
5753 	__le32 reg1;
5754 	__le32 reg2;
5755 	__le32 reg3;
5756 	__le16 word2;
5757 	__le16 word3;
5758 };
5759 
5760 /* The toe storm context of Tstorm */
5761 struct tstorm_toe_conn_st_ctx {
5762 	__le32 reserved[16];
5763 };
5764 
5765 /* The toe storm context of Ustorm */
5766 struct ustorm_toe_conn_st_ctx {
5767 	__le32 reserved[52];
5768 };
5769 
5770 /* toe connection context */
5771 struct toe_conn_context {
5772 	struct ystorm_toe_conn_st_ctx ystorm_st_context;
5773 	struct pstorm_toe_conn_st_ctx pstorm_st_context;
5774 	struct regpair pstorm_st_padding[2];
5775 	struct xstorm_toe_conn_st_ctx xstorm_st_context;
5776 	struct regpair xstorm_st_padding[2];
5777 	struct ystorm_toe_conn_ag_ctx ystorm_ag_context;
5778 	struct xstorm_toe_conn_ag_ctx xstorm_ag_context;
5779 	struct tstorm_toe_conn_ag_ctx tstorm_ag_context;
5780 	struct regpair tstorm_ag_padding[2];
5781 	struct timers_context timer_context;
5782 	struct ustorm_toe_conn_ag_ctx ustorm_ag_context;
5783 	struct tstorm_toe_conn_st_ctx tstorm_st_context;
5784 	struct mstorm_toe_conn_st_ctx mstorm_st_context;
5785 	struct ustorm_toe_conn_st_ctx ustorm_st_context;
5786 };
5787 
5788 /* toe init ramrod header */
5789 struct toe_init_ramrod_header {
5790 	u8 first_rss;
5791 	u8 num_rss;
5792 	u8 reserved[6];
5793 };
5794 
5795 /* toe pf init parameters */
5796 struct toe_pf_init_params {
5797 	__le32 push_timeout;
5798 	__le16 grq_buffer_size;
5799 	__le16 grq_sb_id;
5800 	u8 grq_sb_index;
5801 	u8 max_seg_retransmit;
5802 	u8 doubt_reachability;
5803 	u8 ll2_rx_queue_id;
5804 	__le16 grq_fetch_threshold;
5805 	u8 reserved1[2];
5806 	struct regpair grq_page_addr;
5807 };
5808 
5809 /* toe tss parameters */
5810 struct toe_tss_params {
5811 	struct regpair curr_page_addr;
5812 	struct regpair next_page_addr;
5813 	u8 reserved0;
5814 	u8 status_block_index;
5815 	__le16 status_block_id;
5816 	__le16 reserved1[2];
5817 };
5818 
5819 /* toe rss parameters */
5820 struct toe_rss_params {
5821 	struct regpair curr_page_addr;
5822 	struct regpair next_page_addr;
5823 	u8 reserved0;
5824 	u8 status_block_index;
5825 	__le16 status_block_id;
5826 	__le16 reserved1[2];
5827 };
5828 
5829 /* toe init ramrod data */
5830 struct toe_init_ramrod_data {
5831 	struct toe_init_ramrod_header hdr;
5832 	struct tcp_init_params tcp_params;
5833 	struct toe_pf_init_params pf_params;
5834 	struct toe_tss_params tss_params[TOE_TX_MAX_TSS_CHAINS];
5835 	struct toe_rss_params rss_params[TOE_RX_MAX_RSS_CHAINS];
5836 };
5837 
5838 /* toe offload parameters */
5839 struct toe_offload_params {
5840 	struct regpair tx_bd_page_addr;
5841 	struct regpair tx_app_page_addr;
5842 	__le32 more_to_send_seq;
5843 	__le16 rcv_indication_size;
5844 	u8 rss_tss_id;
5845 	u8 ignore_grq_push;
5846 	struct regpair rx_db_data_ptr;
5847 };
5848 
5849 /* TOE offload ramrod data - DMAed by firmware */
5850 struct toe_offload_ramrod_data {
5851 	struct tcp_offload_params tcp_ofld_params;
5852 	struct toe_offload_params toe_ofld_params;
5853 };
5854 
5855 /* TOE ramrod command IDs */
5856 enum toe_ramrod_cmd_id {
5857 	TOE_RAMROD_UNUSED,
5858 	TOE_RAMROD_FUNC_INIT,
5859 	TOE_RAMROD_INITATE_OFFLOAD,
5860 	TOE_RAMROD_FUNC_CLOSE,
5861 	TOE_RAMROD_SEARCHER_DELETE,
5862 	TOE_RAMROD_TERMINATE,
5863 	TOE_RAMROD_QUERY,
5864 	TOE_RAMROD_UPDATE,
5865 	TOE_RAMROD_EMPTY,
5866 	TOE_RAMROD_RESET_SEND,
5867 	TOE_RAMROD_INVALIDATE,
5868 	MAX_TOE_RAMROD_CMD_ID
5869 };
5870 
5871 /* Toe RQ buffer descriptor */
5872 struct toe_rx_bd {
5873 	struct regpair addr;
5874 	__le16 size;
5875 	__le16 flags;
5876 #define TOE_RX_BD_START_MASK		0x1
5877 #define TOE_RX_BD_START_SHIFT		0
5878 #define TOE_RX_BD_END_MASK		0x1
5879 #define TOE_RX_BD_END_SHIFT		1
5880 #define TOE_RX_BD_NO_PUSH_MASK		0x1
5881 #define TOE_RX_BD_NO_PUSH_SHIFT		2
5882 #define TOE_RX_BD_SPLIT_MASK		0x1
5883 #define TOE_RX_BD_SPLIT_SHIFT		3
5884 #define TOE_RX_BD_RESERVED0_MASK	0xFFF
5885 #define TOE_RX_BD_RESERVED0_SHIFT	4
5886 	__le32 reserved1;
5887 };
5888 
5889 /* TOE RX completion queue opcodes (opcode 0 is illegal) */
5890 enum toe_rx_cmp_opcode {
5891 	TOE_RX_CMP_OPCODE_GA = 1,
5892 	TOE_RX_CMP_OPCODE_GR = 2,
5893 	TOE_RX_CMP_OPCODE_GNI = 3,
5894 	TOE_RX_CMP_OPCODE_GAIR = 4,
5895 	TOE_RX_CMP_OPCODE_GAIL = 5,
5896 	TOE_RX_CMP_OPCODE_GRI = 6,
5897 	TOE_RX_CMP_OPCODE_GJ = 7,
5898 	TOE_RX_CMP_OPCODE_DGI = 8,
5899 	TOE_RX_CMP_OPCODE_CMP = 9,
5900 	TOE_RX_CMP_OPCODE_REL = 10,
5901 	TOE_RX_CMP_OPCODE_SKP = 11,
5902 	TOE_RX_CMP_OPCODE_URG = 12,
5903 	TOE_RX_CMP_OPCODE_RT_TO = 13,
5904 	TOE_RX_CMP_OPCODE_KA_TO = 14,
5905 	TOE_RX_CMP_OPCODE_MAX_RT = 15,
5906 	TOE_RX_CMP_OPCODE_DBT_RE = 16,
5907 	TOE_RX_CMP_OPCODE_SYN = 17,
5908 	TOE_RX_CMP_OPCODE_OPT_ERR = 18,
5909 	TOE_RX_CMP_OPCODE_FW2_TO = 19,
5910 	TOE_RX_CMP_OPCODE_2WY_CLS = 20,
5911 	TOE_RX_CMP_OPCODE_RST_RCV = 21,
5912 	TOE_RX_CMP_OPCODE_FIN_RCV = 22,
5913 	TOE_RX_CMP_OPCODE_FIN_UPL = 23,
5914 	TOE_RX_CMP_OPCODE_INIT = 32,
5915 	TOE_RX_CMP_OPCODE_RSS_UPDATE = 33,
5916 	TOE_RX_CMP_OPCODE_CLOSE = 34,
5917 	TOE_RX_CMP_OPCODE_INITIATE_OFFLOAD = 80,
5918 	TOE_RX_CMP_OPCODE_SEARCHER_DELETE = 81,
5919 	TOE_RX_CMP_OPCODE_TERMINATE = 82,
5920 	TOE_RX_CMP_OPCODE_QUERY = 83,
5921 	TOE_RX_CMP_OPCODE_RESET_SEND = 84,
5922 	TOE_RX_CMP_OPCODE_INVALIDATE = 85,
5923 	TOE_RX_CMP_OPCODE_EMPTY = 86,
5924 	TOE_RX_CMP_OPCODE_UPDATE = 87,
5925 	MAX_TOE_RX_CMP_OPCODE
5926 };
5927 
5928 /* TOE rx ooo completion data */
5929 struct toe_rx_cqe_ooo_params {
5930 	__le32 nbytes;
5931 	__le16 grq_buff_id;
5932 	u8 isle_num;
5933 	u8 reserved0;
5934 };
5935 
5936 /* TOE rx in order completion data */
5937 struct toe_rx_cqe_in_order_params {
5938 	__le32 nbytes;
5939 	__le16 grq_buff_id;
5940 	__le16 reserved1;
5941 };
5942 
5943 /* Union for TOE rx completion data */
5944 union toe_rx_cqe_data_union {
5945 	struct toe_rx_cqe_ooo_params ooo_params;
5946 	struct toe_rx_cqe_in_order_params in_order_params;
5947 	struct regpair raw_data;
5948 };
5949 
5950 /* TOE rx completion element */
5951 struct toe_rx_cqe {
5952 	__le16 icid;
5953 	u8 completion_opcode;
5954 	u8 reserved0;
5955 	__le32 reserved1;
5956 	union toe_rx_cqe_data_union data;
5957 };
5958 
5959 /* toe RX doorbel data */
5960 struct toe_rx_db_data {
5961 	__le32 local_adv_wnd_seq;
5962 	__le32 reserved[3];
5963 };
5964 
5965 /* Toe GRQ buffer descriptor */
5966 struct toe_rx_grq_bd {
5967 	struct regpair addr;
5968 	__le16 buff_id;
5969 	__le16 reserved0;
5970 	__le32 reserved1;
5971 };
5972 
5973 /* Toe transmission application buffer descriptor */
5974 struct toe_tx_app_buff_desc {
5975 	__le32 next_buffer_start_seq;
5976 	__le32 reserved;
5977 };
5978 
5979 /* Toe transmission application buffer descriptor page pointer */
5980 struct toe_tx_app_buff_page_pointer {
5981 	struct regpair next_page_addr;
5982 };
5983 
5984 /* Toe transmission buffer descriptor */
5985 struct toe_tx_bd {
5986 	struct regpair addr;
5987 	__le16 size;
5988 	__le16 flags;
5989 #define TOE_TX_BD_PUSH_MASK		0x1
5990 #define TOE_TX_BD_PUSH_SHIFT		0
5991 #define TOE_TX_BD_NOTIFY_MASK		0x1
5992 #define TOE_TX_BD_NOTIFY_SHIFT		1
5993 #define TOE_TX_BD_LARGE_IO_MASK		0x1
5994 #define TOE_TX_BD_LARGE_IO_SHIFT	2
5995 #define TOE_TX_BD_BD_CONS_MASK		0x1FFF
5996 #define TOE_TX_BD_BD_CONS_SHIFT		3
5997 	__le32 next_bd_start_seq;
5998 };
5999 
6000 /* TOE completion opcodes */
6001 enum toe_tx_cmp_opcode {
6002 	TOE_TX_CMP_OPCODE_DATA,
6003 	TOE_TX_CMP_OPCODE_TERMINATE,
6004 	TOE_TX_CMP_OPCODE_EMPTY,
6005 	TOE_TX_CMP_OPCODE_RESET_SEND,
6006 	TOE_TX_CMP_OPCODE_INVALIDATE,
6007 	TOE_TX_CMP_OPCODE_RST_RCV,
6008 	MAX_TOE_TX_CMP_OPCODE
6009 };
6010 
6011 /* Toe transmission completion element */
6012 struct toe_tx_cqe {
6013 	__le16 icid;
6014 	u8 opcode;
6015 	u8 reserved;
6016 	__le32 size;
6017 };
6018 
6019 /* Toe transmission page pointer bd */
6020 struct toe_tx_page_pointer_bd {
6021 	struct regpair next_page_addr;
6022 	struct regpair prev_page_addr;
6023 };
6024 
6025 /* Toe transmission completion element page pointer */
6026 struct toe_tx_page_pointer_cqe {
6027 	struct regpair next_page_addr;
6028 };
6029 
6030 /* toe update parameters */
6031 struct toe_update_params {
6032 	__le16 flags;
6033 #define TOE_UPDATE_PARAMS_RCV_INDICATION_SIZE_CHANGED_MASK	0x1
6034 #define TOE_UPDATE_PARAMS_RCV_INDICATION_SIZE_CHANGED_SHIFT	0
6035 #define TOE_UPDATE_PARAMS_RESERVED_MASK				0x7FFF
6036 #define TOE_UPDATE_PARAMS_RESERVED_SHIFT			1
6037 	__le16 rcv_indication_size;
6038 	__le16 reserved1[2];
6039 };
6040 
6041 /* TOE update ramrod data - DMAed by firmware */
6042 struct toe_update_ramrod_data {
6043 	struct tcp_update_params tcp_upd_params;
6044 	struct toe_update_params toe_upd_params;
6045 };
6046 
6047 struct mstorm_toe_conn_ag_ctx {
6048 	u8 byte0;
6049 	u8 byte1;
6050 	u8 flags0;
6051 #define MSTORM_TOE_CONN_AG_CTX_BIT0_MASK	0x1
6052 #define MSTORM_TOE_CONN_AG_CTX_BIT0_SHIFT	0
6053 #define MSTORM_TOE_CONN_AG_CTX_BIT1_MASK	0x1
6054 #define MSTORM_TOE_CONN_AG_CTX_BIT1_SHIFT	1
6055 #define MSTORM_TOE_CONN_AG_CTX_CF0_MASK		0x3
6056 #define MSTORM_TOE_CONN_AG_CTX_CF0_SHIFT	2
6057 #define MSTORM_TOE_CONN_AG_CTX_CF1_MASK		0x3
6058 #define MSTORM_TOE_CONN_AG_CTX_CF1_SHIFT	4
6059 #define MSTORM_TOE_CONN_AG_CTX_CF2_MASK		0x3
6060 #define MSTORM_TOE_CONN_AG_CTX_CF2_SHIFT	6
6061 	u8 flags1;
6062 #define MSTORM_TOE_CONN_AG_CTX_CF0EN_MASK	0x1
6063 #define MSTORM_TOE_CONN_AG_CTX_CF0EN_SHIFT	0
6064 #define MSTORM_TOE_CONN_AG_CTX_CF1EN_MASK	0x1
6065 #define MSTORM_TOE_CONN_AG_CTX_CF1EN_SHIFT	1
6066 #define MSTORM_TOE_CONN_AG_CTX_CF2EN_MASK	0x1
6067 #define MSTORM_TOE_CONN_AG_CTX_CF2EN_SHIFT	2
6068 #define MSTORM_TOE_CONN_AG_CTX_RULE0EN_MASK	0x1
6069 #define MSTORM_TOE_CONN_AG_CTX_RULE0EN_SHIFT	3
6070 #define MSTORM_TOE_CONN_AG_CTX_RULE1EN_MASK	0x1
6071 #define MSTORM_TOE_CONN_AG_CTX_RULE1EN_SHIFT	4
6072 #define MSTORM_TOE_CONN_AG_CTX_RULE2EN_MASK	0x1
6073 #define MSTORM_TOE_CONN_AG_CTX_RULE2EN_SHIFT	5
6074 #define MSTORM_TOE_CONN_AG_CTX_RULE3EN_MASK	0x1
6075 #define MSTORM_TOE_CONN_AG_CTX_RULE3EN_SHIFT	6
6076 #define MSTORM_TOE_CONN_AG_CTX_RULE4EN_MASK	0x1
6077 #define MSTORM_TOE_CONN_AG_CTX_RULE4EN_SHIFT	7
6078 	__le16 word0;
6079 	__le16 word1;
6080 	__le32 reg0;
6081 	__le32 reg1;
6082 };
6083 
6084 /* TOE doorbell data */
6085 struct toe_db_data {
6086 	u8 params;
6087 #define TOE_DB_DATA_DEST_MASK			0x3
6088 #define TOE_DB_DATA_DEST_SHIFT			0
6089 #define TOE_DB_DATA_AGG_CMD_MASK		0x3
6090 #define TOE_DB_DATA_AGG_CMD_SHIFT		2
6091 #define TOE_DB_DATA_BYPASS_EN_MASK		0x1
6092 #define TOE_DB_DATA_BYPASS_EN_SHIFT		4
6093 #define TOE_DB_DATA_RESERVED_MASK		0x1
6094 #define TOE_DB_DATA_RESERVED_SHIFT		5
6095 #define TOE_DB_DATA_AGG_VAL_SEL_MASK		0x3
6096 #define TOE_DB_DATA_AGG_VAL_SEL_SHIFT		6
6097 	u8 agg_flags;
6098 	__le16 bd_prod;
6099 };
6100 
6101 /* rdma function init ramrod data */
6102 struct rdma_close_func_ramrod_data {
6103 	u8 cnq_start_offset;
6104 	u8 num_cnqs;
6105 	u8 vf_id;
6106 	u8 vf_valid;
6107 	u8 reserved[4];
6108 };
6109 
6110 /* rdma function init CNQ parameters */
6111 struct rdma_cnq_params {
6112 	__le16 sb_num;
6113 	u8 sb_index;
6114 	u8 num_pbl_pages;
6115 	__le32 reserved;
6116 	struct regpair pbl_base_addr;
6117 	__le16 queue_zone_num;
6118 	u8 reserved1[6];
6119 };
6120 
6121 /* rdma create cq ramrod data */
6122 struct rdma_create_cq_ramrod_data {
6123 	struct regpair cq_handle;
6124 	struct regpair pbl_addr;
6125 	__le32 max_cqes;
6126 	__le16 pbl_num_pages;
6127 	__le16 dpi;
6128 	u8 is_two_level_pbl;
6129 	u8 cnq_id;
6130 	u8 pbl_log_page_size;
6131 	u8 toggle_bit;
6132 	__le16 int_timeout;
6133 	u8 vf_id;
6134 	u8 flags;
6135 #define RDMA_CREATE_CQ_RAMROD_DATA_VF_ID_VALID_MASK  0x1
6136 #define RDMA_CREATE_CQ_RAMROD_DATA_VF_ID_VALID_SHIFT 0
6137 #define RDMA_CREATE_CQ_RAMROD_DATA_RESERVED1_MASK    0x7F
6138 #define RDMA_CREATE_CQ_RAMROD_DATA_RESERVED1_SHIFT   1
6139 };
6140 
6141 /* rdma deregister tid ramrod data */
6142 struct rdma_deregister_tid_ramrod_data {
6143 	__le32 itid;
6144 	__le32 reserved;
6145 };
6146 
6147 /* rdma destroy cq output params */
6148 struct rdma_destroy_cq_output_params {
6149 	__le16 cnq_num;
6150 	__le16 reserved0;
6151 	__le32 reserved1;
6152 };
6153 
6154 /* rdma destroy cq ramrod data */
6155 struct rdma_destroy_cq_ramrod_data {
6156 	struct regpair output_params_addr;
6157 };
6158 
6159 /* RDMA slow path EQ cmd IDs */
6160 enum rdma_event_opcode {
6161 	RDMA_EVENT_UNUSED,
6162 	RDMA_EVENT_FUNC_INIT,
6163 	RDMA_EVENT_FUNC_CLOSE,
6164 	RDMA_EVENT_REGISTER_MR,
6165 	RDMA_EVENT_DEREGISTER_MR,
6166 	RDMA_EVENT_CREATE_CQ,
6167 	RDMA_EVENT_RESIZE_CQ,
6168 	RDMA_EVENT_DESTROY_CQ,
6169 	RDMA_EVENT_CREATE_SRQ,
6170 	RDMA_EVENT_MODIFY_SRQ,
6171 	RDMA_EVENT_DESTROY_SRQ,
6172 	RDMA_EVENT_START_NAMESPACE_TRACKING,
6173 	RDMA_EVENT_STOP_NAMESPACE_TRACKING,
6174 	MAX_RDMA_EVENT_OPCODE
6175 };
6176 
6177 /* RDMA FW return code for slow path ramrods */
6178 enum rdma_fw_return_code {
6179 	RDMA_RETURN_OK = 0,
6180 	RDMA_RETURN_REGISTER_MR_BAD_STATE_ERR,
6181 	RDMA_RETURN_DEREGISTER_MR_BAD_STATE_ERR,
6182 	RDMA_RETURN_RESIZE_CQ_ERR,
6183 	RDMA_RETURN_NIG_DRAIN_REQ,
6184 	RDMA_RETURN_GENERAL_ERR,
6185 	MAX_RDMA_FW_RETURN_CODE
6186 };
6187 
6188 /* rdma function init header */
6189 struct rdma_init_func_hdr {
6190 	u8 cnq_start_offset;
6191 	u8 num_cnqs;
6192 	u8 cq_ring_mode;
6193 	u8 vf_id;
6194 	u8 vf_valid;
6195 	u8 relaxed_ordering;
6196 	__le16 first_reg_srq_id;
6197 	__le32 reg_srq_base_addr;
6198 	u8 flags;
6199 #define RDMA_INIT_FUNC_HDR_SEARCHER_MODE_MASK		0x1
6200 #define RDMA_INIT_FUNC_HDR_SEARCHER_MODE_SHIFT		0
6201 #define RDMA_INIT_FUNC_HDR_PVRDMA_MODE_MASK		0x1
6202 #define RDMA_INIT_FUNC_HDR_PVRDMA_MODE_SHIFT		1
6203 #define RDMA_INIT_FUNC_HDR_DPT_MODE_MASK		0x1
6204 #define RDMA_INIT_FUNC_HDR_DPT_MODE_SHIFT		2
6205 #define RDMA_INIT_FUNC_HDR_RESERVED0_MASK		0x1F
6206 #define RDMA_INIT_FUNC_HDR_RESERVED0_SHIFT		3
6207 	u8 dpt_byte_threshold_log;
6208 	u8 dpt_common_queue_id;
6209 	u8 max_num_ns_log;
6210 };
6211 
6212 /* rdma function init ramrod data */
6213 struct rdma_init_func_ramrod_data {
6214 	struct rdma_init_func_hdr params_header;
6215 	struct rdma_cnq_params dptq_params;
6216 	struct rdma_cnq_params cnq_params[NUM_OF_GLOBAL_QUEUES];
6217 };
6218 
6219 /* rdma namespace tracking ramrod data */
6220 struct rdma_namespace_tracking_ramrod_data {
6221 	u8 name_space;
6222 	u8 reserved[7];
6223 };
6224 
6225 /* RDMA ramrod command IDs */
6226 enum rdma_ramrod_cmd_id {
6227 	RDMA_RAMROD_UNUSED,
6228 	RDMA_RAMROD_FUNC_INIT,
6229 	RDMA_RAMROD_FUNC_CLOSE,
6230 	RDMA_RAMROD_REGISTER_MR,
6231 	RDMA_RAMROD_DEREGISTER_MR,
6232 	RDMA_RAMROD_CREATE_CQ,
6233 	RDMA_RAMROD_RESIZE_CQ,
6234 	RDMA_RAMROD_DESTROY_CQ,
6235 	RDMA_RAMROD_CREATE_SRQ,
6236 	RDMA_RAMROD_MODIFY_SRQ,
6237 	RDMA_RAMROD_DESTROY_SRQ,
6238 	RDMA_RAMROD_START_NS_TRACKING,
6239 	RDMA_RAMROD_STOP_NS_TRACKING,
6240 	MAX_RDMA_RAMROD_CMD_ID
6241 };
6242 
6243 /* rdma register tid ramrod data */
6244 struct rdma_register_tid_ramrod_data {
6245 	__le16 flags;
6246 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_MASK	0x1F
6247 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_SHIFT	0
6248 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_MASK	0x1
6249 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_SHIFT	5
6250 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_MASK		0x1
6251 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_SHIFT		6
6252 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_MASK		0x1
6253 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_SHIFT		7
6254 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_MASK		0x1
6255 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_SHIFT		8
6256 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_MASK		0x1
6257 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_SHIFT	9
6258 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_MASK	0x1
6259 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_SHIFT	10
6260 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_MASK		0x1
6261 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_SHIFT		11
6262 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_MASK		0x1
6263 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_SHIFT		12
6264 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_MASK	0x1
6265 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_SHIFT	13
6266 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_MASK		0x3
6267 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_SHIFT		14
6268 	u8 flags1;
6269 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_MASK	0x1F
6270 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_SHIFT	0
6271 #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_MASK		0x7
6272 #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_SHIFT		5
6273 	u8 flags2;
6274 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_MASK		0x1
6275 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_SHIFT		0
6276 #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_MASK	0x1
6277 #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_SHIFT	1
6278 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_MASK		0x3F
6279 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_SHIFT		2
6280 	u8 key;
6281 	u8 length_hi;
6282 	u8 vf_id;
6283 	u8 vf_valid;
6284 	__le16 pd;
6285 	__le16 reserved2;
6286 	__le32 length_lo;
6287 	__le32 itid;
6288 	__le32 reserved3;
6289 	struct regpair va;
6290 	struct regpair pbl_base;
6291 	struct regpair dif_error_addr;
6292 	__le32 reserved4[4];
6293 };
6294 
6295 /* rdma resize cq output params */
6296 struct rdma_resize_cq_output_params {
6297 	__le32 old_cq_cons;
6298 	__le32 old_cq_prod;
6299 };
6300 
6301 /* rdma resize cq ramrod data */
6302 struct rdma_resize_cq_ramrod_data {
6303 	u8 flags;
6304 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_MASK		0x1
6305 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_SHIFT		0
6306 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_MASK	0x1
6307 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_SHIFT	1
6308 #define RDMA_RESIZE_CQ_RAMROD_DATA_VF_ID_VALID_MASK		0x1
6309 #define RDMA_RESIZE_CQ_RAMROD_DATA_VF_ID_VALID_SHIFT		2
6310 #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_MASK		0x1F
6311 #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_SHIFT		3
6312 	u8 pbl_log_page_size;
6313 	__le16 pbl_num_pages;
6314 	__le32 max_cqes;
6315 	struct regpair pbl_addr;
6316 	struct regpair output_params_addr;
6317 	u8 vf_id;
6318 	u8 reserved1[7];
6319 };
6320 
6321 /* The rdma SRQ context */
6322 struct rdma_srq_context {
6323 	struct regpair temp[8];
6324 };
6325 
6326 /* rdma create qp requester ramrod data */
6327 struct rdma_srq_create_ramrod_data {
6328 	u8 flags;
6329 #define RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG_MASK         0x1
6330 #define RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG_SHIFT        0
6331 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED_KEY_EN_MASK  0x1
6332 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED_KEY_EN_SHIFT 1
6333 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED1_MASK        0x3F
6334 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED1_SHIFT       2
6335 	u8 reserved2;
6336 	__le16 xrc_domain;
6337 	__le32 xrc_srq_cq_cid;
6338 	struct regpair pbl_base_addr;
6339 	__le16 pages_in_srq_pbl;
6340 	__le16 pd_id;
6341 	struct rdma_srq_id srq_id;
6342 	__le16 page_size;
6343 	__le16 reserved3;
6344 	__le32 reserved4;
6345 	struct regpair producers_addr;
6346 };
6347 
6348 /* rdma create qp requester ramrod data */
6349 struct rdma_srq_destroy_ramrod_data {
6350 	struct rdma_srq_id srq_id;
6351 	__le32 reserved;
6352 };
6353 
6354 /* rdma create qp requester ramrod data */
6355 struct rdma_srq_modify_ramrod_data {
6356 	struct rdma_srq_id srq_id;
6357 	__le32 wqe_limit;
6358 };
6359 
6360 /* RDMA Tid type enumeration (for register_tid ramrod) */
6361 enum rdma_tid_type {
6362 	RDMA_TID_REGISTERED_MR,
6363 	RDMA_TID_FMR,
6364 	RDMA_TID_MW,
6365 	MAX_RDMA_TID_TYPE
6366 };
6367 
6368 /* The rdma XRC SRQ context */
6369 struct rdma_xrc_srq_context {
6370 	struct regpair temp[9];
6371 };
6372 
6373 struct tstorm_rdma_task_ag_ctx {
6374 	u8 byte0;
6375 	u8 byte1;
6376 	__le16 word0;
6377 	u8 flags0;
6378 #define TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK		0xF
6379 #define TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT	0
6380 #define TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK		0x1
6381 #define TSTORM_RDMA_TASK_AG_CTX_BIT0_SHIFT		4
6382 #define TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK		0x1
6383 #define TSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT		5
6384 #define TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK		0x1
6385 #define TSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT		6
6386 #define TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK		0x1
6387 #define TSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT		7
6388 	u8 flags1;
6389 #define TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK	0x1
6390 #define TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT	0
6391 #define TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK	0x1
6392 #define TSTORM_RDMA_TASK_AG_CTX_BIT5_SHIFT	1
6393 #define TSTORM_RDMA_TASK_AG_CTX_CF0_MASK	0x3
6394 #define TSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT	2
6395 #define TSTORM_RDMA_TASK_AG_CTX_CF1_MASK	0x3
6396 #define TSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT	4
6397 #define TSTORM_RDMA_TASK_AG_CTX_CF2_MASK	0x3
6398 #define TSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT	6
6399 	u8 flags2;
6400 #define TSTORM_RDMA_TASK_AG_CTX_CF3_MASK	0x3
6401 #define TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT	0
6402 #define TSTORM_RDMA_TASK_AG_CTX_CF4_MASK	0x3
6403 #define TSTORM_RDMA_TASK_AG_CTX_CF4_SHIFT	2
6404 #define TSTORM_RDMA_TASK_AG_CTX_CF5_MASK	0x3
6405 #define TSTORM_RDMA_TASK_AG_CTX_CF5_SHIFT	4
6406 #define TSTORM_RDMA_TASK_AG_CTX_CF6_MASK	0x3
6407 #define TSTORM_RDMA_TASK_AG_CTX_CF6_SHIFT	6
6408 	u8 flags3;
6409 #define TSTORM_RDMA_TASK_AG_CTX_CF7_MASK	0x3
6410 #define TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT	0
6411 #define TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK	0x1
6412 #define TSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT	2
6413 #define TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK	0x1
6414 #define TSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT	3
6415 #define TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK	0x1
6416 #define TSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT	4
6417 #define TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK	0x1
6418 #define TSTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT	5
6419 #define TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK	0x1
6420 #define TSTORM_RDMA_TASK_AG_CTX_CF4EN_SHIFT	6
6421 #define TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK	0x1
6422 #define TSTORM_RDMA_TASK_AG_CTX_CF5EN_SHIFT	7
6423 	u8 flags4;
6424 #define TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK		0x1
6425 #define TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT		0
6426 #define TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK		0x1
6427 #define TSTORM_RDMA_TASK_AG_CTX_CF7EN_SHIFT		1
6428 #define TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK		0x1
6429 #define TSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT	2
6430 #define TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK		0x1
6431 #define TSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT	3
6432 #define TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK		0x1
6433 #define TSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT	4
6434 #define TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK		0x1
6435 #define TSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT	5
6436 #define TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK		0x1
6437 #define TSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT	6
6438 #define TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK		0x1
6439 #define TSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT	7
6440 	u8 byte2;
6441 	__le16 word1;
6442 	__le32 reg0;
6443 	u8 byte3;
6444 	u8 byte4;
6445 	__le16 word2;
6446 	__le16 word3;
6447 	__le16 word4;
6448 	__le32 reg1;
6449 	__le32 reg2;
6450 };
6451 
6452 struct ustorm_rdma_conn_ag_ctx {
6453 	u8 reserved;
6454 	u8 byte1;
6455 	u8 flags0;
6456 #define USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
6457 #define USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
6458 #define USTORM_RDMA_CONN_AG_CTX_DIF_ERROR_REPORTED_MASK  0x1
6459 #define USTORM_RDMA_CONN_AG_CTX_DIF_ERROR_REPORTED_SHIFT 1
6460 #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK	0x3
6461 #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT	2
6462 #define USTORM_RDMA_CONN_AG_CTX_CF1_MASK		0x3
6463 #define USTORM_RDMA_CONN_AG_CTX_CF1_SHIFT		4
6464 #define USTORM_RDMA_CONN_AG_CTX_CF2_MASK		0x3
6465 #define USTORM_RDMA_CONN_AG_CTX_CF2_SHIFT		6
6466 	u8 flags1;
6467 #define USTORM_RDMA_CONN_AG_CTX_CF3_MASK		0x3
6468 #define USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT		0
6469 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK	0x3
6470 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT	2
6471 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK	0x3
6472 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_SHIFT	4
6473 #define USTORM_RDMA_CONN_AG_CTX_CF6_MASK		0x3
6474 #define USTORM_RDMA_CONN_AG_CTX_CF6_SHIFT		6
6475 	u8 flags2;
6476 #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK		0x1
6477 #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT		0
6478 #define USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK			0x1
6479 #define USTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT			1
6480 #define USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK			0x1
6481 #define USTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT			2
6482 #define USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK			0x1
6483 #define USTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT			3
6484 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK		0x1
6485 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT	4
6486 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK		0x1
6487 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT		5
6488 #define USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK			0x1
6489 #define USTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT			6
6490 #define USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK		0x1
6491 #define USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_SHIFT		7
6492 	u8 flags3;
6493 #define USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK		0x1
6494 #define USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT		0
6495 #define USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK		0x1
6496 #define USTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT	1
6497 #define USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK		0x1
6498 #define USTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT	2
6499 #define USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK		0x1
6500 #define USTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT	3
6501 #define USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK		0x1
6502 #define USTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT	4
6503 #define USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK		0x1
6504 #define USTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT	5
6505 #define USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK		0x1
6506 #define USTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT	6
6507 #define USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK		0x1
6508 #define USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT	7
6509 	u8 byte2;
6510 	u8 nvmf_only;
6511 	__le16 conn_dpi;
6512 	__le16 word1;
6513 	__le32 cq_cons;
6514 	__le32 cq_se_prod;
6515 	__le32 cq_prod;
6516 	__le32 reg3;
6517 	__le16 int_timeout;
6518 	__le16 word3;
6519 };
6520 
6521 struct xstorm_roce_conn_ag_ctx {
6522 	u8 reserved0;
6523 	u8 state;
6524 	u8 flags0;
6525 #define XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_MASK      0x1
6526 #define XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT     0
6527 #define XSTORM_ROCE_CONN_AG_CTX_BIT1_MASK              0x1
6528 #define XSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT             1
6529 #define XSTORM_ROCE_CONN_AG_CTX_BIT2_MASK              0x1
6530 #define XSTORM_ROCE_CONN_AG_CTX_BIT2_SHIFT             2
6531 #define XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM3_MASK      0x1
6532 #define XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT     3
6533 #define XSTORM_ROCE_CONN_AG_CTX_BIT4_MASK              0x1
6534 #define XSTORM_ROCE_CONN_AG_CTX_BIT4_SHIFT             4
6535 #define XSTORM_ROCE_CONN_AG_CTX_BIT5_MASK              0x1
6536 #define XSTORM_ROCE_CONN_AG_CTX_BIT5_SHIFT             5
6537 #define XSTORM_ROCE_CONN_AG_CTX_BIT6_MASK              0x1
6538 #define XSTORM_ROCE_CONN_AG_CTX_BIT6_SHIFT             6
6539 #define XSTORM_ROCE_CONN_AG_CTX_BIT7_MASK              0x1
6540 #define XSTORM_ROCE_CONN_AG_CTX_BIT7_SHIFT             7
6541 	u8 flags1;
6542 #define XSTORM_ROCE_CONN_AG_CTX_BIT8_MASK              0x1
6543 #define XSTORM_ROCE_CONN_AG_CTX_BIT8_SHIFT             0
6544 #define XSTORM_ROCE_CONN_AG_CTX_BIT9_MASK              0x1
6545 #define XSTORM_ROCE_CONN_AG_CTX_BIT9_SHIFT             1
6546 #define XSTORM_ROCE_CONN_AG_CTX_BIT10_MASK             0x1
6547 #define XSTORM_ROCE_CONN_AG_CTX_BIT10_SHIFT            2
6548 #define XSTORM_ROCE_CONN_AG_CTX_BIT11_MASK             0x1
6549 #define XSTORM_ROCE_CONN_AG_CTX_BIT11_SHIFT            3
6550 #define XSTORM_ROCE_CONN_AG_CTX_MSDM_FLUSH_MASK        0x1
6551 #define XSTORM_ROCE_CONN_AG_CTX_MSDM_FLUSH_SHIFT       4
6552 #define XSTORM_ROCE_CONN_AG_CTX_MSEM_FLUSH_MASK        0x1
6553 #define XSTORM_ROCE_CONN_AG_CTX_MSEM_FLUSH_SHIFT       5
6554 #define XSTORM_ROCE_CONN_AG_CTX_BIT14_MASK	       0x1
6555 #define XSTORM_ROCE_CONN_AG_CTX_BIT14_SHIFT	       6
6556 #define XSTORM_ROCE_CONN_AG_CTX_YSTORM_FLUSH_MASK      0x1
6557 #define XSTORM_ROCE_CONN_AG_CTX_YSTORM_FLUSH_SHIFT     7
6558 	u8 flags2;
6559 #define XSTORM_ROCE_CONN_AG_CTX_CF0_MASK               0x3
6560 #define XSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT              0
6561 #define XSTORM_ROCE_CONN_AG_CTX_CF1_MASK               0x3
6562 #define XSTORM_ROCE_CONN_AG_CTX_CF1_SHIFT              2
6563 #define XSTORM_ROCE_CONN_AG_CTX_CF2_MASK               0x3
6564 #define XSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT              4
6565 #define XSTORM_ROCE_CONN_AG_CTX_CF3_MASK               0x3
6566 #define XSTORM_ROCE_CONN_AG_CTX_CF3_SHIFT              6
6567 	u8 flags3;
6568 #define XSTORM_ROCE_CONN_AG_CTX_CF4_MASK               0x3
6569 #define XSTORM_ROCE_CONN_AG_CTX_CF4_SHIFT              0
6570 #define XSTORM_ROCE_CONN_AG_CTX_CF5_MASK               0x3
6571 #define XSTORM_ROCE_CONN_AG_CTX_CF5_SHIFT              2
6572 #define XSTORM_ROCE_CONN_AG_CTX_CF6_MASK               0x3
6573 #define XSTORM_ROCE_CONN_AG_CTX_CF6_SHIFT              4
6574 #define XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_MASK       0x3
6575 #define XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT      6
6576 	u8 flags4;
6577 #define XSTORM_ROCE_CONN_AG_CTX_CF8_MASK               0x3
6578 #define XSTORM_ROCE_CONN_AG_CTX_CF8_SHIFT              0
6579 #define XSTORM_ROCE_CONN_AG_CTX_CF9_MASK               0x3
6580 #define XSTORM_ROCE_CONN_AG_CTX_CF9_SHIFT              2
6581 #define XSTORM_ROCE_CONN_AG_CTX_CF10_MASK              0x3
6582 #define XSTORM_ROCE_CONN_AG_CTX_CF10_SHIFT             4
6583 #define XSTORM_ROCE_CONN_AG_CTX_CF11_MASK              0x3
6584 #define XSTORM_ROCE_CONN_AG_CTX_CF11_SHIFT             6
6585 	u8 flags5;
6586 #define XSTORM_ROCE_CONN_AG_CTX_CF12_MASK              0x3
6587 #define XSTORM_ROCE_CONN_AG_CTX_CF12_SHIFT             0
6588 #define XSTORM_ROCE_CONN_AG_CTX_CF13_MASK              0x3
6589 #define XSTORM_ROCE_CONN_AG_CTX_CF13_SHIFT             2
6590 #define XSTORM_ROCE_CONN_AG_CTX_CF14_MASK              0x3
6591 #define XSTORM_ROCE_CONN_AG_CTX_CF14_SHIFT             4
6592 #define XSTORM_ROCE_CONN_AG_CTX_CF15_MASK              0x3
6593 #define XSTORM_ROCE_CONN_AG_CTX_CF15_SHIFT             6
6594 	u8 flags6;
6595 #define XSTORM_ROCE_CONN_AG_CTX_CF16_MASK              0x3
6596 #define XSTORM_ROCE_CONN_AG_CTX_CF16_SHIFT             0
6597 #define XSTORM_ROCE_CONN_AG_CTX_CF17_MASK              0x3
6598 #define XSTORM_ROCE_CONN_AG_CTX_CF17_SHIFT             2
6599 #define XSTORM_ROCE_CONN_AG_CTX_CF18_MASK              0x3
6600 #define XSTORM_ROCE_CONN_AG_CTX_CF18_SHIFT             4
6601 #define XSTORM_ROCE_CONN_AG_CTX_CF19_MASK              0x3
6602 #define XSTORM_ROCE_CONN_AG_CTX_CF19_SHIFT             6
6603 	u8 flags7;
6604 #define XSTORM_ROCE_CONN_AG_CTX_CF20_MASK              0x3
6605 #define XSTORM_ROCE_CONN_AG_CTX_CF20_SHIFT             0
6606 #define XSTORM_ROCE_CONN_AG_CTX_CF21_MASK              0x3
6607 #define XSTORM_ROCE_CONN_AG_CTX_CF21_SHIFT             2
6608 #define XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_MASK         0x3
6609 #define XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_SHIFT        4
6610 #define XSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK             0x1
6611 #define XSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT            6
6612 #define XSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK             0x1
6613 #define XSTORM_ROCE_CONN_AG_CTX_CF1EN_SHIFT            7
6614 	u8 flags8;
6615 #define XSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK             0x1
6616 #define XSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT            0
6617 #define XSTORM_ROCE_CONN_AG_CTX_CF3EN_MASK             0x1
6618 #define XSTORM_ROCE_CONN_AG_CTX_CF3EN_SHIFT            1
6619 #define XSTORM_ROCE_CONN_AG_CTX_CF4EN_MASK             0x1
6620 #define XSTORM_ROCE_CONN_AG_CTX_CF4EN_SHIFT            2
6621 #define XSTORM_ROCE_CONN_AG_CTX_CF5EN_MASK             0x1
6622 #define XSTORM_ROCE_CONN_AG_CTX_CF5EN_SHIFT            3
6623 #define XSTORM_ROCE_CONN_AG_CTX_CF6EN_MASK             0x1
6624 #define XSTORM_ROCE_CONN_AG_CTX_CF6EN_SHIFT            4
6625 #define XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK    0x1
6626 #define XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT   5
6627 #define XSTORM_ROCE_CONN_AG_CTX_CF8EN_MASK             0x1
6628 #define XSTORM_ROCE_CONN_AG_CTX_CF8EN_SHIFT            6
6629 #define XSTORM_ROCE_CONN_AG_CTX_CF9EN_MASK             0x1
6630 #define XSTORM_ROCE_CONN_AG_CTX_CF9EN_SHIFT            7
6631 	u8 flags9;
6632 #define XSTORM_ROCE_CONN_AG_CTX_CF10EN_MASK            0x1
6633 #define XSTORM_ROCE_CONN_AG_CTX_CF10EN_SHIFT           0
6634 #define XSTORM_ROCE_CONN_AG_CTX_CF11EN_MASK            0x1
6635 #define XSTORM_ROCE_CONN_AG_CTX_CF11EN_SHIFT           1
6636 #define XSTORM_ROCE_CONN_AG_CTX_CF12EN_MASK            0x1
6637 #define XSTORM_ROCE_CONN_AG_CTX_CF12EN_SHIFT           2
6638 #define XSTORM_ROCE_CONN_AG_CTX_CF13EN_MASK            0x1
6639 #define XSTORM_ROCE_CONN_AG_CTX_CF13EN_SHIFT           3
6640 #define XSTORM_ROCE_CONN_AG_CTX_CF14EN_MASK            0x1
6641 #define XSTORM_ROCE_CONN_AG_CTX_CF14EN_SHIFT           4
6642 #define XSTORM_ROCE_CONN_AG_CTX_CF15EN_MASK            0x1
6643 #define XSTORM_ROCE_CONN_AG_CTX_CF15EN_SHIFT           5
6644 #define XSTORM_ROCE_CONN_AG_CTX_CF16EN_MASK            0x1
6645 #define XSTORM_ROCE_CONN_AG_CTX_CF16EN_SHIFT           6
6646 #define XSTORM_ROCE_CONN_AG_CTX_CF17EN_MASK            0x1
6647 #define XSTORM_ROCE_CONN_AG_CTX_CF17EN_SHIFT           7
6648 	u8 flags10;
6649 #define XSTORM_ROCE_CONN_AG_CTX_CF18EN_MASK            0x1
6650 #define XSTORM_ROCE_CONN_AG_CTX_CF18EN_SHIFT           0
6651 #define XSTORM_ROCE_CONN_AG_CTX_CF19EN_MASK            0x1
6652 #define XSTORM_ROCE_CONN_AG_CTX_CF19EN_SHIFT           1
6653 #define XSTORM_ROCE_CONN_AG_CTX_CF20EN_MASK            0x1
6654 #define XSTORM_ROCE_CONN_AG_CTX_CF20EN_SHIFT           2
6655 #define XSTORM_ROCE_CONN_AG_CTX_CF21EN_MASK            0x1
6656 #define XSTORM_ROCE_CONN_AG_CTX_CF21EN_SHIFT           3
6657 #define XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_EN_MASK      0x1
6658 #define XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT     4
6659 #define XSTORM_ROCE_CONN_AG_CTX_CF23EN_MASK            0x1
6660 #define XSTORM_ROCE_CONN_AG_CTX_CF23EN_SHIFT           5
6661 #define XSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK           0x1
6662 #define XSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT          6
6663 #define XSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK           0x1
6664 #define XSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT          7
6665 	u8 flags11;
6666 #define XSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK           0x1
6667 #define XSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT          0
6668 #define XSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK           0x1
6669 #define XSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT          1
6670 #define XSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK           0x1
6671 #define XSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT          2
6672 #define XSTORM_ROCE_CONN_AG_CTX_RULE5EN_MASK           0x1
6673 #define XSTORM_ROCE_CONN_AG_CTX_RULE5EN_SHIFT          3
6674 #define XSTORM_ROCE_CONN_AG_CTX_RULE6EN_MASK           0x1
6675 #define XSTORM_ROCE_CONN_AG_CTX_RULE6EN_SHIFT          4
6676 #define XSTORM_ROCE_CONN_AG_CTX_RULE7EN_MASK           0x1
6677 #define XSTORM_ROCE_CONN_AG_CTX_RULE7EN_SHIFT          5
6678 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED1_MASK      0x1
6679 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED1_SHIFT     6
6680 #define XSTORM_ROCE_CONN_AG_CTX_RULE9EN_MASK           0x1
6681 #define XSTORM_ROCE_CONN_AG_CTX_RULE9EN_SHIFT          7
6682 	u8 flags12;
6683 #define XSTORM_ROCE_CONN_AG_CTX_RULE10EN_MASK          0x1
6684 #define XSTORM_ROCE_CONN_AG_CTX_RULE10EN_SHIFT         0
6685 #define XSTORM_ROCE_CONN_AG_CTX_RULE11EN_MASK          0x1
6686 #define XSTORM_ROCE_CONN_AG_CTX_RULE11EN_SHIFT         1
6687 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED2_MASK      0x1
6688 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED2_SHIFT     2
6689 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED3_MASK      0x1
6690 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED3_SHIFT     3
6691 #define XSTORM_ROCE_CONN_AG_CTX_RULE14EN_MASK          0x1
6692 #define XSTORM_ROCE_CONN_AG_CTX_RULE14EN_SHIFT         4
6693 #define XSTORM_ROCE_CONN_AG_CTX_RULE15EN_MASK          0x1
6694 #define XSTORM_ROCE_CONN_AG_CTX_RULE15EN_SHIFT         5
6695 #define XSTORM_ROCE_CONN_AG_CTX_RULE16EN_MASK          0x1
6696 #define XSTORM_ROCE_CONN_AG_CTX_RULE16EN_SHIFT         6
6697 #define XSTORM_ROCE_CONN_AG_CTX_RULE17EN_MASK          0x1
6698 #define XSTORM_ROCE_CONN_AG_CTX_RULE17EN_SHIFT         7
6699 	u8 flags13;
6700 #define XSTORM_ROCE_CONN_AG_CTX_RULE18EN_MASK          0x1
6701 #define XSTORM_ROCE_CONN_AG_CTX_RULE18EN_SHIFT         0
6702 #define XSTORM_ROCE_CONN_AG_CTX_RULE19EN_MASK          0x1
6703 #define XSTORM_ROCE_CONN_AG_CTX_RULE19EN_SHIFT         1
6704 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED4_MASK      0x1
6705 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED4_SHIFT     2
6706 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED5_MASK      0x1
6707 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED5_SHIFT     3
6708 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED6_MASK      0x1
6709 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED6_SHIFT     4
6710 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED7_MASK      0x1
6711 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED7_SHIFT     5
6712 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED8_MASK      0x1
6713 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED8_SHIFT     6
6714 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED9_MASK      0x1
6715 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED9_SHIFT     7
6716 	u8 flags14;
6717 #define XSTORM_ROCE_CONN_AG_CTX_MIGRATION_MASK         0x1
6718 #define XSTORM_ROCE_CONN_AG_CTX_MIGRATION_SHIFT        0
6719 #define XSTORM_ROCE_CONN_AG_CTX_BIT17_MASK             0x1
6720 #define XSTORM_ROCE_CONN_AG_CTX_BIT17_SHIFT            1
6721 #define XSTORM_ROCE_CONN_AG_CTX_DPM_PORT_NUM_MASK      0x3
6722 #define XSTORM_ROCE_CONN_AG_CTX_DPM_PORT_NUM_SHIFT     2
6723 #define XSTORM_ROCE_CONN_AG_CTX_RESERVED_MASK          0x1
6724 #define XSTORM_ROCE_CONN_AG_CTX_RESERVED_SHIFT         4
6725 #define XSTORM_ROCE_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK  0x1
6726 #define XSTORM_ROCE_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
6727 #define XSTORM_ROCE_CONN_AG_CTX_CF23_MASK              0x3
6728 #define XSTORM_ROCE_CONN_AG_CTX_CF23_SHIFT             6
6729 	u8 byte2;
6730 	__le16 physical_q0;
6731 	__le16 word1;
6732 	__le16 word2;
6733 	__le16 word3;
6734 	__le16 word4;
6735 	__le16 word5;
6736 	__le16 conn_dpi;
6737 	u8 byte3;
6738 	u8 byte4;
6739 	u8 byte5;
6740 	u8 byte6;
6741 	__le32 reg0;
6742 	__le32 reg1;
6743 	__le32 reg2;
6744 	__le32 snd_nxt_psn;
6745 	__le32 reg4;
6746 	__le32 reg5;
6747 	__le32 reg6;
6748 };
6749 
6750 struct tstorm_roce_conn_ag_ctx {
6751 	u8 reserved0;
6752 	u8 byte1;
6753 	u8 flags0;
6754 #define TSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_MASK          0x1
6755 #define TSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT         0
6756 #define TSTORM_ROCE_CONN_AG_CTX_BIT1_MASK                  0x1
6757 #define TSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT                 1
6758 #define TSTORM_ROCE_CONN_AG_CTX_BIT2_MASK                  0x1
6759 #define TSTORM_ROCE_CONN_AG_CTX_BIT2_SHIFT                 2
6760 #define TSTORM_ROCE_CONN_AG_CTX_BIT3_MASK                  0x1
6761 #define TSTORM_ROCE_CONN_AG_CTX_BIT3_SHIFT                 3
6762 #define TSTORM_ROCE_CONN_AG_CTX_BIT4_MASK                  0x1
6763 #define TSTORM_ROCE_CONN_AG_CTX_BIT4_SHIFT                 4
6764 #define TSTORM_ROCE_CONN_AG_CTX_BIT5_MASK                  0x1
6765 #define TSTORM_ROCE_CONN_AG_CTX_BIT5_SHIFT                 5
6766 #define TSTORM_ROCE_CONN_AG_CTX_CF0_MASK                   0x3
6767 #define TSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT                  6
6768 	u8 flags1;
6769 #define TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK       0x3
6770 #define TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT      0
6771 #define TSTORM_ROCE_CONN_AG_CTX_CF2_MASK                   0x3
6772 #define TSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT                  2
6773 #define TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK     0x3
6774 #define TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT    4
6775 #define TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_MASK           0x3
6776 #define TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT          6
6777 	u8 flags2;
6778 #define TSTORM_ROCE_CONN_AG_CTX_CF5_MASK                   0x3
6779 #define TSTORM_ROCE_CONN_AG_CTX_CF5_SHIFT                  0
6780 #define TSTORM_ROCE_CONN_AG_CTX_CF6_MASK                   0x3
6781 #define TSTORM_ROCE_CONN_AG_CTX_CF6_SHIFT                  2
6782 #define TSTORM_ROCE_CONN_AG_CTX_CF7_MASK                   0x3
6783 #define TSTORM_ROCE_CONN_AG_CTX_CF7_SHIFT                  4
6784 #define TSTORM_ROCE_CONN_AG_CTX_CF8_MASK                   0x3
6785 #define TSTORM_ROCE_CONN_AG_CTX_CF8_SHIFT                  6
6786 	u8 flags3;
6787 #define TSTORM_ROCE_CONN_AG_CTX_CF9_MASK                   0x3
6788 #define TSTORM_ROCE_CONN_AG_CTX_CF9_SHIFT                  0
6789 #define TSTORM_ROCE_CONN_AG_CTX_CF10_MASK                  0x3
6790 #define TSTORM_ROCE_CONN_AG_CTX_CF10_SHIFT                 2
6791 #define TSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK                 0x1
6792 #define TSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT                4
6793 #define TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK    0x1
6794 #define TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT   5
6795 #define TSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK                 0x1
6796 #define TSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT                6
6797 #define TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK  0x1
6798 #define TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
6799 	u8 flags4;
6800 #define TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK        0x1
6801 #define TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT       0
6802 #define TSTORM_ROCE_CONN_AG_CTX_CF5EN_MASK                 0x1
6803 #define TSTORM_ROCE_CONN_AG_CTX_CF5EN_SHIFT                1
6804 #define TSTORM_ROCE_CONN_AG_CTX_CF6EN_MASK                 0x1
6805 #define TSTORM_ROCE_CONN_AG_CTX_CF6EN_SHIFT                2
6806 #define TSTORM_ROCE_CONN_AG_CTX_CF7EN_MASK                 0x1
6807 #define TSTORM_ROCE_CONN_AG_CTX_CF7EN_SHIFT                3
6808 #define TSTORM_ROCE_CONN_AG_CTX_CF8EN_MASK                 0x1
6809 #define TSTORM_ROCE_CONN_AG_CTX_CF8EN_SHIFT                4
6810 #define TSTORM_ROCE_CONN_AG_CTX_CF9EN_MASK                 0x1
6811 #define TSTORM_ROCE_CONN_AG_CTX_CF9EN_SHIFT                5
6812 #define TSTORM_ROCE_CONN_AG_CTX_CF10EN_MASK                0x1
6813 #define TSTORM_ROCE_CONN_AG_CTX_CF10EN_SHIFT               6
6814 #define TSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK               0x1
6815 #define TSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT              7
6816 	u8 flags5;
6817 #define TSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK               0x1
6818 #define TSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT              0
6819 #define TSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK               0x1
6820 #define TSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT              1
6821 #define TSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK               0x1
6822 #define TSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT              2
6823 #define TSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK               0x1
6824 #define TSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT              3
6825 #define TSTORM_ROCE_CONN_AG_CTX_RULE5EN_MASK               0x1
6826 #define TSTORM_ROCE_CONN_AG_CTX_RULE5EN_SHIFT              4
6827 #define TSTORM_ROCE_CONN_AG_CTX_RULE6EN_MASK               0x1
6828 #define TSTORM_ROCE_CONN_AG_CTX_RULE6EN_SHIFT              5
6829 #define TSTORM_ROCE_CONN_AG_CTX_RULE7EN_MASK               0x1
6830 #define TSTORM_ROCE_CONN_AG_CTX_RULE7EN_SHIFT              6
6831 #define TSTORM_ROCE_CONN_AG_CTX_RULE8EN_MASK               0x1
6832 #define TSTORM_ROCE_CONN_AG_CTX_RULE8EN_SHIFT              7
6833 	__le32 reg0;
6834 	__le32 reg1;
6835 	__le32 reg2;
6836 	__le32 reg3;
6837 	__le32 reg4;
6838 	__le32 reg5;
6839 	__le32 reg6;
6840 	__le32 reg7;
6841 	__le32 reg8;
6842 	u8 byte2;
6843 	u8 byte3;
6844 	__le16 word0;
6845 	u8 byte4;
6846 	u8 byte5;
6847 	__le16 word1;
6848 	__le16 word2;
6849 	__le16 word3;
6850 	__le32 reg9;
6851 	__le32 reg10;
6852 };
6853 
6854 /* The roce storm context of Ystorm */
6855 struct ystorm_roce_conn_st_ctx {
6856 	struct regpair temp[2];
6857 };
6858 
6859 /* The roce storm context of Mstorm */
6860 struct pstorm_roce_conn_st_ctx {
6861 	struct regpair temp[16];
6862 };
6863 
6864 /* The roce storm context of Xstorm */
6865 struct xstorm_roce_conn_st_ctx {
6866 	struct regpair temp[24];
6867 };
6868 
6869 /* The roce storm context of Tstorm */
6870 struct tstorm_roce_conn_st_ctx {
6871 	struct regpair temp[30];
6872 };
6873 
6874 /* The roce storm context of Mstorm */
6875 struct mstorm_roce_conn_st_ctx {
6876 	struct regpair temp[6];
6877 };
6878 
6879 /* The roce storm context of Ustorm */
6880 struct ustorm_roce_conn_st_ctx {
6881 	struct regpair temp[14];
6882 };
6883 
6884 /* roce connection context */
6885 struct roce_conn_context {
6886 	struct ystorm_roce_conn_st_ctx ystorm_st_context;
6887 	struct regpair ystorm_st_padding[2];
6888 	struct pstorm_roce_conn_st_ctx pstorm_st_context;
6889 	struct xstorm_roce_conn_st_ctx xstorm_st_context;
6890 	struct xstorm_roce_conn_ag_ctx xstorm_ag_context;
6891 	struct tstorm_roce_conn_ag_ctx tstorm_ag_context;
6892 	struct timers_context timer_context;
6893 	struct ustorm_rdma_conn_ag_ctx ustorm_ag_context;
6894 	struct tstorm_roce_conn_st_ctx tstorm_st_context;
6895 	struct regpair tstorm_st_padding[2];
6896 	struct mstorm_roce_conn_st_ctx mstorm_st_context;
6897 	struct regpair mstorm_st_padding[2];
6898 	struct ustorm_roce_conn_st_ctx ustorm_st_context;
6899 	struct regpair ustorm_st_padding[2];
6900 };
6901 
6902 /* roce cqes statistics */
6903 struct roce_cqe_stats {
6904 	__le32 req_cqe_error;
6905 	__le32 req_remote_access_errors;
6906 	__le32 req_remote_invalid_request;
6907 	__le32 resp_cqe_error;
6908 	__le32 resp_local_length_error;
6909 	__le32 reserved;
6910 };
6911 
6912 /* roce create qp requester ramrod data */
6913 struct roce_create_qp_req_ramrod_data {
6914 	__le16 flags;
6915 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_MASK			0x3
6916 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_SHIFT		0
6917 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK		0x1
6918 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT	2
6919 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_MASK		0x1
6920 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_SHIFT		3
6921 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_MASK				0x7
6922 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_SHIFT			4
6923 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_XRC_FLAG_MASK			0x1
6924 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_XRC_FLAG_SHIFT			7
6925 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK		0xF
6926 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT		8
6927 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK			0xF
6928 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT		12
6929 	u8 max_ord;
6930 	u8 traffic_class;
6931 	u8 hop_limit;
6932 	u8 orq_num_pages;
6933 	__le16 p_key;
6934 	__le32 flow_label;
6935 	__le32 dst_qp_id;
6936 	__le32 ack_timeout_val;
6937 	__le32 initial_psn;
6938 	__le16 mtu;
6939 	__le16 pd;
6940 	__le16 sq_num_pages;
6941 	__le16 low_latency_phy_queue;
6942 	struct regpair sq_pbl_addr;
6943 	struct regpair orq_pbl_addr;
6944 	__le16 local_mac_addr[3];
6945 	__le16 remote_mac_addr[3];
6946 	__le16 vlan_id;
6947 	__le16 udp_src_port;
6948 	__le32 src_gid[4];
6949 	__le32 dst_gid[4];
6950 	__le32 cq_cid;
6951 	struct regpair qp_handle_for_cqe;
6952 	struct regpair qp_handle_for_async;
6953 	u8 stats_counter_id;
6954 	u8 vf_id;
6955 	u8 vport_id;
6956 	u8 flags2;
6957 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_EDPM_MODE_MASK			0x1
6958 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_EDPM_MODE_SHIFT			0
6959 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_VF_ID_VALID_MASK			0x1
6960 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_VF_ID_VALID_SHIFT		1
6961 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FORCE_LB_MASK			0x1
6962 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FORCE_LB_SHIFT			2
6963 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_MASK			0x1F
6964 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_SHIFT			3
6965 	u8 name_space;
6966 	u8 reserved3[3];
6967 	__le16 regular_latency_phy_queue;
6968 	__le16 dpi;
6969 };
6970 
6971 /* roce create qp responder ramrod data */
6972 struct roce_create_qp_resp_ramrod_data {
6973 	__le32 flags;
6974 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_MASK		0x3
6975 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_SHIFT		0
6976 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK			0x1
6977 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT		2
6978 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK			0x1
6979 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT		3
6980 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK			0x1
6981 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT			4
6982 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_MASK			0x1
6983 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_SHIFT			5
6984 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_MASK	0x1
6985 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_SHIFT	6
6986 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_MASK		0x1
6987 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_SHIFT		7
6988 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_MASK			0x7
6989 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_SHIFT			8
6990 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK		0x1F
6991 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT		11
6992 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG_MASK             0x1
6993 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG_SHIFT            16
6994 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_VF_ID_VALID_MASK	0x1
6995 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_VF_ID_VALID_SHIFT	17
6996 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_FORCE_LB_MASK			0x1
6997 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_FORCE_LB_SHIFT			18
6998 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_MASK			0x1FFF
6999 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_SHIFT			19
7000 	__le16 xrc_domain;
7001 	u8 max_ird;
7002 	u8 traffic_class;
7003 	u8 hop_limit;
7004 	u8 irq_num_pages;
7005 	__le16 p_key;
7006 	__le32 flow_label;
7007 	__le32 dst_qp_id;
7008 	u8 stats_counter_id;
7009 	u8 reserved1;
7010 	__le16 mtu;
7011 	__le32 initial_psn;
7012 	__le16 pd;
7013 	__le16 rq_num_pages;
7014 	struct rdma_srq_id srq_id;
7015 	struct regpair rq_pbl_addr;
7016 	struct regpair irq_pbl_addr;
7017 	__le16 local_mac_addr[3];
7018 	__le16 remote_mac_addr[3];
7019 	__le16 vlan_id;
7020 	__le16 udp_src_port;
7021 	__le32 src_gid[4];
7022 	__le32 dst_gid[4];
7023 	struct regpair qp_handle_for_cqe;
7024 	struct regpair qp_handle_for_async;
7025 	__le16 low_latency_phy_queue;
7026 	u8 vf_id;
7027 	u8 vport_id;
7028 	__le32 cq_cid;
7029 	__le16 regular_latency_phy_queue;
7030 	__le16 dpi;
7031 	__le32 src_qp_id;
7032 	u8 name_space;
7033 	u8 reserved3[3];
7034 };
7035 
7036 /* RoCE Create Suspended qp requester runtime ramrod data */
7037 struct roce_create_suspended_qp_req_runtime_ramrod_data {
7038 	__le32 flags;
7039 #define ROCE_CREATE_SUSPENDED_QP_REQ_RUNTIME_RAMROD_DATA_ERR_FLG_MASK 0x1
7040 #define ROCE_CREATE_SUSPENDED_QP_REQ_RUNTIME_RAMROD_DATA_ERR_FLG_SHIFT 0
7041 #define ROCE_CREATE_SUSPENDED_QP_REQ_RUNTIME_RAMROD_DATA_RESERVED0_MASK \
7042 								 0x7FFFFFFF
7043 #define ROCE_CREATE_SUSPENDED_QP_REQ_RUNTIME_RAMROD_DATA_RESERVED0_SHIFT 1
7044 	__le32 send_msg_psn;
7045 	__le32 inflight_sends;
7046 	__le32 ssn;
7047 };
7048 
7049 /* RoCE Create Suspended QP requester ramrod data */
7050 struct roce_create_suspended_qp_req_ramrod_data {
7051 	struct roce_create_qp_req_ramrod_data qp_params;
7052 	struct roce_create_suspended_qp_req_runtime_ramrod_data
7053 	 qp_runtime_params;
7054 };
7055 
7056 /* RoCE Create Suspended QP responder runtime params */
7057 struct roce_create_suspended_qp_resp_runtime_params {
7058 	__le32 flags;
7059 #define ROCE_CREATE_SUSPENDED_QP_RESP_RUNTIME_PARAMS_ERR_FLG_MASK 0x1
7060 #define ROCE_CREATE_SUSPENDED_QP_RESP_RUNTIME_PARAMS_ERR_FLG_SHIFT 0
7061 #define ROCE_CREATE_SUSPENDED_QP_RESP_RUNTIME_PARAMS_RDMA_ACTIVE_MASK 0x1
7062 #define ROCE_CREATE_SUSPENDED_QP_RESP_RUNTIME_PARAMS_RDMA_ACTIVE_SHIFT 1
7063 #define ROCE_CREATE_SUSPENDED_QP_RESP_RUNTIME_PARAMS_RESERVED0_MASK 0x3FFFFFFF
7064 #define ROCE_CREATE_SUSPENDED_QP_RESP_RUNTIME_PARAMS_RESERVED0_SHIFT 2
7065 	__le32 receive_msg_psn;
7066 	__le32 inflight_receives;
7067 	__le32 rmsn;
7068 	__le32 rdma_key;
7069 	struct regpair rdma_va;
7070 	__le32 rdma_length;
7071 	__le32 num_rdb_entries;
7072 	__le32 resreved;
7073 };
7074 
7075 /* RoCE RDB array entry */
7076 struct roce_resp_qp_rdb_entry {
7077 	struct regpair atomic_data;
7078 	struct regpair va;
7079 	__le32 psn;
7080 	__le32 rkey;
7081 	__le32 byte_count;
7082 	u8 op_type;
7083 	u8 reserved[3];
7084 };
7085 
7086 /* RoCE Create Suspended QP responder runtime ramrod data */
7087 struct roce_create_suspended_qp_resp_runtime_ramrod_data {
7088 	struct roce_create_suspended_qp_resp_runtime_params params;
7089 	struct roce_resp_qp_rdb_entry
7090 	 rdb_array_entries[RDMA_MAX_IRQ_ELEMS_IN_PAGE];
7091 };
7092 
7093 /* RoCE Create Suspended QP responder ramrod data */
7094 struct roce_create_suspended_qp_resp_ramrod_data {
7095 	struct roce_create_qp_resp_ramrod_data
7096 	 qp_params;
7097 	struct roce_create_suspended_qp_resp_runtime_ramrod_data
7098 	 qp_runtime_params;
7099 };
7100 
7101 /* RoCE create ud qp ramrod data */
7102 struct roce_create_ud_qp_ramrod_data {
7103 	__le16 local_mac_addr[3];
7104 	__le16 vlan_id;
7105 	__le32 src_qp_id;
7106 	u8 name_space;
7107 	u8 reserved[3];
7108 };
7109 
7110 /* roce DCQCN received statistics */
7111 struct roce_dcqcn_received_stats {
7112 	struct regpair ecn_pkt_rcv;
7113 	struct regpair cnp_pkt_rcv;
7114 	struct regpair cnp_pkt_reject;
7115 };
7116 
7117 /* roce DCQCN sent statistics */
7118 struct roce_dcqcn_sent_stats {
7119 	struct regpair cnp_pkt_sent;
7120 };
7121 
7122 /* RoCE destroy qp requester output params */
7123 struct roce_destroy_qp_req_output_params {
7124 	__le32 cq_prod;
7125 	__le32 reserved;
7126 };
7127 
7128 /* RoCE destroy qp requester ramrod data */
7129 struct roce_destroy_qp_req_ramrod_data {
7130 	struct regpair output_params_addr;
7131 };
7132 
7133 /* RoCE destroy qp responder output params */
7134 struct roce_destroy_qp_resp_output_params {
7135 	__le32 cq_prod;
7136 	__le32 reserved;
7137 };
7138 
7139 /* RoCE destroy qp responder ramrod data */
7140 struct roce_destroy_qp_resp_ramrod_data {
7141 	struct regpair output_params_addr;
7142 	__le32 src_qp_id;
7143 	__le32 reserved;
7144 };
7145 
7146 /* RoCE destroy ud qp ramrod data */
7147 struct roce_destroy_ud_qp_ramrod_data {
7148 	__le32 src_qp_id;
7149 	__le32 reserved;
7150 };
7151 
7152 /* roce error statistics */
7153 struct roce_error_stats {
7154 	__le32 resp_remote_access_errors;
7155 	__le32 reserved;
7156 };
7157 
7158 /* roce special events statistics */
7159 struct roce_events_stats {
7160 	__le32 silent_drops;
7161 	__le32 rnr_naks_sent;
7162 	__le32 retransmit_count;
7163 	__le32 icrc_error_count;
7164 	__le32 implied_nak_seq_err;
7165 	__le32 duplicate_request;
7166 	__le32 local_ack_timeout_err;
7167 	__le32 out_of_sequence;
7168 	__le32 packet_seq_err;
7169 	__le32 rnr_nak_retry_err;
7170 };
7171 
7172 /* roce slow path EQ cmd IDs */
7173 enum roce_event_opcode {
7174 	ROCE_EVENT_CREATE_QP = 13,
7175 	ROCE_EVENT_MODIFY_QP,
7176 	ROCE_EVENT_QUERY_QP,
7177 	ROCE_EVENT_DESTROY_QP,
7178 	ROCE_EVENT_CREATE_UD_QP,
7179 	ROCE_EVENT_DESTROY_UD_QP,
7180 	ROCE_EVENT_FUNC_UPDATE,
7181 	ROCE_EVENT_SUSPEND_QP,
7182 	ROCE_EVENT_QUERY_SUSPENDED_QP,
7183 	ROCE_EVENT_CREATE_SUSPENDED_QP,
7184 	ROCE_EVENT_RESUME_QP,
7185 	ROCE_EVENT_SUSPEND_UD_QP,
7186 	ROCE_EVENT_RESUME_UD_QP,
7187 	ROCE_EVENT_CREATE_SUSPENDED_UD_QP,
7188 	ROCE_EVENT_FLUSH_DPT_QP,
7189 	MAX_ROCE_EVENT_OPCODE
7190 };
7191 
7192 /* roce func init ramrod data */
7193 struct roce_init_func_params {
7194 	u8 ll2_queue_id;
7195 	u8 cnp_vlan_priority;
7196 	u8 cnp_dscp;
7197 	u8 flags;
7198 #define ROCE_INIT_FUNC_PARAMS_DCQCN_NP_EN_MASK		0x1
7199 #define ROCE_INIT_FUNC_PARAMS_DCQCN_NP_EN_SHIFT		0
7200 #define ROCE_INIT_FUNC_PARAMS_DCQCN_RP_EN_MASK		0x1
7201 #define ROCE_INIT_FUNC_PARAMS_DCQCN_RP_EN_SHIFT		1
7202 #define ROCE_INIT_FUNC_PARAMS_RESERVED0_MASK		0x3F
7203 #define ROCE_INIT_FUNC_PARAMS_RESERVED0_SHIFT		2
7204 	__le32 cnp_send_timeout;
7205 	__le16 rl_offset;
7206 	u8 rl_count_log;
7207 	u8 reserved1[5];
7208 };
7209 
7210 /* roce func init ramrod data */
7211 struct roce_init_func_ramrod_data {
7212 	struct rdma_init_func_ramrod_data rdma;
7213 	struct roce_init_func_params roce;
7214 };
7215 
7216 /* roce_ll2_cqe_data */
7217 struct roce_ll2_cqe_data {
7218 	u8 name_space;
7219 	u8 flags;
7220 #define ROCE_LL2_CQE_DATA_QP_SUSPENDED_MASK	0x1
7221 #define ROCE_LL2_CQE_DATA_QP_SUSPENDED_SHIFT	0
7222 #define ROCE_LL2_CQE_DATA_RESERVED0_MASK	0x7F
7223 #define ROCE_LL2_CQE_DATA_RESERVED0_SHIFT	1
7224 	u8 reserved1[2];
7225 	__le32 cid;
7226 };
7227 
7228 /* roce modify qp requester ramrod data */
7229 struct roce_modify_qp_req_ramrod_data {
7230 	__le16 flags;
7231 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK		0x1
7232 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT		0
7233 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_MASK		0x1
7234 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_SHIFT		1
7235 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_MASK		0x1
7236 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_SHIFT	2
7237 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_MASK			0x1
7238 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_SHIFT			3
7239 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK		0x1
7240 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT		4
7241 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_MASK			0x1
7242 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_SHIFT		5
7243 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_MASK		0x1
7244 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_SHIFT		6
7245 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_MASK		0x1
7246 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_SHIFT		7
7247 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_MASK		0x1
7248 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_SHIFT		8
7249 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_MASK			0x1
7250 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_SHIFT			9
7251 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_MASK				0x7
7252 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_SHIFT			10
7253 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK		0x1
7254 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUE_FLG_SHIFT		13
7255 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_FORCE_LB_MASK			0x1
7256 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_FORCE_LB_SHIFT			14
7257 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_MASK			0x1
7258 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_SHIFT			15
7259 	u8 fields;
7260 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK	0xF
7261 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT	0
7262 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK		0xF
7263 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT	4
7264 	u8 max_ord;
7265 	u8 traffic_class;
7266 	u8 hop_limit;
7267 	__le16 p_key;
7268 	__le32 flow_label;
7269 	__le32 ack_timeout_val;
7270 	__le16 mtu;
7271 	__le16 reserved2;
7272 	__le32 reserved3[2];
7273 	__le16 low_latency_phy_queue;
7274 	__le16 regular_latency_phy_queue;
7275 	__le32 src_gid[4];
7276 	__le32 dst_gid[4];
7277 };
7278 
7279 /* roce modify qp responder ramrod data */
7280 struct roce_modify_qp_resp_ramrod_data {
7281 	__le16 flags;
7282 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK		0x1
7283 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT		0
7284 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK			0x1
7285 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT		1
7286 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK			0x1
7287 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT		2
7288 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK			0x1
7289 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT			3
7290 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_MASK			0x1
7291 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_SHIFT			4
7292 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK		0x1
7293 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT	5
7294 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_MASK		0x1
7295 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_SHIFT		6
7296 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_MASK			0x1
7297 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_SHIFT			7
7298 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_MASK	0x1
7299 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_SHIFT	8
7300 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK		0x1
7301 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT		9
7302 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK		0x1
7303 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_SHIFT	10
7304 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_FORCE_LB_MASK			0x1
7305 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_FORCE_LB_SHIFT			11
7306 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_MASK			0xF
7307 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_SHIFT			12
7308 	u8 fields;
7309 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_MASK		0x7
7310 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_SHIFT		0
7311 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK	0x1F
7312 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT	3
7313 	u8 max_ird;
7314 	u8 traffic_class;
7315 	u8 hop_limit;
7316 	__le16 p_key;
7317 	__le32 flow_label;
7318 	__le16 mtu;
7319 	__le16 low_latency_phy_queue;
7320 	__le16 regular_latency_phy_queue;
7321 	u8 reserved2[6];
7322 	__le32 src_gid[4];
7323 	__le32 dst_gid[4];
7324 };
7325 
7326 /* RoCE query qp requester output params */
7327 struct roce_query_qp_req_output_params {
7328 	__le32 psn;
7329 	__le32 flags;
7330 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_MASK		0x1
7331 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_SHIFT		0
7332 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_MASK	0x1
7333 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_SHIFT	1
7334 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_MASK		0x3FFFFFFF
7335 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_SHIFT		2
7336 };
7337 
7338 /* RoCE query qp requester ramrod data */
7339 struct roce_query_qp_req_ramrod_data {
7340 	struct regpair output_params_addr;
7341 };
7342 
7343 /* RoCE query qp responder output params */
7344 struct roce_query_qp_resp_output_params {
7345 	__le32 psn;
7346 	__le32 flags;
7347 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_MASK  0x1
7348 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0
7349 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_MASK  0x7FFFFFFF
7350 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_SHIFT 1
7351 };
7352 
7353 /* RoCE query qp responder ramrod data */
7354 struct roce_query_qp_resp_ramrod_data {
7355 	struct regpair output_params_addr;
7356 };
7357 
7358 /* RoCE Query Suspended QP requester output params */
7359 struct roce_query_suspended_qp_req_output_params {
7360 	__le32 psn;
7361 	__le32 flags;
7362 #define ROCE_QUERY_SUSPENDED_QP_REQ_OUTPUT_PARAMS_ERR_FLG_MASK		0x1
7363 #define ROCE_QUERY_SUSPENDED_QP_REQ_OUTPUT_PARAMS_ERR_FLG_SHIFT		0
7364 #define ROCE_QUERY_SUSPENDED_QP_REQ_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF
7365 #define ROCE_QUERY_SUSPENDED_QP_REQ_OUTPUT_PARAMS_RESERVED0_SHIFT	1
7366 	__le32 send_msg_psn;
7367 	__le32 inflight_sends;
7368 	__le32 ssn;
7369 	__le32 reserved;
7370 };
7371 
7372 /* RoCE Query Suspended QP requester ramrod data */
7373 struct roce_query_suspended_qp_req_ramrod_data {
7374 	struct regpair output_params_addr;
7375 };
7376 
7377 /* RoCE Query Suspended QP responder runtime params */
7378 struct roce_query_suspended_qp_resp_runtime_params {
7379 	__le32 psn;
7380 	__le32 flags;
7381 #define ROCE_QUERY_SUSPENDED_QP_RESP_RUNTIME_PARAMS_ERR_FLG_MASK 0x1
7382 #define ROCE_QUERY_SUSPENDED_QP_RESP_RUNTIME_PARAMS_ERR_FLG_SHIFT 0
7383 #define ROCE_QUERY_SUSPENDED_QP_RESP_RUNTIME_PARAMS_RDMA_ACTIVE_MASK 0x1
7384 #define ROCE_QUERY_SUSPENDED_QP_RESP_RUNTIME_PARAMS_RDMA_ACTIVE_SHIFT 1
7385 #define ROCE_QUERY_SUSPENDED_QP_RESP_RUNTIME_PARAMS_RESERVED0_MASK 0x3FFFFFFF
7386 #define ROCE_QUERY_SUSPENDED_QP_RESP_RUNTIME_PARAMS_RESERVED0_SHIFT 2
7387 	__le32 receive_msg_psn;
7388 	__le32 inflight_receives;
7389 	__le32 rmsn;
7390 	__le32 rdma_key;
7391 	struct regpair rdma_va;
7392 	__le32 rdma_length;
7393 	__le32 num_rdb_entries;
7394 };
7395 
7396 /* RoCE Query Suspended QP responder output params */
7397 struct roce_query_suspended_qp_resp_output_params {
7398 	struct roce_query_suspended_qp_resp_runtime_params runtime_params;
7399 	struct roce_resp_qp_rdb_entry
7400 	 rdb_array_entries[RDMA_MAX_IRQ_ELEMS_IN_PAGE];
7401 };
7402 
7403 /* RoCE Query Suspended QP responder ramrod data */
7404 struct roce_query_suspended_qp_resp_ramrod_data {
7405 	struct regpair output_params_addr;
7406 };
7407 
7408 /* ROCE ramrod command IDs */
7409 enum roce_ramrod_cmd_id {
7410 	ROCE_RAMROD_CREATE_QP = 13,
7411 	ROCE_RAMROD_MODIFY_QP,
7412 	ROCE_RAMROD_QUERY_QP,
7413 	ROCE_RAMROD_DESTROY_QP,
7414 	ROCE_RAMROD_CREATE_UD_QP,
7415 	ROCE_RAMROD_DESTROY_UD_QP,
7416 	ROCE_RAMROD_FUNC_UPDATE,
7417 	ROCE_RAMROD_SUSPEND_QP,
7418 	ROCE_RAMROD_QUERY_SUSPENDED_QP,
7419 	ROCE_RAMROD_CREATE_SUSPENDED_QP,
7420 	ROCE_RAMROD_RESUME_QP,
7421 	ROCE_RAMROD_SUSPEND_UD_QP,
7422 	ROCE_RAMROD_RESUME_UD_QP,
7423 	ROCE_RAMROD_CREATE_SUSPENDED_UD_QP,
7424 	ROCE_RAMROD_FLUSH_DPT_QP,
7425 	MAX_ROCE_RAMROD_CMD_ID
7426 };
7427 
7428 /* ROCE RDB array entry type */
7429 enum roce_resp_qp_rdb_entry_type {
7430 	ROCE_QP_RDB_ENTRY_RDMA_RESPONSE = 0,
7431 	ROCE_QP_RDB_ENTRY_ATOMIC_RESPONSE = 1,
7432 	ROCE_QP_RDB_ENTRY_INVALID = 2,
7433 	MAX_ROCE_RESP_QP_RDB_ENTRY_TYPE
7434 };
7435 
7436 /* RoCE func init ramrod data */
7437 struct roce_update_func_params {
7438 	u8 cnp_vlan_priority;
7439 	u8 cnp_dscp;
7440 	__le16 flags;
7441 #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_NP_EN_MASK	0x1
7442 #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_NP_EN_SHIFT	0
7443 #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_RP_EN_MASK	0x1
7444 #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_RP_EN_SHIFT	1
7445 #define ROCE_UPDATE_FUNC_PARAMS_RESERVED0_MASK		0x3FFF
7446 #define ROCE_UPDATE_FUNC_PARAMS_RESERVED0_SHIFT		2
7447 	__le32 cnp_send_timeout;
7448 };
7449 
7450 struct xstorm_roce_conn_ag_ctx_dq_ext_ld_part {
7451 	u8 reserved0;
7452 	u8 state;
7453 	u8 flags0;
7454 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK	0x1
7455 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT	0
7456 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_MASK		0x1
7457 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_SHIFT		1
7458 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_MASK		0x1
7459 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_SHIFT		2
7460 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK	0x1
7461 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT	3
7462 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_MASK		0x1
7463 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_SHIFT		4
7464 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_MASK		0x1
7465 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_SHIFT		5
7466 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_MASK		0x1
7467 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_SHIFT		6
7468 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_MASK		0x1
7469 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_SHIFT		7
7470 	u8 flags1;
7471 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_MASK		0x1
7472 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_SHIFT		0
7473 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_MASK		0x1
7474 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_SHIFT		1
7475 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK		0x1
7476 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT		2
7477 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK		0x1
7478 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT		3
7479 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSDM_FLUSH_MASK	0x1
7480 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSDM_FLUSH_SHIFT	4
7481 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSEM_FLUSH_MASK	0x1
7482 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSEM_FLUSH_SHIFT	5
7483 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_MASK		0x1
7484 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_SHIFT		6
7485 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK	0x1
7486 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT	7
7487 	u8 flags2;
7488 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK	0x3
7489 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT	0
7490 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK	0x3
7491 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_SHIFT	2
7492 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK	0x3
7493 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_SHIFT	4
7494 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK	0x3
7495 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_SHIFT	6
7496 	u8 flags3;
7497 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_MASK		0x3
7498 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_SHIFT		0
7499 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_MASK		0x3
7500 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_SHIFT		2
7501 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_MASK		0x3
7502 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_SHIFT		4
7503 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK	0x3
7504 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_SHIFT	6
7505 	u8 flags4;
7506 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK	0x3
7507 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT	0
7508 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK	0x3
7509 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_SHIFT	2
7510 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK	0x3
7511 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_SHIFT	4
7512 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK	0x3
7513 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_SHIFT	6
7514 	u8 flags5;
7515 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK	0x3
7516 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT	0
7517 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK	0x3
7518 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_SHIFT	2
7519 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_MASK	0x3
7520 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_SHIFT	4
7521 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK	0x3
7522 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_SHIFT	6
7523 	u8 flags6;
7524 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK	0x3
7525 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT	0
7526 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK	0x3
7527 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_SHIFT	2
7528 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK	0x3
7529 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_SHIFT	4
7530 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK	0x3
7531 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_SHIFT	6
7532 	u8 flags7;
7533 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK		0x3
7534 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT		0
7535 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK		0x3
7536 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_SHIFT		2
7537 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK		0x3
7538 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT	4
7539 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK		0x1
7540 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_SHIFT		6
7541 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK		0x1
7542 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_SHIFT		7
7543 	u8 flags8;
7544 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK		0x1
7545 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT		0
7546 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK		0x1
7547 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_SHIFT		1
7548 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_MASK		0x1
7549 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_SHIFT		2
7550 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_MASK		0x1
7551 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_SHIFT		3
7552 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_MASK		0x1
7553 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_SHIFT		4
7554 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK	0x1
7555 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_SHIFT	5
7556 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK		0x1
7557 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_SHIFT		6
7558 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK		0x1
7559 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_SHIFT		7
7560 	u8 flags9;
7561 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK	0x1
7562 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT	0
7563 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK	0x1
7564 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_SHIFT	1
7565 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK	0x1
7566 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_SHIFT	2
7567 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK	0x1
7568 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_SHIFT	3
7569 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_MASK	0x1
7570 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_SHIFT	4
7571 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK	0x1
7572 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_SHIFT	5
7573 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK	0x1
7574 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_SHIFT	6
7575 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK	0x1
7576 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_SHIFT	7
7577 	u8 flags10;
7578 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK		0x1
7579 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT		0
7580 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK		0x1
7581 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_SHIFT		1
7582 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK		0x1
7583 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_SHIFT		2
7584 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK		0x1
7585 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_SHIFT		3
7586 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK	0x1
7587 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT	4
7588 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK		0x1
7589 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_SHIFT		5
7590 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK		0x1
7591 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_SHIFT		6
7592 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK		0x1
7593 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_SHIFT		7
7594 	u8 flags11;
7595 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK		0x1
7596 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT		0
7597 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK		0x1
7598 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_SHIFT		1
7599 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK		0x1
7600 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_SHIFT		2
7601 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK		0x1
7602 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_SHIFT		3
7603 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK		0x1
7604 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_SHIFT		4
7605 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_MASK		0x1
7606 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_SHIFT		5
7607 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK	0x1
7608 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT	6
7609 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK		0x1
7610 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_SHIFT		7
7611 	u8 flags12;
7612 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_MASK		0x1
7613 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_SHIFT		0
7614 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK		0x1
7615 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_SHIFT		1
7616 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK	0x1
7617 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT	2
7618 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK	0x1
7619 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT	3
7620 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_MASK		0x1
7621 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_SHIFT		4
7622 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK		0x1
7623 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_SHIFT		5
7624 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_MASK		0x1
7625 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_SHIFT		6
7626 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_MASK		0x1
7627 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_SHIFT		7
7628 	u8 flags13;
7629 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK		0x1
7630 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT		0
7631 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK		0x1
7632 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_SHIFT		1
7633 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK	0x1
7634 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT	2
7635 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK	0x1
7636 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT	3
7637 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK	0x1
7638 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT	4
7639 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK	0x1
7640 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT	5
7641 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK	0x1
7642 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT	6
7643 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK	0x1
7644 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT	7
7645 	u8 flags14;
7646 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_MASK		0x1
7647 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_SHIFT	0
7648 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK		0x1
7649 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_SHIFT		1
7650 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK	0x3
7651 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_SHIFT	2
7652 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK		0x1
7653 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_SHIFT		4
7654 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK	0x1
7655 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT	5
7656 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK		0x3
7657 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_SHIFT		6
7658 	u8 byte2;
7659 	__le16 physical_q0;
7660 	__le16 word1;
7661 	__le16 word2;
7662 	__le16 word3;
7663 	__le16 word4;
7664 	__le16 word5;
7665 	__le16 conn_dpi;
7666 	u8 byte3;
7667 	u8 byte4;
7668 	u8 byte5;
7669 	u8 byte6;
7670 	__le32 reg0;
7671 	__le32 reg1;
7672 	__le32 reg2;
7673 	__le32 snd_nxt_psn;
7674 	__le32 reg4;
7675 };
7676 
7677 struct mstorm_roce_conn_ag_ctx {
7678 	u8 byte0;
7679 	u8 byte1;
7680 	u8 flags0;
7681 #define MSTORM_ROCE_CONN_AG_CTX_BIT0_MASK     0x1
7682 #define MSTORM_ROCE_CONN_AG_CTX_BIT0_SHIFT    0
7683 #define MSTORM_ROCE_CONN_AG_CTX_BIT1_MASK     0x1
7684 #define MSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT    1
7685 #define MSTORM_ROCE_CONN_AG_CTX_CF0_MASK      0x3
7686 #define MSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT     2
7687 #define MSTORM_ROCE_CONN_AG_CTX_CF1_MASK      0x3
7688 #define MSTORM_ROCE_CONN_AG_CTX_CF1_SHIFT     4
7689 #define MSTORM_ROCE_CONN_AG_CTX_CF2_MASK      0x3
7690 #define MSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT     6
7691 	u8 flags1;
7692 #define MSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK    0x1
7693 #define MSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT   0
7694 #define MSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK    0x1
7695 #define MSTORM_ROCE_CONN_AG_CTX_CF1EN_SHIFT   1
7696 #define MSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK    0x1
7697 #define MSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT   2
7698 #define MSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK  0x1
7699 #define MSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT 3
7700 #define MSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK  0x1
7701 #define MSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 4
7702 #define MSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK  0x1
7703 #define MSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 5
7704 #define MSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK  0x1
7705 #define MSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 6
7706 #define MSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK  0x1
7707 #define MSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 7
7708 	__le16 word0;
7709 	__le16 word1;
7710 	__le32 reg0;
7711 	__le32 reg1;
7712 };
7713 
7714 struct mstorm_roce_req_conn_ag_ctx {
7715 	u8 byte0;
7716 	u8 byte1;
7717 	u8 flags0;
7718 #define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK	0x1
7719 #define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT	0
7720 #define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK	0x1
7721 #define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT	1
7722 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK		0x3
7723 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT	2
7724 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK		0x3
7725 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT	4
7726 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK		0x3
7727 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT	6
7728 	u8 flags1;
7729 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK	0x1
7730 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT	0
7731 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK	0x1
7732 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT	1
7733 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK	0x1
7734 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT	2
7735 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK	0x1
7736 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT	3
7737 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK	0x1
7738 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT	4
7739 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK	0x1
7740 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT	5
7741 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK	0x1
7742 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT	6
7743 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK	0x1
7744 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT	7
7745 	__le16 word0;
7746 	__le16 word1;
7747 	__le32 reg0;
7748 	__le32 reg1;
7749 };
7750 
7751 struct mstorm_roce_resp_conn_ag_ctx {
7752 	u8 byte0;
7753 	u8 byte1;
7754 	u8 flags0;
7755 #define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK	0x1
7756 #define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT	0
7757 #define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK	0x1
7758 #define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT	1
7759 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK	0x3
7760 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT	2
7761 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK	0x3
7762 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT	4
7763 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK	0x3
7764 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT	6
7765 	u8 flags1;
7766 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK	0x1
7767 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT	0
7768 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK	0x1
7769 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT	1
7770 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK	0x1
7771 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT	2
7772 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK	0x1
7773 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT	3
7774 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK	0x1
7775 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT	4
7776 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK	0x1
7777 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT	5
7778 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK	0x1
7779 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT	6
7780 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK	0x1
7781 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT	7
7782 	__le16 word0;
7783 	__le16 word1;
7784 	__le32 reg0;
7785 	__le32 reg1;
7786 };
7787 
7788 struct tstorm_roce_req_conn_ag_ctx {
7789 	u8 reserved0;
7790 	u8 state;
7791 	u8 flags0;
7792 #define TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK		0x1
7793 #define TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT		0
7794 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURRED_MASK		0x1
7795 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURRED_SHIFT		1
7796 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURRED_MASK	0x1
7797 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURRED_SHIFT	2
7798 #define TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_MASK			0x1
7799 #define TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_SHIFT			3
7800 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_MASK		0x1
7801 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_SHIFT		4
7802 #define TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_MASK			0x1
7803 #define TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_SHIFT			5
7804 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK			0x3
7805 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_SHIFT			6
7806 	u8 flags1;
7807 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK             0x3
7808 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT            0
7809 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK			0x3
7810 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_SHIFT		2
7811 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK		0x3
7812 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT		4
7813 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK			0x3
7814 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT		6
7815 	u8 flags2;
7816 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_MASK               0x3
7817 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_SHIFT              0
7818 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK	0x3
7819 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_SHIFT	2
7820 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK	0x3
7821 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_SHIFT	4
7822 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK	0x3
7823 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_SHIFT	6
7824 	u8 flags3;
7825 #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK	0x3
7826 #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_SHIFT	0
7827 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK	0x3
7828 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_SHIFT	2
7829 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK			0x1
7830 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_SHIFT		4
7831 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK          0x1
7832 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT         5
7833 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK		0x1
7834 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_SHIFT		6
7835 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK	0x1
7836 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT	7
7837 	u8 flags4;
7838 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK		0x1
7839 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT		0
7840 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_EN_MASK            0x1
7841 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_EN_SHIFT           1
7842 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK		0x1
7843 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_SHIFT		2
7844 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK	0x1
7845 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_SHIFT	3
7846 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_MASK		0x1
7847 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_SHIFT		4
7848 #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_MASK	0x1
7849 #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_SHIFT	5
7850 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_MASK	0x1
7851 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_SHIFT	6
7852 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK			0x1
7853 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT			7
7854 	u8 flags5;
7855 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK		0x1
7856 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT		0
7857 #define TSTORM_ROCE_REQ_CONN_AG_CTX_DIF_CNT_EN_MASK		0x1
7858 #define TSTORM_ROCE_REQ_CONN_AG_CTX_DIF_CNT_EN_SHIFT		1
7859 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK		0x1
7860 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT		2
7861 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK		0x1
7862 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT		3
7863 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK		0x1
7864 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT		4
7865 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_MASK	0x1
7866 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_SHIFT	5
7867 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK		0x1
7868 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT		6
7869 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK		0x1
7870 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT		7
7871 	__le32 dif_rxmit_cnt;
7872 	__le32 snd_nxt_psn;
7873 	__le32 snd_max_psn;
7874 	__le32 orq_prod;
7875 	__le32 reg4;
7876 	__le32 dif_acked_cnt;
7877 	__le32 dif_cnt;
7878 	__le32 reg7;
7879 	__le32 reg8;
7880 	u8 tx_cqe_error_type;
7881 	u8 orq_cache_idx;
7882 	__le16 snd_sq_cons_th;
7883 	u8 byte4;
7884 	u8 byte5;
7885 	__le16 snd_sq_cons;
7886 	__le16 conn_dpi;
7887 	__le16 force_comp_cons;
7888 	__le32 dif_rxmit_acked_cnt;
7889 	__le32 reg10;
7890 };
7891 
7892 struct tstorm_roce_resp_conn_ag_ctx {
7893 	u8 byte0;
7894 	u8 state;
7895 	u8 flags0;
7896 #define TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK		0x1
7897 #define TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT		0
7898 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_MASK	0x1
7899 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_SHIFT	1
7900 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_MASK			0x1
7901 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_SHIFT			2
7902 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_MASK			0x1
7903 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_SHIFT			3
7904 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_MASK		0x1
7905 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT		4
7906 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_MASK			0x1
7907 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_SHIFT			5
7908 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK			0x3
7909 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT			6
7910 	u8 flags1;
7911 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK            0x3
7912 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT           0
7913 #define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK	0x3
7914 #define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_SHIFT	2
7915 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK		0x3
7916 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT		4
7917 #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK	0x3
7918 #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT	6
7919 	u8 flags2;
7920 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK                0x3
7921 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT               0
7922 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK		0x3
7923 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT		2
7924 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK		0x3
7925 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_SHIFT		4
7926 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK		0x3
7927 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT		6
7928 	u8 flags3;
7929 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK		0x3
7930 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT		0
7931 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK		0x3
7932 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT		2
7933 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK		0x1
7934 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT		4
7935 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK         0x1
7936 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT        5
7937 #define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_MASK	0x1
7938 #define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_SHIFT	6
7939 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK		0x1
7940 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT		7
7941 	u8 flags4;
7942 #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK		0x1
7943 #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT		0
7944 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK             0x1
7945 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT            1
7946 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK			0x1
7947 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT			2
7948 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_MASK			0x1
7949 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_SHIFT			3
7950 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK			0x1
7951 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT			4
7952 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK			0x1
7953 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT			5
7954 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK			0x1
7955 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT			6
7956 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK			0x1
7957 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT			7
7958 	u8 flags5;
7959 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK		0x1
7960 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT		0
7961 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK		0x1
7962 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT		1
7963 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK		0x1
7964 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT		2
7965 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK		0x1
7966 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT		3
7967 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK		0x1
7968 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT		4
7969 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_MASK		0x1
7970 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_SHIFT	5
7971 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK		0x1
7972 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT		6
7973 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK		0x1
7974 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT		7
7975 	__le32 psn_and_rxmit_id_echo;
7976 	__le32 reg1;
7977 	__le32 reg2;
7978 	__le32 reg3;
7979 	__le32 reg4;
7980 	__le32 reg5;
7981 	__le32 reg6;
7982 	__le32 reg7;
7983 	__le32 reg8;
7984 	u8 tx_async_error_type;
7985 	u8 byte3;
7986 	__le16 rq_cons;
7987 	u8 byte4;
7988 	u8 byte5;
7989 	__le16 rq_prod;
7990 	__le16 conn_dpi;
7991 	__le16 irq_cons;
7992 	__le32 reg9;
7993 	__le32 reg10;
7994 };
7995 
7996 struct ustorm_roce_req_conn_ag_ctx {
7997 	u8 byte0;
7998 	u8 byte1;
7999 	u8 flags0;
8000 #define USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK	0x1
8001 #define USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT	0
8002 #define USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK	0x1
8003 #define USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT	1
8004 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK		0x3
8005 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT	2
8006 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK		0x3
8007 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT	4
8008 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK		0x3
8009 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT	6
8010 	u8 flags1;
8011 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK		0x3
8012 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT	0
8013 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF4_MASK		0x3
8014 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF4_SHIFT	2
8015 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF5_MASK		0x3
8016 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF5_SHIFT	4
8017 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF6_MASK		0x3
8018 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF6_SHIFT	6
8019 	u8 flags2;
8020 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK	0x1
8021 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT	0
8022 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK	0x1
8023 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT	1
8024 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK	0x1
8025 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT	2
8026 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK	0x1
8027 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT	3
8028 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_MASK	0x1
8029 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_SHIFT	4
8030 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_MASK	0x1
8031 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_SHIFT	5
8032 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_MASK	0x1
8033 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_SHIFT	6
8034 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK	0x1
8035 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT	7
8036 	u8 flags3;
8037 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK	0x1
8038 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT	0
8039 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK	0x1
8040 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT	1
8041 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK	0x1
8042 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT	2
8043 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK	0x1
8044 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT	3
8045 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK	0x1
8046 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT	4
8047 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK	0x1
8048 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT	5
8049 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK	0x1
8050 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT	6
8051 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK	0x1
8052 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT	7
8053 	u8 byte2;
8054 	u8 byte3;
8055 	__le16 word0;
8056 	__le16 word1;
8057 	__le32 reg0;
8058 	__le32 reg1;
8059 	__le32 reg2;
8060 	__le32 reg3;
8061 	__le16 word2;
8062 	__le16 word3;
8063 };
8064 
8065 struct ustorm_roce_resp_conn_ag_ctx {
8066 	u8 byte0;
8067 	u8 byte1;
8068 	u8 flags0;
8069 #define USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK	0x1
8070 #define USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT	0
8071 #define USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK	0x1
8072 #define USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT	1
8073 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK	0x3
8074 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT	2
8075 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK	0x3
8076 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT	4
8077 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK	0x3
8078 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT	6
8079 	u8 flags1;
8080 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK	0x3
8081 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT	0
8082 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF4_MASK	0x3
8083 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF4_SHIFT	2
8084 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF5_MASK	0x3
8085 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF5_SHIFT	4
8086 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK	0x3
8087 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT	6
8088 	u8 flags2;
8089 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK	0x1
8090 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT	0
8091 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK	0x1
8092 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT	1
8093 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK	0x1
8094 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT	2
8095 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK	0x1
8096 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT	3
8097 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_MASK	0x1
8098 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_SHIFT	4
8099 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_MASK	0x1
8100 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_SHIFT	5
8101 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK	0x1
8102 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT	6
8103 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK	0x1
8104 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT	7
8105 	u8 flags3;
8106 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK	0x1
8107 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT	0
8108 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK	0x1
8109 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT	1
8110 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK	0x1
8111 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT	2
8112 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK	0x1
8113 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT	3
8114 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK	0x1
8115 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT	4
8116 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK	0x1
8117 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT	5
8118 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK	0x1
8119 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT	6
8120 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK	0x1
8121 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT	7
8122 	u8 byte2;
8123 	u8 byte3;
8124 	__le16 word0;
8125 	__le16 word1;
8126 	__le32 reg0;
8127 	__le32 reg1;
8128 	__le32 reg2;
8129 	__le32 reg3;
8130 	__le16 word2;
8131 	__le16 word3;
8132 };
8133 
8134 struct xstorm_roce_req_conn_ag_ctx {
8135 	u8 reserved0;
8136 	u8 state;
8137 	u8 flags0;
8138 #define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
8139 #define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
8140 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_MASK		0x1
8141 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_SHIFT		1
8142 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_MASK		0x1
8143 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_SHIFT		2
8144 #define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_MASK	0x1
8145 #define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_SHIFT	3
8146 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_MASK		0x1
8147 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_SHIFT		4
8148 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_MASK		0x1
8149 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_SHIFT		5
8150 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_MASK		0x1
8151 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_SHIFT		6
8152 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_MASK		0x1
8153 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_SHIFT		7
8154 	u8 flags1;
8155 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_MASK		0x1
8156 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_SHIFT		0
8157 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_MASK		0x1
8158 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_SHIFT		1
8159 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_MASK		0x1
8160 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_SHIFT		2
8161 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK		0x1
8162 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_SHIFT		3
8163 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MSDM_FLUSH_MASK		0x1
8164 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MSDM_FLUSH_SHIFT		4
8165 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MSEM_FLUSH_MASK		0x1
8166 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MSEM_FLUSH_SHIFT		5
8167 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK		0x1
8168 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_SHIFT	6
8169 #define XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK	0x1
8170 #define XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_SHIFT	7
8171 	u8 flags2;
8172 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK		0x3
8173 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT	0
8174 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK		0x3
8175 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT	2
8176 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK		0x3
8177 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT	4
8178 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK		0x3
8179 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT	6
8180 	u8 flags3;
8181 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_MASK		0x3
8182 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT	0
8183 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_MASK		0x3
8184 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_SHIFT	2
8185 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_MASK	0x3
8186 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_SHIFT	4
8187 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK		0x3
8188 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT	6
8189 	u8 flags4;
8190 #define XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_MASK        0x3
8191 #define XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_SHIFT       0
8192 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_MASK     0x3
8193 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_SHIFT    2
8194 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK	0x3
8195 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_SHIFT	4
8196 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK	0x3
8197 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_SHIFT	6
8198 	u8 flags5;
8199 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_MASK		0x3
8200 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_SHIFT		0
8201 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_MASK		0x3
8202 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_SHIFT		2
8203 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_MASK	0x3
8204 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_SHIFT	4
8205 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_MASK		0x3
8206 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_SHIFT		6
8207 	u8 flags6;
8208 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_MASK	0x3
8209 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_SHIFT	0
8210 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_MASK	0x3
8211 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_SHIFT	2
8212 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_MASK	0x3
8213 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_SHIFT	4
8214 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_MASK	0x3
8215 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_SHIFT	6
8216 	u8 flags7;
8217 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_MASK	0x3
8218 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_SHIFT	0
8219 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_MASK	0x3
8220 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_SHIFT	2
8221 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_MASK	0x3
8222 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_SHIFT	4
8223 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK	0x1
8224 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT	6
8225 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK	0x1
8226 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT	7
8227 	u8 flags8;
8228 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK		0x1
8229 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT		0
8230 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK		0x1
8231 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT		1
8232 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK	0x1
8233 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT	2
8234 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_MASK	0x1
8235 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT	3
8236 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK	0x1
8237 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_SHIFT	4
8238 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK	0x1
8239 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT	5
8240 #define XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_EN_MASK     0x1
8241 #define XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_EN_SHIFT    6
8242 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_EN_MASK  0x1
8243 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_EN_SHIFT 7
8244 	u8 flags9;
8245 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_MASK		0x1
8246 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_SHIFT		0
8247 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_MASK		0x1
8248 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_SHIFT		1
8249 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_MASK		0x1
8250 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_SHIFT		2
8251 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_MASK		0x1
8252 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_SHIFT		3
8253 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_MASK	0x1
8254 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_SHIFT	4
8255 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_MASK		0x1
8256 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_SHIFT		5
8257 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_MASK		0x1
8258 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_SHIFT		6
8259 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_MASK		0x1
8260 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_SHIFT		7
8261 	u8 flags10;
8262 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_MASK		0x1
8263 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_SHIFT		0
8264 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_MASK		0x1
8265 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_SHIFT		1
8266 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_MASK		0x1
8267 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_SHIFT		2
8268 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_MASK		0x1
8269 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_SHIFT		3
8270 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_MASK	0x1
8271 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_SHIFT	4
8272 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_MASK		0x1
8273 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_SHIFT		5
8274 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK		0x1
8275 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT		6
8276 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK		0x1
8277 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT		7
8278 	u8 flags11;
8279 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK		0x1
8280 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT		0
8281 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK		0x1
8282 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT		1
8283 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK		0x1
8284 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT		2
8285 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK		0x1
8286 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT		3
8287 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK		0x1
8288 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT		4
8289 #define XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_MASK	0x1
8290 #define XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_SHIFT	5
8291 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_MASK	0x1
8292 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_SHIFT	6
8293 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_MASK		0x1
8294 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_SHIFT		7
8295 	u8 flags12;
8296 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_MASK		0x1
8297 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_SHIFT		0
8298 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_MASK		0x1
8299 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_SHIFT		1
8300 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_MASK	0x1
8301 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_SHIFT	2
8302 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_MASK	0x1
8303 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_SHIFT	3
8304 #define XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_MASK	0x1
8305 #define XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_SHIFT	4
8306 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_MASK		0x1
8307 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_SHIFT		5
8308 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_MASK	0x1
8309 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_SHIFT	6
8310 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_MASK	0x1
8311 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_SHIFT	7
8312 	u8 flags13;
8313 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_MASK		0x1
8314 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_SHIFT		0
8315 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_MASK		0x1
8316 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_SHIFT		1
8317 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_MASK	0x1
8318 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_SHIFT	2
8319 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_MASK	0x1
8320 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_SHIFT	3
8321 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_MASK	0x1
8322 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_SHIFT	4
8323 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_MASK	0x1
8324 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_SHIFT	5
8325 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_MASK	0x1
8326 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_SHIFT	6
8327 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_MASK	0x1
8328 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_SHIFT	7
8329 	u8 flags14;
8330 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_MASK	0x1
8331 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_SHIFT	0
8332 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_MASK		0x1
8333 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_SHIFT		1
8334 #define XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_MASK	0x3
8335 #define XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_SHIFT	2
8336 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_MASK		0x1
8337 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_SHIFT		4
8338 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK	0x1
8339 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT	5
8340 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_MASK		0x3
8341 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_SHIFT		6
8342 	u8 byte2;
8343 	__le16 physical_q0;
8344 	__le16 word1;
8345 	__le16 sq_cmp_cons;
8346 	__le16 sq_cons;
8347 	__le16 sq_prod;
8348 	__le16 dif_error_first_sq_cons;
8349 	__le16 conn_dpi;
8350 	u8 dif_error_sge_index;
8351 	u8 byte4;
8352 	u8 byte5;
8353 	u8 byte6;
8354 	__le32 lsn;
8355 	__le32 ssn;
8356 	__le32 snd_una_psn;
8357 	__le32 snd_nxt_psn;
8358 	__le32 dif_error_offset;
8359 	__le32 orq_cons_th;
8360 	__le32 orq_cons;
8361 };
8362 
8363 struct xstorm_roce_resp_conn_ag_ctx {
8364 	u8 reserved0;
8365 	u8 state;
8366 	u8 flags0;
8367 #define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
8368 #define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
8369 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_MASK		0x1
8370 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_SHIFT		1
8371 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_MASK		0x1
8372 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_SHIFT		2
8373 #define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_MASK	0x1
8374 #define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT	3
8375 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_MASK		0x1
8376 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_SHIFT		4
8377 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_MASK		0x1
8378 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_SHIFT		5
8379 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_MASK		0x1
8380 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_SHIFT		6
8381 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_MASK		0x1
8382 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_SHIFT		7
8383 	u8 flags1;
8384 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_MASK		0x1
8385 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_SHIFT		0
8386 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_MASK		0x1
8387 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_SHIFT		1
8388 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_MASK		0x1
8389 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_SHIFT		2
8390 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK		0x1
8391 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_SHIFT		3
8392 #define XSTORM_ROCE_RESP_CONN_AG_CTX_MSDM_FLUSH_MASK		0x1
8393 #define XSTORM_ROCE_RESP_CONN_AG_CTX_MSDM_FLUSH_SHIFT	4
8394 #define XSTORM_ROCE_RESP_CONN_AG_CTX_MSEM_FLUSH_MASK		0x1
8395 #define XSTORM_ROCE_RESP_CONN_AG_CTX_MSEM_FLUSH_SHIFT	5
8396 #define XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK	0x1
8397 #define XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_SHIFT	6
8398 #define XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK	0x1
8399 #define XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_SHIFT	7
8400 	u8 flags2;
8401 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK	0x3
8402 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT	0
8403 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK	0x3
8404 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT	2
8405 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK	0x3
8406 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT	4
8407 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK	0x3
8408 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT	6
8409 	u8 flags3;
8410 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_MASK		0x3
8411 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_SHIFT		0
8412 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK	0x3
8413 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT	2
8414 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_MASK	0x3
8415 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_SHIFT	4
8416 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK	0x3
8417 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT	6
8418 	u8 flags4;
8419 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK	0x3
8420 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT	0
8421 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK	0x3
8422 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT	2
8423 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK	0x3
8424 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT	4
8425 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_MASK	0x3
8426 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_SHIFT	6
8427 	u8 flags5;
8428 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_MASK	0x3
8429 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_SHIFT	0
8430 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_MASK	0x3
8431 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_SHIFT	2
8432 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_MASK	0x3
8433 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_SHIFT	4
8434 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_MASK	0x3
8435 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_SHIFT	6
8436 	u8 flags6;
8437 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_MASK	0x3
8438 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_SHIFT	0
8439 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_MASK	0x3
8440 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_SHIFT	2
8441 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_MASK	0x3
8442 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_SHIFT	4
8443 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_MASK	0x3
8444 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_SHIFT	6
8445 	u8 flags7;
8446 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_MASK	0x3
8447 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_SHIFT	0
8448 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_MASK	0x3
8449 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_SHIFT	2
8450 #define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_MASK	0x3
8451 #define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_SHIFT	4
8452 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK	0x1
8453 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT	6
8454 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK	0x1
8455 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT	7
8456 	u8 flags8;
8457 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK		0x1
8458 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT		0
8459 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK		0x1
8460 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT		1
8461 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_MASK	0x1
8462 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_SHIFT	2
8463 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK	0x1
8464 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT	3
8465 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK	0x1
8466 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_SHIFT	4
8467 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK	0x1
8468 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT	5
8469 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK		0x1
8470 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT		6
8471 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK		0x1
8472 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT		7
8473 	u8 flags9;
8474 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK	0x1
8475 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT	0
8476 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_MASK	0x1
8477 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_SHIFT	1
8478 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_MASK	0x1
8479 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_SHIFT	2
8480 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_MASK	0x1
8481 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_SHIFT	3
8482 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_MASK	0x1
8483 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_SHIFT	4
8484 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_MASK	0x1
8485 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_SHIFT	5
8486 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_MASK	0x1
8487 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_SHIFT	6
8488 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_MASK	0x1
8489 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_SHIFT	7
8490 	u8 flags10;
8491 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_MASK		0x1
8492 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_SHIFT		0
8493 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_MASK		0x1
8494 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_SHIFT		1
8495 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_MASK		0x1
8496 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_SHIFT		2
8497 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_MASK		0x1
8498 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_SHIFT		3
8499 #define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_MASK	0x1
8500 #define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT	4
8501 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_MASK		0x1
8502 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_SHIFT		5
8503 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK		0x1
8504 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT		6
8505 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK		0x1
8506 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT		7
8507 	u8 flags11;
8508 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK		0x1
8509 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT		0
8510 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK		0x1
8511 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT		1
8512 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK		0x1
8513 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT		2
8514 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK		0x1
8515 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT		3
8516 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK		0x1
8517 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT		4
8518 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK		0x1
8519 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT		5
8520 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_MASK	0x1
8521 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_SHIFT	6
8522 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_MASK		0x1
8523 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_SHIFT		7
8524 	u8 flags12;
8525 #define XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_MASK	0x1
8526 #define XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_SHIFT	0
8527 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_MASK		0x1
8528 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_SHIFT		1
8529 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_MASK	0x1
8530 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_SHIFT	2
8531 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_MASK	0x1
8532 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_SHIFT	3
8533 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_MASK		0x1
8534 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_SHIFT		4
8535 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_MASK		0x1
8536 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_SHIFT		5
8537 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_MASK		0x1
8538 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_SHIFT		6
8539 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_MASK		0x1
8540 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_SHIFT		7
8541 	u8 flags13;
8542 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_MASK		0x1
8543 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_SHIFT		0
8544 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_MASK		0x1
8545 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_SHIFT		1
8546 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_MASK	0x1
8547 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_SHIFT	2
8548 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_MASK	0x1
8549 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_SHIFT	3
8550 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_MASK	0x1
8551 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_SHIFT	4
8552 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_MASK	0x1
8553 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_SHIFT	5
8554 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_MASK	0x1
8555 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_SHIFT	6
8556 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_MASK	0x1
8557 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_SHIFT	7
8558 	u8 flags14;
8559 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_MASK	0x1
8560 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_SHIFT	0
8561 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_MASK	0x1
8562 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_SHIFT	1
8563 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_MASK	0x1
8564 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_SHIFT	2
8565 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_MASK	0x1
8566 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_SHIFT	3
8567 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_MASK	0x1
8568 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_SHIFT	4
8569 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_MASK	0x1
8570 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_SHIFT	5
8571 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_MASK	0x3
8572 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_SHIFT	6
8573 	u8 byte2;
8574 	__le16 physical_q0;
8575 	__le16 irq_prod_shadow;
8576 	__le16 word2;
8577 	__le16 irq_cons;
8578 	__le16 irq_prod;
8579 	__le16 e5_reserved1;
8580 	__le16 conn_dpi;
8581 	u8 rxmit_opcode;
8582 	u8 byte4;
8583 	u8 byte5;
8584 	u8 byte6;
8585 	__le32 rxmit_psn_and_id;
8586 	__le32 rxmit_bytes_length;
8587 	__le32 psn;
8588 	__le32 reg3;
8589 	__le32 reg4;
8590 	__le32 reg5;
8591 	__le32 msn_and_syndrome;
8592 };
8593 
8594 struct ystorm_roce_conn_ag_ctx {
8595 	u8 byte0;
8596 	u8 byte1;
8597 	u8 flags0;
8598 #define YSTORM_ROCE_CONN_AG_CTX_BIT0_MASK     0x1
8599 #define YSTORM_ROCE_CONN_AG_CTX_BIT0_SHIFT    0
8600 #define YSTORM_ROCE_CONN_AG_CTX_BIT1_MASK     0x1
8601 #define YSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT    1
8602 #define YSTORM_ROCE_CONN_AG_CTX_CF0_MASK      0x3
8603 #define YSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT     2
8604 #define YSTORM_ROCE_CONN_AG_CTX_CF1_MASK      0x3
8605 #define YSTORM_ROCE_CONN_AG_CTX_CF1_SHIFT     4
8606 #define YSTORM_ROCE_CONN_AG_CTX_CF2_MASK      0x3
8607 #define YSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT     6
8608 	u8 flags1;
8609 #define YSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK    0x1
8610 #define YSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT   0
8611 #define YSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK    0x1
8612 #define YSTORM_ROCE_CONN_AG_CTX_CF1EN_SHIFT   1
8613 #define YSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK    0x1
8614 #define YSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT   2
8615 #define YSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK  0x1
8616 #define YSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT 3
8617 #define YSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK  0x1
8618 #define YSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 4
8619 #define YSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK  0x1
8620 #define YSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 5
8621 #define YSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK  0x1
8622 #define YSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 6
8623 #define YSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK  0x1
8624 #define YSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 7
8625 	u8 byte2;
8626 	u8 byte3;
8627 	__le16 word0;
8628 	__le32 reg0;
8629 	__le32 reg1;
8630 	__le16 word1;
8631 	__le16 word2;
8632 	__le16 word3;
8633 	__le16 word4;
8634 	__le32 reg2;
8635 	__le32 reg3;
8636 };
8637 
8638 struct ystorm_roce_req_conn_ag_ctx {
8639 	u8 byte0;
8640 	u8 byte1;
8641 	u8 flags0;
8642 #define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK	0x1
8643 #define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT	0
8644 #define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK	0x1
8645 #define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT	1
8646 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK		0x3
8647 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT	2
8648 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK		0x3
8649 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT	4
8650 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK		0x3
8651 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT	6
8652 	u8 flags1;
8653 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK	0x1
8654 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT	0
8655 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK	0x1
8656 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT	1
8657 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK	0x1
8658 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT	2
8659 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK	0x1
8660 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT	3
8661 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK	0x1
8662 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT	4
8663 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK	0x1
8664 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT	5
8665 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK	0x1
8666 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT	6
8667 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK	0x1
8668 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT	7
8669 	u8 byte2;
8670 	u8 byte3;
8671 	__le16 word0;
8672 	__le32 reg0;
8673 	__le32 reg1;
8674 	__le16 word1;
8675 	__le16 word2;
8676 	__le16 word3;
8677 	__le16 word4;
8678 	__le32 reg2;
8679 	__le32 reg3;
8680 };
8681 
8682 struct ystorm_roce_resp_conn_ag_ctx {
8683 	u8 byte0;
8684 	u8 byte1;
8685 	u8 flags0;
8686 #define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK	0x1
8687 #define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT	0
8688 #define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK	0x1
8689 #define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT	1
8690 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK	0x3
8691 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT	2
8692 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK	0x3
8693 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT	4
8694 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK	0x3
8695 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT	6
8696 	u8 flags1;
8697 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK	0x1
8698 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT	0
8699 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK	0x1
8700 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT	1
8701 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK	0x1
8702 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT	2
8703 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK	0x1
8704 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT	3
8705 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK	0x1
8706 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT	4
8707 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK	0x1
8708 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT	5
8709 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK	0x1
8710 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT	6
8711 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK	0x1
8712 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT	7
8713 	u8 byte2;
8714 	u8 byte3;
8715 	__le16 word0;
8716 	__le32 reg0;
8717 	__le32 reg1;
8718 	__le16 word1;
8719 	__le16 word2;
8720 	__le16 word3;
8721 	__le16 word4;
8722 	__le32 reg2;
8723 	__le32 reg3;
8724 };
8725 
8726 /* Roce doorbell data */
8727 enum roce_flavor {
8728 	PLAIN_ROCE,
8729 	RROCE_IPV4,
8730 	RROCE_IPV6,
8731 	MAX_ROCE_FLAVOR
8732 };
8733 
8734 /* The iwarp storm context of Ystorm */
8735 struct ystorm_iwarp_conn_st_ctx {
8736 	__le32 reserved[4];
8737 };
8738 
8739 /* The iwarp storm context of Pstorm */
8740 struct pstorm_iwarp_conn_st_ctx {
8741 	__le32 reserved[36];
8742 };
8743 
8744 /* The iwarp storm context of Xstorm */
8745 struct xstorm_iwarp_conn_st_ctx {
8746 	__le32 reserved[48];
8747 };
8748 
8749 struct xstorm_iwarp_conn_ag_ctx {
8750 	u8 reserved0;
8751 	u8 state;
8752 	u8 flags0;
8753 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
8754 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
8755 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_MASK	0x1
8756 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_SHIFT	1
8757 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_MASK	0x1
8758 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_SHIFT	2
8759 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_MASK	0x1
8760 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT	3
8761 #define XSTORM_IWARP_CONN_AG_CTX_BIT4_MASK		0x1
8762 #define XSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT		4
8763 #define XSTORM_IWARP_CONN_AG_CTX_RESERVED2_MASK	0x1
8764 #define XSTORM_IWARP_CONN_AG_CTX_RESERVED2_SHIFT	5
8765 #define XSTORM_IWARP_CONN_AG_CTX_BIT6_MASK		0x1
8766 #define XSTORM_IWARP_CONN_AG_CTX_BIT6_SHIFT		6
8767 #define XSTORM_IWARP_CONN_AG_CTX_BIT7_MASK		0x1
8768 #define XSTORM_IWARP_CONN_AG_CTX_BIT7_SHIFT		7
8769 	u8 flags1;
8770 #define XSTORM_IWARP_CONN_AG_CTX_BIT8_MASK				0x1
8771 #define XSTORM_IWARP_CONN_AG_CTX_BIT8_SHIFT				0
8772 #define XSTORM_IWARP_CONN_AG_CTX_BIT9_MASK				0x1
8773 #define XSTORM_IWARP_CONN_AG_CTX_BIT9_SHIFT				1
8774 #define XSTORM_IWARP_CONN_AG_CTX_BIT10_MASK				0x1
8775 #define XSTORM_IWARP_CONN_AG_CTX_BIT10_SHIFT				2
8776 #define XSTORM_IWARP_CONN_AG_CTX_BIT11_MASK				0x1
8777 #define XSTORM_IWARP_CONN_AG_CTX_BIT11_SHIFT				3
8778 #define XSTORM_IWARP_CONN_AG_CTX_BIT12_MASK				0x1
8779 #define XSTORM_IWARP_CONN_AG_CTX_BIT12_SHIFT				4
8780 #define XSTORM_IWARP_CONN_AG_CTX_BIT13_MASK				0x1
8781 #define XSTORM_IWARP_CONN_AG_CTX_BIT13_SHIFT				5
8782 #define XSTORM_IWARP_CONN_AG_CTX_BIT14_MASK				0x1
8783 #define XSTORM_IWARP_CONN_AG_CTX_BIT14_SHIFT				6
8784 #define XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_MASK	0x1
8785 #define XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_SHIFT 7
8786 	u8 flags2;
8787 #define XSTORM_IWARP_CONN_AG_CTX_CF0_MASK			0x3
8788 #define XSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT			0
8789 #define XSTORM_IWARP_CONN_AG_CTX_CF1_MASK			0x3
8790 #define XSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT			2
8791 #define XSTORM_IWARP_CONN_AG_CTX_CF2_MASK			0x3
8792 #define XSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT			4
8793 #define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK		0x3
8794 #define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT	6
8795 	u8 flags3;
8796 #define XSTORM_IWARP_CONN_AG_CTX_CF4_MASK	0x3
8797 #define XSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT	0
8798 #define XSTORM_IWARP_CONN_AG_CTX_CF5_MASK	0x3
8799 #define XSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT	2
8800 #define XSTORM_IWARP_CONN_AG_CTX_CF6_MASK	0x3
8801 #define XSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT	4
8802 #define XSTORM_IWARP_CONN_AG_CTX_CF7_MASK	0x3
8803 #define XSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT	6
8804 	u8 flags4;
8805 #define XSTORM_IWARP_CONN_AG_CTX_CF8_MASK	0x3
8806 #define XSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT	0
8807 #define XSTORM_IWARP_CONN_AG_CTX_CF9_MASK	0x3
8808 #define XSTORM_IWARP_CONN_AG_CTX_CF9_SHIFT	2
8809 #define XSTORM_IWARP_CONN_AG_CTX_CF10_MASK	0x3
8810 #define XSTORM_IWARP_CONN_AG_CTX_CF10_SHIFT	4
8811 #define XSTORM_IWARP_CONN_AG_CTX_CF11_MASK	0x3
8812 #define XSTORM_IWARP_CONN_AG_CTX_CF11_SHIFT	6
8813 	u8 flags5;
8814 #define XSTORM_IWARP_CONN_AG_CTX_CF12_MASK		0x3
8815 #define XSTORM_IWARP_CONN_AG_CTX_CF12_SHIFT		0
8816 #define XSTORM_IWARP_CONN_AG_CTX_CF13_MASK		0x3
8817 #define XSTORM_IWARP_CONN_AG_CTX_CF13_SHIFT		2
8818 #define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_MASK	0x3
8819 #define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT	4
8820 #define XSTORM_IWARP_CONN_AG_CTX_CF15_MASK		0x3
8821 #define XSTORM_IWARP_CONN_AG_CTX_CF15_SHIFT		6
8822 	u8 flags6;
8823 #define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_MASK	0x3
8824 #define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_SHIFT 0
8825 #define XSTORM_IWARP_CONN_AG_CTX_CF17_MASK				0x3
8826 #define XSTORM_IWARP_CONN_AG_CTX_CF17_SHIFT				2
8827 #define XSTORM_IWARP_CONN_AG_CTX_CF18_MASK				0x3
8828 #define XSTORM_IWARP_CONN_AG_CTX_CF18_SHIFT				4
8829 #define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_MASK			0x3
8830 #define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_SHIFT			6
8831 	u8 flags7;
8832 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK	0x3
8833 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT	0
8834 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_MASK	0x3
8835 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_SHIFT	2
8836 #define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_MASK	0x3
8837 #define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_SHIFT	4
8838 #define XSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK		0x1
8839 #define XSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT		6
8840 #define XSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK		0x1
8841 #define XSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT		7
8842 	u8 flags8;
8843 #define XSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK			0x1
8844 #define XSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT			0
8845 #define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK	0x1
8846 #define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT	1
8847 #define XSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK			0x1
8848 #define XSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT			2
8849 #define XSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK			0x1
8850 #define XSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT			3
8851 #define XSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK			0x1
8852 #define XSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT			4
8853 #define XSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK			0x1
8854 #define XSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT			5
8855 #define XSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK			0x1
8856 #define XSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT			6
8857 #define XSTORM_IWARP_CONN_AG_CTX_CF9EN_MASK			0x1
8858 #define XSTORM_IWARP_CONN_AG_CTX_CF9EN_SHIFT			7
8859 	u8 flags9;
8860 #define XSTORM_IWARP_CONN_AG_CTX_CF10EN_MASK				0x1
8861 #define XSTORM_IWARP_CONN_AG_CTX_CF10EN_SHIFT			0
8862 #define XSTORM_IWARP_CONN_AG_CTX_CF11EN_MASK				0x1
8863 #define XSTORM_IWARP_CONN_AG_CTX_CF11EN_SHIFT			1
8864 #define XSTORM_IWARP_CONN_AG_CTX_CF12EN_MASK				0x1
8865 #define XSTORM_IWARP_CONN_AG_CTX_CF12EN_SHIFT			2
8866 #define XSTORM_IWARP_CONN_AG_CTX_CF13EN_MASK				0x1
8867 #define XSTORM_IWARP_CONN_AG_CTX_CF13EN_SHIFT			3
8868 #define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK			0x1
8869 #define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT		4
8870 #define XSTORM_IWARP_CONN_AG_CTX_CF15EN_MASK				0x1
8871 #define XSTORM_IWARP_CONN_AG_CTX_CF15EN_SHIFT			5
8872 #define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_MASK 0x1
8873 #define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_SHIFT 6
8874 #define XSTORM_IWARP_CONN_AG_CTX_CF17EN_MASK				0x1
8875 #define XSTORM_IWARP_CONN_AG_CTX_CF17EN_SHIFT			7
8876 	u8 flags10;
8877 #define XSTORM_IWARP_CONN_AG_CTX_CF18EN_MASK			0x1
8878 #define XSTORM_IWARP_CONN_AG_CTX_CF18EN_SHIFT		0
8879 #define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_MASK		0x1
8880 #define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT		1
8881 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK		0x1
8882 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT		2
8883 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_MASK		0x1
8884 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_SHIFT		3
8885 #define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_MASK		0x1
8886 #define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT		4
8887 #define XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_EN_MASK               0x1
8888 #define XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_EN_SHIFT              5
8889 #define XSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK		0x1
8890 #define XSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT		6
8891 #define XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_MASK	0x1
8892 #define XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_SHIFT	7
8893 	u8 flags11;
8894 #define XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_MASK	0x1
8895 #define XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT	0
8896 #define XSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK	0x1
8897 #define XSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT	1
8898 #define XSTORM_IWARP_CONN_AG_CTX_RESERVED3_MASK	0x1
8899 #define XSTORM_IWARP_CONN_AG_CTX_RESERVED3_SHIFT	2
8900 #define XSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK	0x1
8901 #define XSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT	3
8902 #define XSTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK	0x1
8903 #define XSTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT	4
8904 #define XSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK	0x1
8905 #define XSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT	5
8906 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_MASK	0x1
8907 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_SHIFT	6
8908 #define XSTORM_IWARP_CONN_AG_CTX_RULE9EN_MASK	0x1
8909 #define XSTORM_IWARP_CONN_AG_CTX_RULE9EN_SHIFT	7
8910 	u8 flags12;
8911 #define XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_MASK	0x1
8912 #define XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_SHIFT	0
8913 #define XSTORM_IWARP_CONN_AG_CTX_RULE11EN_MASK		0x1
8914 #define XSTORM_IWARP_CONN_AG_CTX_RULE11EN_SHIFT		1
8915 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_MASK		0x1
8916 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_SHIFT		2
8917 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_MASK		0x1
8918 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_SHIFT		3
8919 #define XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_MASK	0x1
8920 #define XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_SHIFT	4
8921 #define XSTORM_IWARP_CONN_AG_CTX_RULE15EN_MASK		0x1
8922 #define XSTORM_IWARP_CONN_AG_CTX_RULE15EN_SHIFT		5
8923 #define XSTORM_IWARP_CONN_AG_CTX_RULE16EN_MASK		0x1
8924 #define XSTORM_IWARP_CONN_AG_CTX_RULE16EN_SHIFT		6
8925 #define XSTORM_IWARP_CONN_AG_CTX_RULE17EN_MASK		0x1
8926 #define XSTORM_IWARP_CONN_AG_CTX_RULE17EN_SHIFT		7
8927 	u8 flags13;
8928 #define XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_MASK	0x1
8929 #define XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_SHIFT	0
8930 #define XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_MASK	0x1
8931 #define XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_SHIFT	1
8932 #define XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_MASK	0x1
8933 #define XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_SHIFT	2
8934 #define XSTORM_IWARP_CONN_AG_CTX_RULE21EN_MASK		0x1
8935 #define XSTORM_IWARP_CONN_AG_CTX_RULE21EN_SHIFT		3
8936 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_MASK		0x1
8937 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_SHIFT		4
8938 #define XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_MASK	0x1
8939 #define XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_SHIFT	5
8940 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_MASK		0x1
8941 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_SHIFT		6
8942 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_MASK		0x1
8943 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_SHIFT		7
8944 	u8 flags14;
8945 #define XSTORM_IWARP_CONN_AG_CTX_BIT16_MASK		0x1
8946 #define XSTORM_IWARP_CONN_AG_CTX_BIT16_SHIFT		0
8947 #define XSTORM_IWARP_CONN_AG_CTX_BIT17_MASK		0x1
8948 #define XSTORM_IWARP_CONN_AG_CTX_BIT17_SHIFT		1
8949 #define XSTORM_IWARP_CONN_AG_CTX_BIT18_MASK		0x1
8950 #define XSTORM_IWARP_CONN_AG_CTX_BIT18_SHIFT		2
8951 #define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_MASK	0x1
8952 #define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_SHIFT	3
8953 #define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_MASK	0x1
8954 #define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_SHIFT	4
8955 #define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_MASK	0x1
8956 #define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_SHIFT	5
8957 #define XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_MASK	0x3
8958 #define XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_SHIFT	6
8959 	u8 byte2;
8960 	__le16 physical_q0;
8961 	__le16 physical_q1;
8962 	__le16 sq_comp_cons;
8963 	__le16 sq_tx_cons;
8964 	__le16 sq_prod;
8965 	__le16 word5;
8966 	__le16 conn_dpi;
8967 	u8 byte3;
8968 	u8 byte4;
8969 	u8 byte5;
8970 	u8 byte6;
8971 	__le32 reg0;
8972 	__le32 reg1;
8973 	__le32 reg2;
8974 	__le32 more_to_send_seq;
8975 	__le32 reg4;
8976 	__le32 rewinded_snd_max_or_term_opcode;
8977 	__le32 rd_msn;
8978 	__le16 irq_prod_via_msdm;
8979 	__le16 irq_cons;
8980 	__le16 hq_cons_th_or_mpa_data;
8981 	__le16 hq_cons;
8982 	__le32 atom_msn;
8983 	__le32 orq_cons;
8984 	__le32 orq_cons_th;
8985 	u8 byte7;
8986 	u8 wqe_data_pad_bytes;
8987 	u8 max_ord;
8988 	u8 former_hq_prod;
8989 	u8 irq_prod_via_msem;
8990 	u8 byte12;
8991 	u8 max_pkt_pdu_size_lo;
8992 	u8 max_pkt_pdu_size_hi;
8993 	u8 byte15;
8994 	u8 e5_reserved;
8995 	__le16 e5_reserved4;
8996 	__le32 reg10;
8997 	__le32 reg11;
8998 	__le32 shared_queue_page_addr_lo;
8999 	__le32 shared_queue_page_addr_hi;
9000 	__le32 reg14;
9001 	__le32 reg15;
9002 	__le32 reg16;
9003 	__le32 reg17;
9004 };
9005 
9006 struct tstorm_iwarp_conn_ag_ctx {
9007 	u8 reserved0;
9008 	u8 state;
9009 	u8 flags0;
9010 #define TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
9011 #define TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
9012 #define TSTORM_IWARP_CONN_AG_CTX_BIT1_MASK		0x1
9013 #define TSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT		1
9014 #define TSTORM_IWARP_CONN_AG_CTX_BIT2_MASK		0x1
9015 #define TSTORM_IWARP_CONN_AG_CTX_BIT2_SHIFT		2
9016 #define TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_OR_TERMINATE_SENT_MASK  0x1
9017 #define TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_OR_TERMINATE_SENT_SHIFT 3
9018 #define TSTORM_IWARP_CONN_AG_CTX_BIT4_MASK		0x1
9019 #define TSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT		4
9020 #define TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_MASK	0x1
9021 #define TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_SHIFT	5
9022 #define TSTORM_IWARP_CONN_AG_CTX_CF0_MASK		0x3
9023 #define TSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT		6
9024 	u8 flags1;
9025 #define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_MASK		0x3
9026 #define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_SHIFT		0
9027 #define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_MASK		0x3
9028 #define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_SHIFT	2
9029 #define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK		0x3
9030 #define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT	4
9031 #define TSTORM_IWARP_CONN_AG_CTX_CF4_MASK			0x3
9032 #define TSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT			6
9033 	u8 flags2;
9034 #define TSTORM_IWARP_CONN_AG_CTX_CF5_MASK	0x3
9035 #define TSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT	0
9036 #define TSTORM_IWARP_CONN_AG_CTX_CF6_MASK	0x3
9037 #define TSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT	2
9038 #define TSTORM_IWARP_CONN_AG_CTX_CF7_MASK	0x3
9039 #define TSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT	4
9040 #define TSTORM_IWARP_CONN_AG_CTX_CF8_MASK	0x3
9041 #define TSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT	6
9042 	u8 flags3;
9043 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_MASK 0x3
9044 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_SHIFT 0
9045 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_MASK	0x3
9046 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_SHIFT	2
9047 #define TSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK				0x1
9048 #define TSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT				4
9049 #define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_MASK			0x1
9050 #define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_SHIFT			5
9051 #define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_MASK		0x1
9052 #define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_SHIFT		6
9053 #define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK		0x1
9054 #define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT		7
9055 	u8 flags4;
9056 #define TSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK				0x1
9057 #define TSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT				0
9058 #define TSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK				0x1
9059 #define TSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT				1
9060 #define TSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK				0x1
9061 #define TSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT				2
9062 #define TSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK				0x1
9063 #define TSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT				3
9064 #define TSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK				0x1
9065 #define TSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT				4
9066 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPL_EN_MASK 0x1
9067 #define	TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPL_EN_SHIFT 5
9068 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_MASK	0x1
9069 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_SHIFT	6
9070 #define TSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK			0x1
9071 #define TSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT			7
9072 	u8 flags5;
9073 #define TSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK		0x1
9074 #define TSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT		0
9075 #define TSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK		0x1
9076 #define TSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT		1
9077 #define TSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK		0x1
9078 #define TSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT		2
9079 #define TSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK		0x1
9080 #define TSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT		3
9081 #define TSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK		0x1
9082 #define TSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT		4
9083 #define TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_MASK	0x1
9084 #define TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_SHIFT	5
9085 #define TSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK		0x1
9086 #define TSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT		6
9087 #define TSTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK		0x1
9088 #define TSTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT		7
9089 	__le32 reg0;
9090 	__le32 reg1;
9091 	__le32 unaligned_nxt_seq;
9092 	__le32 reg3;
9093 	__le32 reg4;
9094 	__le32 reg5;
9095 	__le32 reg6;
9096 	__le32 reg7;
9097 	__le32 reg8;
9098 	u8 orq_cache_idx;
9099 	u8 hq_prod;
9100 	__le16 sq_tx_cons_th;
9101 	u8 orq_prod;
9102 	u8 irq_cons;
9103 	__le16 sq_tx_cons;
9104 	__le16 conn_dpi;
9105 	__le16 rq_prod;
9106 	__le32 snd_seq;
9107 	__le32 last_hq_sequence;
9108 };
9109 
9110 /* The iwarp storm context of Tstorm */
9111 struct tstorm_iwarp_conn_st_ctx {
9112 	__le32 reserved[60];
9113 };
9114 
9115 /* The iwarp storm context of Mstorm */
9116 struct mstorm_iwarp_conn_st_ctx {
9117 	__le32 reserved[32];
9118 };
9119 
9120 /* The iwarp storm context of Ustorm */
9121 struct ustorm_iwarp_conn_st_ctx {
9122 	struct regpair reserved[14];
9123 };
9124 
9125 /* iwarp connection context */
9126 struct iwarp_conn_context {
9127 	struct ystorm_iwarp_conn_st_ctx ystorm_st_context;
9128 	struct regpair ystorm_st_padding[2];
9129 	struct pstorm_iwarp_conn_st_ctx pstorm_st_context;
9130 	struct regpair pstorm_st_padding[2];
9131 	struct xstorm_iwarp_conn_st_ctx xstorm_st_context;
9132 	struct xstorm_iwarp_conn_ag_ctx xstorm_ag_context;
9133 	struct tstorm_iwarp_conn_ag_ctx tstorm_ag_context;
9134 	struct timers_context timer_context;
9135 	struct ustorm_rdma_conn_ag_ctx ustorm_ag_context;
9136 	struct tstorm_iwarp_conn_st_ctx tstorm_st_context;
9137 	struct regpair tstorm_st_padding[2];
9138 	struct mstorm_iwarp_conn_st_ctx mstorm_st_context;
9139 	struct ustorm_iwarp_conn_st_ctx ustorm_st_context;
9140 	struct regpair ustorm_st_padding[2];
9141 };
9142 
9143 /* iWARP create QP params passed by driver to FW in CreateQP Request Ramrod */
9144 struct iwarp_create_qp_ramrod_data {
9145 	u8 flags;
9146 #define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK	0x1
9147 #define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT	0
9148 #define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_MASK		0x1
9149 #define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_SHIFT		1
9150 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_MASK		0x1
9151 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT		2
9152 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_MASK		0x1
9153 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT		3
9154 #define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_MASK		0x1
9155 #define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_SHIFT		4
9156 #define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_MASK		0x1
9157 #define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_SHIFT		5
9158 #define IWARP_CREATE_QP_RAMROD_DATA_LOW_LATENCY_QUEUE_EN_MASK	0x1
9159 #define IWARP_CREATE_QP_RAMROD_DATA_LOW_LATENCY_QUEUE_EN_SHIFT	6
9160 #define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_MASK		0x1
9161 #define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_SHIFT		7
9162 	u8 reserved1;
9163 	__le16 pd;
9164 	__le16 sq_num_pages;
9165 	__le16 rq_num_pages;
9166 	__le32 reserved3[2];
9167 	struct regpair qp_handle_for_cqe;
9168 	struct rdma_srq_id srq_id;
9169 	__le32 cq_cid_for_sq;
9170 	__le32 cq_cid_for_rq;
9171 	__le16 dpi;
9172 	__le16 physical_q0;
9173 	__le16 physical_q1;
9174 	u8 reserved2[6];
9175 };
9176 
9177 /* iWARP completion queue types */
9178 enum iwarp_eqe_async_opcode {
9179 	IWARP_EVENT_TYPE_ASYNC_CONNECT_COMPLETE,
9180 	IWARP_EVENT_TYPE_ASYNC_ENHANCED_MPA_REPLY_ARRIVED,
9181 	IWARP_EVENT_TYPE_ASYNC_MPA_HANDSHAKE_COMPLETE,
9182 	IWARP_EVENT_TYPE_ASYNC_CID_CLEANED,
9183 	IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED,
9184 	IWARP_EVENT_TYPE_ASYNC_QP_IN_ERROR_STATE,
9185 	IWARP_EVENT_TYPE_ASYNC_CQ_OVERFLOW,
9186 	IWARP_EVENT_TYPE_ASYNC_SRQ_LIMIT,
9187 	IWARP_EVENT_TYPE_ASYNC_SRQ_EMPTY,
9188 	MAX_IWARP_EQE_ASYNC_OPCODE
9189 };
9190 
9191 struct iwarp_eqe_data_mpa_async_completion {
9192 	__le16 ulp_data_len;
9193 	u8 rtr_type_sent;
9194 	u8 reserved[5];
9195 };
9196 
9197 struct iwarp_eqe_data_tcp_async_completion {
9198 	__le16 ulp_data_len;
9199 	u8 mpa_handshake_mode;
9200 	u8 reserved[5];
9201 };
9202 
9203 /* iWARP completion queue types */
9204 enum iwarp_eqe_sync_opcode {
9205 	IWARP_EVENT_TYPE_TCP_OFFLOAD = 13,
9206 	IWARP_EVENT_TYPE_MPA_OFFLOAD,
9207 	IWARP_EVENT_TYPE_MPA_OFFLOAD_SEND_RTR,
9208 	IWARP_EVENT_TYPE_CREATE_QP,
9209 	IWARP_EVENT_TYPE_QUERY_QP,
9210 	IWARP_EVENT_TYPE_MODIFY_QP,
9211 	IWARP_EVENT_TYPE_DESTROY_QP,
9212 	IWARP_EVENT_TYPE_ABORT_TCP_OFFLOAD,
9213 	MAX_IWARP_EQE_SYNC_OPCODE
9214 };
9215 
9216 /* iWARP EQE completion status */
9217 enum iwarp_fw_return_code {
9218 	IWARP_CONN_ERROR_TCP_CONNECT_INVALID_PACKET = 6,
9219 	IWARP_CONN_ERROR_TCP_CONNECTION_RST,
9220 	IWARP_CONN_ERROR_TCP_CONNECT_TIMEOUT,
9221 	IWARP_CONN_ERROR_MPA_ERROR_REJECT,
9222 	IWARP_CONN_ERROR_MPA_NOT_SUPPORTED_VER,
9223 	IWARP_CONN_ERROR_MPA_RST,
9224 	IWARP_CONN_ERROR_MPA_FIN,
9225 	IWARP_CONN_ERROR_MPA_RTR_MISMATCH,
9226 	IWARP_CONN_ERROR_MPA_INSUF_IRD,
9227 	IWARP_CONN_ERROR_MPA_INVALID_PACKET,
9228 	IWARP_CONN_ERROR_MPA_LOCAL_ERROR,
9229 	IWARP_CONN_ERROR_MPA_TIMEOUT,
9230 	IWARP_CONN_ERROR_MPA_TERMINATE,
9231 	IWARP_QP_IN_ERROR_GOOD_CLOSE,
9232 	IWARP_QP_IN_ERROR_BAD_CLOSE,
9233 	IWARP_EXCEPTION_DETECTED_LLP_CLOSED,
9234 	IWARP_EXCEPTION_DETECTED_LLP_RESET,
9235 	IWARP_EXCEPTION_DETECTED_IRQ_FULL,
9236 	IWARP_EXCEPTION_DETECTED_RQ_EMPTY,
9237 	IWARP_EXCEPTION_DETECTED_LLP_TIMEOUT,
9238 	IWARP_EXCEPTION_DETECTED_REMOTE_PROTECTION_ERROR,
9239 	IWARP_EXCEPTION_DETECTED_CQ_OVERFLOW,
9240 	IWARP_EXCEPTION_DETECTED_LOCAL_CATASTROPHIC,
9241 	IWARP_EXCEPTION_DETECTED_LOCAL_ACCESS_ERROR,
9242 	IWARP_EXCEPTION_DETECTED_REMOTE_OPERATION_ERROR,
9243 	IWARP_EXCEPTION_DETECTED_TERMINATE_RECEIVED,
9244 	MAX_IWARP_FW_RETURN_CODE
9245 };
9246 
9247 /* unaligned opaque data received from LL2 */
9248 struct iwarp_init_func_params {
9249 	u8 ll2_ooo_q_index;
9250 	u8 reserved1[7];
9251 };
9252 
9253 /* iwarp func init ramrod data */
9254 struct iwarp_init_func_ramrod_data {
9255 	struct rdma_init_func_ramrod_data rdma;
9256 	struct tcp_init_params tcp;
9257 	struct iwarp_init_func_params iwarp;
9258 };
9259 
9260 /* iWARP QP - possible states to transition to */
9261 enum iwarp_modify_qp_new_state_type {
9262 	IWARP_MODIFY_QP_STATE_CLOSING = 1,
9263 	IWARP_MODIFY_QP_STATE_ERROR = 2,
9264 	MAX_IWARP_MODIFY_QP_NEW_STATE_TYPE
9265 };
9266 
9267 /* iwarp modify qp responder ramrod data */
9268 struct iwarp_modify_qp_ramrod_data {
9269 	__le16 transition_to_state;
9270 	__le16 flags;
9271 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_MASK		0x1
9272 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT		0
9273 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_MASK		0x1
9274 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT		1
9275 #define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_MASK		0x1
9276 #define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_SHIFT		2
9277 #define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_MASK		0x1
9278 #define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_SHIFT	3
9279 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK	0x1
9280 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT	4
9281 #define IWARP_MODIFY_QP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK	0x1
9282 #define IWARP_MODIFY_QP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_SHIFT	5
9283 #define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_MASK		0x3FF
9284 #define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_SHIFT		6
9285 	__le16 physical_q0;
9286 	__le16 physical_q1;
9287 	__le32 reserved1[10];
9288 };
9289 
9290 /* MPA params for Enhanced mode */
9291 struct mpa_rq_params {
9292 	__le32 ird;
9293 	__le32 ord;
9294 };
9295 
9296 /* MPA host Address-Len for private data */
9297 struct mpa_ulp_buffer {
9298 	struct regpair addr;
9299 	__le16 len;
9300 	__le16 reserved[3];
9301 };
9302 
9303 /* iWARP MPA offload params common to Basic and Enhanced modes */
9304 struct mpa_outgoing_params {
9305 	u8 crc_needed;
9306 	u8 reject;
9307 	u8 reserved[6];
9308 	struct mpa_rq_params out_rq;
9309 	struct mpa_ulp_buffer outgoing_ulp_buffer;
9310 };
9311 
9312 /* iWARP MPA offload params passed by driver to FW in MPA Offload Request
9313  * Ramrod.
9314  */
9315 struct iwarp_mpa_offload_ramrod_data {
9316 	struct mpa_outgoing_params common;
9317 	__le32 tcp_cid;
9318 	u8 mode;
9319 	u8 tcp_connect_side;
9320 	u8 rtr_pref;
9321 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_MASK	0x7
9322 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_SHIFT	0
9323 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_MASK		0x1F
9324 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_SHIFT		3
9325 	u8 reserved2;
9326 	struct mpa_ulp_buffer incoming_ulp_buffer;
9327 	struct regpair async_eqe_output_buf;
9328 	struct regpair handle_for_async;
9329 	struct regpair shared_queue_addr;
9330 	__le32 additional_setup_time;
9331 	__le16 rcv_wnd;
9332 	u8 stats_counter_id;
9333 	u8 reserved3[9];
9334 };
9335 
9336 /* iWARP TCP connection offload params passed by driver to FW */
9337 struct iwarp_offload_params {
9338 	struct mpa_ulp_buffer incoming_ulp_buffer;
9339 	struct regpair async_eqe_output_buf;
9340 	struct regpair handle_for_async;
9341 	__le32 additional_setup_time;
9342 	__le16 physical_q0;
9343 	__le16 physical_q1;
9344 	u8 stats_counter_id;
9345 	u8 mpa_mode;
9346 	u8 src_vport_id;
9347 	u8 reserved[5];
9348 };
9349 
9350 /* iWARP query QP output params */
9351 struct iwarp_query_qp_output_params {
9352 	__le32 flags;
9353 #define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_MASK	0x1
9354 #define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_SHIFT	0
9355 #define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_MASK	0x7FFFFFFF
9356 #define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_SHIFT	1
9357 	u8 reserved1[4];
9358 };
9359 
9360 /* iWARP query QP ramrod data */
9361 struct iwarp_query_qp_ramrod_data {
9362 	struct regpair output_params_addr;
9363 };
9364 
9365 /* iWARP Ramrod Command IDs */
9366 enum iwarp_ramrod_cmd_id {
9367 	IWARP_RAMROD_CMD_ID_TCP_OFFLOAD = 13,
9368 	IWARP_RAMROD_CMD_ID_MPA_OFFLOAD,
9369 	IWARP_RAMROD_CMD_ID_MPA_OFFLOAD_SEND_RTR,
9370 	IWARP_RAMROD_CMD_ID_CREATE_QP,
9371 	IWARP_RAMROD_CMD_ID_QUERY_QP,
9372 	IWARP_RAMROD_CMD_ID_MODIFY_QP,
9373 	IWARP_RAMROD_CMD_ID_DESTROY_QP,
9374 	IWARP_RAMROD_CMD_ID_ABORT_TCP_OFFLOAD,
9375 	MAX_IWARP_RAMROD_CMD_ID
9376 };
9377 
9378 /* Per PF iWARP retransmit path statistics */
9379 struct iwarp_rxmit_stats_drv {
9380 	struct regpair tx_go_to_slow_start_event_cnt;
9381 	struct regpair tx_fast_retransmit_event_cnt;
9382 };
9383 
9384 /* iWARP and TCP connection offload params passed by driver to FW in iWARP
9385  * offload ramrod.
9386  */
9387 struct iwarp_tcp_offload_ramrod_data {
9388 	struct tcp_offload_params_opt2 tcp;
9389 	struct iwarp_offload_params iwarp;
9390 };
9391 
9392 /* iWARP MPA negotiation types */
9393 enum mpa_negotiation_mode {
9394 	MPA_NEGOTIATION_TYPE_BASIC = 1,
9395 	MPA_NEGOTIATION_TYPE_ENHANCED = 2,
9396 	MAX_MPA_NEGOTIATION_MODE
9397 };
9398 
9399 /* iWARP MPA Enhanced mode RTR types */
9400 enum mpa_rtr_type {
9401 	MPA_RTR_TYPE_NONE = 0,
9402 	MPA_RTR_TYPE_ZERO_SEND = 1,
9403 	MPA_RTR_TYPE_ZERO_WRITE = 2,
9404 	MPA_RTR_TYPE_ZERO_SEND_AND_WRITE = 3,
9405 	MPA_RTR_TYPE_ZERO_READ = 4,
9406 	MPA_RTR_TYPE_ZERO_SEND_AND_READ = 5,
9407 	MPA_RTR_TYPE_ZERO_WRITE_AND_READ = 6,
9408 	MPA_RTR_TYPE_ZERO_SEND_AND_WRITE_AND_READ = 7,
9409 	MAX_MPA_RTR_TYPE
9410 };
9411 
9412 /* unaligned opaque data received from LL2 */
9413 struct unaligned_opaque_data {
9414 	__le16 first_mpa_offset;
9415 	u8 tcp_payload_offset;
9416 	u8 flags;
9417 #define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_MASK	0x1
9418 #define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_SHIFT	0
9419 #define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_MASK		0x1
9420 #define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_SHIFT		1
9421 #define UNALIGNED_OPAQUE_DATA_RESERVED_MASK			0x3F
9422 #define UNALIGNED_OPAQUE_DATA_RESERVED_SHIFT			2
9423 	__le32 cid;
9424 };
9425 
9426 struct mstorm_iwarp_conn_ag_ctx {
9427 	u8 reserved;
9428 	u8 state;
9429 	u8 flags0;
9430 #define MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK		0x1
9431 #define MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT		0
9432 #define MSTORM_IWARP_CONN_AG_CTX_BIT1_MASK			0x1
9433 #define MSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT			1
9434 #define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_MASK	0x3
9435 #define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_SHIFT	2
9436 #define MSTORM_IWARP_CONN_AG_CTX_CF1_MASK			0x3
9437 #define MSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT			4
9438 #define MSTORM_IWARP_CONN_AG_CTX_CF2_MASK			0x3
9439 #define MSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT			6
9440 	u8 flags1;
9441 #define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_MASK	0x1
9442 #define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_SHIFT	0
9443 #define MSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK			0x1
9444 #define MSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT			1
9445 #define MSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK			0x1
9446 #define MSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT			2
9447 #define MSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK		0x1
9448 #define MSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT		3
9449 #define MSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK		0x1
9450 #define MSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT		4
9451 #define MSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK		0x1
9452 #define MSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT		5
9453 #define MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_MASK		0x1
9454 #define MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_SHIFT		6
9455 #define MSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK		0x1
9456 #define MSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT		7
9457 	__le16 rcq_cons;
9458 	__le16 rcq_cons_th;
9459 	__le32 reg0;
9460 	__le32 reg1;
9461 };
9462 
9463 struct ustorm_iwarp_conn_ag_ctx {
9464 	u8 reserved;
9465 	u8 byte1;
9466 	u8 flags0;
9467 #define USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
9468 #define USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
9469 #define USTORM_IWARP_CONN_AG_CTX_BIT1_MASK		0x1
9470 #define USTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT		1
9471 #define USTORM_IWARP_CONN_AG_CTX_CF0_MASK		0x3
9472 #define USTORM_IWARP_CONN_AG_CTX_CF0_SHIFT		2
9473 #define USTORM_IWARP_CONN_AG_CTX_CF1_MASK		0x3
9474 #define USTORM_IWARP_CONN_AG_CTX_CF1_SHIFT		4
9475 #define USTORM_IWARP_CONN_AG_CTX_CF2_MASK		0x3
9476 #define USTORM_IWARP_CONN_AG_CTX_CF2_SHIFT		6
9477 	u8 flags1;
9478 #define USTORM_IWARP_CONN_AG_CTX_CF3_MASK		0x3
9479 #define USTORM_IWARP_CONN_AG_CTX_CF3_SHIFT		0
9480 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_MASK	0x3
9481 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT	2
9482 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_MASK	0x3
9483 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_SHIFT	4
9484 #define USTORM_IWARP_CONN_AG_CTX_CF6_MASK		0x3
9485 #define USTORM_IWARP_CONN_AG_CTX_CF6_SHIFT		6
9486 	u8 flags2;
9487 #define USTORM_IWARP_CONN_AG_CTX_CF0EN_MASK			0x1
9488 #define USTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT			0
9489 #define USTORM_IWARP_CONN_AG_CTX_CF1EN_MASK			0x1
9490 #define USTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT			1
9491 #define USTORM_IWARP_CONN_AG_CTX_CF2EN_MASK			0x1
9492 #define USTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT			2
9493 #define USTORM_IWARP_CONN_AG_CTX_CF3EN_MASK			0x1
9494 #define USTORM_IWARP_CONN_AG_CTX_CF3EN_SHIFT			3
9495 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK	0x1
9496 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT	4
9497 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_MASK		0x1
9498 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT		5
9499 #define USTORM_IWARP_CONN_AG_CTX_CF6EN_MASK			0x1
9500 #define USTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT			6
9501 #define USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_MASK		0x1
9502 #define USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_SHIFT		7
9503 	u8 flags3;
9504 #define USTORM_IWARP_CONN_AG_CTX_CQ_EN_MASK		0x1
9505 #define USTORM_IWARP_CONN_AG_CTX_CQ_EN_SHIFT		0
9506 #define USTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK	0x1
9507 #define USTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT	1
9508 #define USTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK	0x1
9509 #define USTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT	2
9510 #define USTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK	0x1
9511 #define USTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT	3
9512 #define USTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK	0x1
9513 #define USTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT	4
9514 #define USTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK	0x1
9515 #define USTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT	5
9516 #define USTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK	0x1
9517 #define USTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT	6
9518 #define USTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK	0x1
9519 #define USTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT	7
9520 	u8 byte2;
9521 	u8 byte3;
9522 	__le16 word0;
9523 	__le16 word1;
9524 	__le32 cq_cons;
9525 	__le32 cq_se_prod;
9526 	__le32 cq_prod;
9527 	__le32 reg3;
9528 	__le16 word2;
9529 	__le16 word3;
9530 };
9531 
9532 struct ystorm_iwarp_conn_ag_ctx {
9533 	u8 byte0;
9534 	u8 byte1;
9535 	u8 flags0;
9536 #define YSTORM_IWARP_CONN_AG_CTX_BIT0_MASK	0x1
9537 #define YSTORM_IWARP_CONN_AG_CTX_BIT0_SHIFT	0
9538 #define YSTORM_IWARP_CONN_AG_CTX_BIT1_MASK	0x1
9539 #define YSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT	1
9540 #define YSTORM_IWARP_CONN_AG_CTX_CF0_MASK	0x3
9541 #define YSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT	2
9542 #define YSTORM_IWARP_CONN_AG_CTX_CF1_MASK	0x3
9543 #define YSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT	4
9544 #define YSTORM_IWARP_CONN_AG_CTX_CF2_MASK	0x3
9545 #define YSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT	6
9546 	u8 flags1;
9547 #define YSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK		0x1
9548 #define YSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT		0
9549 #define YSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK		0x1
9550 #define YSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT		1
9551 #define YSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK		0x1
9552 #define YSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT		2
9553 #define YSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK	0x1
9554 #define YSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT	3
9555 #define YSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK	0x1
9556 #define YSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT	4
9557 #define YSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK	0x1
9558 #define YSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT	5
9559 #define YSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK	0x1
9560 #define YSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT	6
9561 #define YSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK	0x1
9562 #define YSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT	7
9563 	u8 byte2;
9564 	u8 byte3;
9565 	__le16 word0;
9566 	__le32 reg0;
9567 	__le32 reg1;
9568 	__le16 word1;
9569 	__le16 word2;
9570 	__le16 word3;
9571 	__le16 word4;
9572 	__le32 reg2;
9573 	__le32 reg3;
9574 };
9575 
9576 /* The fcoe storm context of Ystorm */
9577 struct ystorm_fcoe_conn_st_ctx {
9578 	u8 func_mode;
9579 	u8 cos;
9580 	u8 conf_version;
9581 	u8 eth_hdr_size;
9582 	__le16 stat_ram_addr;
9583 	__le16 mtu;
9584 	__le16 max_fc_payload_len;
9585 	__le16 tx_max_fc_pay_len;
9586 	u8 fcp_cmd_size;
9587 	u8 fcp_rsp_size;
9588 	__le16 mss;
9589 	struct regpair reserved;
9590 	__le16 min_frame_size;
9591 	u8 protection_info_flags;
9592 #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK		0x1
9593 #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT	0
9594 #define YSTORM_FCOE_CONN_ST_CTX_VALID_MASK			0x1
9595 #define YSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT			1
9596 #define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_MASK			0x3F
9597 #define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_SHIFT			2
9598 	u8 dst_protection_per_mss;
9599 	u8 src_protection_per_mss;
9600 	u8 ptu_log_page_size;
9601 	u8 flags;
9602 #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK	0x1
9603 #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT	0
9604 #define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK	0x1
9605 #define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT	1
9606 #define YSTORM_FCOE_CONN_ST_CTX_RSRV_MASK		0x3F
9607 #define YSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT		2
9608 	u8 fcp_xfer_size;
9609 };
9610 
9611 /* FCoE 16-bits vlan structure */
9612 struct fcoe_vlan_fields {
9613 	__le16 fields;
9614 #define FCOE_VLAN_FIELDS_VID_MASK	0xFFF
9615 #define FCOE_VLAN_FIELDS_VID_SHIFT	0
9616 #define FCOE_VLAN_FIELDS_CLI_MASK	0x1
9617 #define FCOE_VLAN_FIELDS_CLI_SHIFT	12
9618 #define FCOE_VLAN_FIELDS_PRI_MASK	0x7
9619 #define FCOE_VLAN_FIELDS_PRI_SHIFT	13
9620 };
9621 
9622 /* FCoE 16-bits vlan union */
9623 union fcoe_vlan_field_union {
9624 	struct fcoe_vlan_fields fields;
9625 	__le16 val;
9626 };
9627 
9628 /* FCoE 16-bits vlan, vif union */
9629 union fcoe_vlan_vif_field_union {
9630 	union fcoe_vlan_field_union vlan;
9631 	__le16 vif;
9632 };
9633 
9634 /* Ethernet context section */
9635 struct pstorm_fcoe_eth_context_section {
9636 	u8 remote_addr_3;
9637 	u8 remote_addr_2;
9638 	u8 remote_addr_1;
9639 	u8 remote_addr_0;
9640 	u8 local_addr_1;
9641 	u8 local_addr_0;
9642 	u8 remote_addr_5;
9643 	u8 remote_addr_4;
9644 	u8 local_addr_5;
9645 	u8 local_addr_4;
9646 	u8 local_addr_3;
9647 	u8 local_addr_2;
9648 	union fcoe_vlan_vif_field_union vif_outer_vlan;
9649 	__le16 vif_outer_eth_type;
9650 	union fcoe_vlan_vif_field_union inner_vlan;
9651 	__le16 inner_eth_type;
9652 };
9653 
9654 /* The fcoe storm context of Pstorm */
9655 struct pstorm_fcoe_conn_st_ctx {
9656 	u8 func_mode;
9657 	u8 cos;
9658 	u8 conf_version;
9659 	u8 rsrv;
9660 	__le16 stat_ram_addr;
9661 	__le16 mss;
9662 	struct regpair abts_cleanup_addr;
9663 	struct pstorm_fcoe_eth_context_section eth;
9664 	u8 sid_2;
9665 	u8 sid_1;
9666 	u8 sid_0;
9667 	u8 flags;
9668 #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_MASK			0x1
9669 #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_SHIFT		0
9670 #define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_MASK		0x1
9671 #define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_SHIFT	1
9672 #define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK		0x1
9673 #define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT		2
9674 #define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK		0x1
9675 #define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT		3
9676 #define PSTORM_FCOE_CONN_ST_CTX_SINGLE_VLAN_FLAG_MASK		0x1
9677 #define PSTORM_FCOE_CONN_ST_CTX_SINGLE_VLAN_FLAG_SHIFT		4
9678 #define PSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK			0x7
9679 #define PSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT			5
9680 	u8 did_2;
9681 	u8 did_1;
9682 	u8 did_0;
9683 	u8 src_mac_index;
9684 	__le16 rec_rr_tov_val;
9685 	u8 q_relative_offset;
9686 	u8 reserved1;
9687 };
9688 
9689 /* The fcoe storm context of Xstorm */
9690 struct xstorm_fcoe_conn_st_ctx {
9691 	u8 func_mode;
9692 	u8 src_mac_index;
9693 	u8 conf_version;
9694 	u8 cached_wqes_avail;
9695 	__le16 stat_ram_addr;
9696 	u8 flags;
9697 #define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_MASK		0x1
9698 #define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_SHIFT		0
9699 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK		0x1
9700 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT		1
9701 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_MASK	0x1
9702 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_SHIFT	2
9703 #define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_MASK		0x3
9704 #define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_SHIFT	3
9705 #define XSTORM_FCOE_CONN_ST_CTX_RSRV_MASK			0x7
9706 #define XSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT			5
9707 	u8 cached_wqes_offset;
9708 	u8 reserved2;
9709 	u8 eth_hdr_size;
9710 	u8 seq_id;
9711 	u8 max_conc_seqs;
9712 	__le16 num_pages_in_pbl;
9713 	__le16 reserved;
9714 	struct regpair sq_pbl_addr;
9715 	struct regpair sq_curr_page_addr;
9716 	struct regpair sq_next_page_addr;
9717 	struct regpair xferq_pbl_addr;
9718 	struct regpair xferq_curr_page_addr;
9719 	struct regpair xferq_next_page_addr;
9720 	struct regpair respq_pbl_addr;
9721 	struct regpair respq_curr_page_addr;
9722 	struct regpair respq_next_page_addr;
9723 	__le16 mtu;
9724 	__le16 tx_max_fc_pay_len;
9725 	__le16 max_fc_payload_len;
9726 	__le16 min_frame_size;
9727 	__le16 sq_pbl_next_index;
9728 	__le16 respq_pbl_next_index;
9729 	u8 fcp_cmd_byte_credit;
9730 	u8 fcp_rsp_byte_credit;
9731 	__le16 protection_info;
9732 #define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_MASK		0x1
9733 #define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_SHIFT		0
9734 #define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK		0x1
9735 #define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT	1
9736 #define XSTORM_FCOE_CONN_ST_CTX_VALID_MASK			0x1
9737 #define XSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT			2
9738 #define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_MASK		0x1
9739 #define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_SHIFT	3
9740 #define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_MASK			0xF
9741 #define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_SHIFT			4
9742 #define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_MASK	0xFF
9743 #define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_SHIFT	8
9744 	__le16 xferq_pbl_next_index;
9745 	__le16 page_size;
9746 	u8 mid_seq;
9747 	u8 fcp_xfer_byte_credit;
9748 	u8 reserved1[2];
9749 	struct fcoe_wqe cached_wqes[16];
9750 };
9751 
9752 struct xstorm_fcoe_conn_ag_ctx {
9753 	u8 reserved0;
9754 	u8 state;
9755 	u8 flags0;
9756 #define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
9757 #define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
9758 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED1_MASK	0x1
9759 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED1_SHIFT	1
9760 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED2_MASK	0x1
9761 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED2_SHIFT	2
9762 #define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_MASK	0x1
9763 #define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT	3
9764 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED3_MASK	0x1
9765 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED3_SHIFT	4
9766 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED4_MASK	0x1
9767 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED4_SHIFT	5
9768 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED5_MASK	0x1
9769 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED5_SHIFT	6
9770 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED6_MASK	0x1
9771 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED6_SHIFT	7
9772 	u8 flags1;
9773 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED7_MASK	0x1
9774 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED7_SHIFT	0
9775 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED8_MASK	0x1
9776 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED8_SHIFT	1
9777 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED9_MASK	0x1
9778 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED9_SHIFT	2
9779 #define XSTORM_FCOE_CONN_AG_CTX_BIT11_MASK		0x1
9780 #define XSTORM_FCOE_CONN_AG_CTX_BIT11_SHIFT		3
9781 #define XSTORM_FCOE_CONN_AG_CTX_BIT12_MASK		0x1
9782 #define XSTORM_FCOE_CONN_AG_CTX_BIT12_SHIFT		4
9783 #define XSTORM_FCOE_CONN_AG_CTX_BIT13_MASK		0x1
9784 #define XSTORM_FCOE_CONN_AG_CTX_BIT13_SHIFT		5
9785 #define XSTORM_FCOE_CONN_AG_CTX_BIT14_MASK		0x1
9786 #define XSTORM_FCOE_CONN_AG_CTX_BIT14_SHIFT		6
9787 #define XSTORM_FCOE_CONN_AG_CTX_BIT15_MASK		0x1
9788 #define XSTORM_FCOE_CONN_AG_CTX_BIT15_SHIFT		7
9789 	u8 flags2;
9790 #define XSTORM_FCOE_CONN_AG_CTX_CF0_MASK	0x3
9791 #define XSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT	0
9792 #define XSTORM_FCOE_CONN_AG_CTX_CF1_MASK	0x3
9793 #define XSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT	2
9794 #define XSTORM_FCOE_CONN_AG_CTX_CF2_MASK	0x3
9795 #define XSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT	4
9796 #define XSTORM_FCOE_CONN_AG_CTX_CF3_MASK	0x3
9797 #define XSTORM_FCOE_CONN_AG_CTX_CF3_SHIFT	6
9798 	u8 flags3;
9799 #define XSTORM_FCOE_CONN_AG_CTX_CF4_MASK	0x3
9800 #define XSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT	0
9801 #define XSTORM_FCOE_CONN_AG_CTX_CF5_MASK	0x3
9802 #define XSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT	2
9803 #define XSTORM_FCOE_CONN_AG_CTX_CF6_MASK	0x3
9804 #define XSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT	4
9805 #define XSTORM_FCOE_CONN_AG_CTX_CF7_MASK	0x3
9806 #define XSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT	6
9807 	u8 flags4;
9808 #define XSTORM_FCOE_CONN_AG_CTX_CF8_MASK	0x3
9809 #define XSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT	0
9810 #define XSTORM_FCOE_CONN_AG_CTX_CF9_MASK	0x3
9811 #define XSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT	2
9812 #define XSTORM_FCOE_CONN_AG_CTX_CF10_MASK	0x3
9813 #define XSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT	4
9814 #define XSTORM_FCOE_CONN_AG_CTX_CF11_MASK	0x3
9815 #define XSTORM_FCOE_CONN_AG_CTX_CF11_SHIFT	6
9816 	u8 flags5;
9817 #define XSTORM_FCOE_CONN_AG_CTX_CF12_MASK	0x3
9818 #define XSTORM_FCOE_CONN_AG_CTX_CF12_SHIFT	0
9819 #define XSTORM_FCOE_CONN_AG_CTX_CF13_MASK	0x3
9820 #define XSTORM_FCOE_CONN_AG_CTX_CF13_SHIFT	2
9821 #define XSTORM_FCOE_CONN_AG_CTX_CF14_MASK	0x3
9822 #define XSTORM_FCOE_CONN_AG_CTX_CF14_SHIFT	4
9823 #define XSTORM_FCOE_CONN_AG_CTX_CF15_MASK	0x3
9824 #define XSTORM_FCOE_CONN_AG_CTX_CF15_SHIFT	6
9825 	u8 flags6;
9826 #define XSTORM_FCOE_CONN_AG_CTX_CF16_MASK	0x3
9827 #define XSTORM_FCOE_CONN_AG_CTX_CF16_SHIFT	0
9828 #define XSTORM_FCOE_CONN_AG_CTX_CF17_MASK	0x3
9829 #define XSTORM_FCOE_CONN_AG_CTX_CF17_SHIFT	2
9830 #define XSTORM_FCOE_CONN_AG_CTX_CF18_MASK	0x3
9831 #define XSTORM_FCOE_CONN_AG_CTX_CF18_SHIFT	4
9832 #define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_MASK	0x3
9833 #define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_SHIFT	6
9834 	u8 flags7;
9835 #define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_MASK	0x3
9836 #define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_SHIFT	0
9837 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED10_MASK	0x3
9838 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED10_SHIFT	2
9839 #define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_MASK	0x3
9840 #define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_SHIFT	4
9841 #define XSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK		0x1
9842 #define XSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT		6
9843 #define XSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK		0x1
9844 #define XSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT		7
9845 	u8 flags8;
9846 #define XSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK	0x1
9847 #define XSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT	0
9848 #define XSTORM_FCOE_CONN_AG_CTX_CF3EN_MASK	0x1
9849 #define XSTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT	1
9850 #define XSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK	0x1
9851 #define XSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT	2
9852 #define XSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK	0x1
9853 #define XSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT	3
9854 #define XSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK	0x1
9855 #define XSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT	4
9856 #define XSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK	0x1
9857 #define XSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT	5
9858 #define XSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK	0x1
9859 #define XSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT	6
9860 #define XSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK	0x1
9861 #define XSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT	7
9862 	u8 flags9;
9863 #define XSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK	0x1
9864 #define XSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT	0
9865 #define XSTORM_FCOE_CONN_AG_CTX_CF11EN_MASK	0x1
9866 #define XSTORM_FCOE_CONN_AG_CTX_CF11EN_SHIFT	1
9867 #define XSTORM_FCOE_CONN_AG_CTX_CF12EN_MASK	0x1
9868 #define XSTORM_FCOE_CONN_AG_CTX_CF12EN_SHIFT	2
9869 #define XSTORM_FCOE_CONN_AG_CTX_CF13EN_MASK	0x1
9870 #define XSTORM_FCOE_CONN_AG_CTX_CF13EN_SHIFT	3
9871 #define XSTORM_FCOE_CONN_AG_CTX_CF14EN_MASK	0x1
9872 #define XSTORM_FCOE_CONN_AG_CTX_CF14EN_SHIFT	4
9873 #define XSTORM_FCOE_CONN_AG_CTX_CF15EN_MASK	0x1
9874 #define XSTORM_FCOE_CONN_AG_CTX_CF15EN_SHIFT	5
9875 #define XSTORM_FCOE_CONN_AG_CTX_CF16EN_MASK	0x1
9876 #define XSTORM_FCOE_CONN_AG_CTX_CF16EN_SHIFT	6
9877 #define XSTORM_FCOE_CONN_AG_CTX_CF17EN_MASK	0x1
9878 #define XSTORM_FCOE_CONN_AG_CTX_CF17EN_SHIFT	7
9879 	u8 flags10;
9880 #define XSTORM_FCOE_CONN_AG_CTX_CF18EN_MASK		0x1
9881 #define XSTORM_FCOE_CONN_AG_CTX_CF18EN_SHIFT		0
9882 #define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_MASK	0x1
9883 #define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_SHIFT	1
9884 #define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK	0x1
9885 #define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT	2
9886 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED11_MASK	0x1
9887 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED11_SHIFT	3
9888 #define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_MASK	0x1
9889 #define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT	4
9890 #define XSTORM_FCOE_CONN_AG_CTX_CF23EN_MASK		0x1
9891 #define XSTORM_FCOE_CONN_AG_CTX_CF23EN_SHIFT		5
9892 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED12_MASK	0x1
9893 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED12_SHIFT	6
9894 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED13_MASK	0x1
9895 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED13_SHIFT	7
9896 	u8 flags11;
9897 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED14_MASK		0x1
9898 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED14_SHIFT		0
9899 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED15_MASK		0x1
9900 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED15_SHIFT		1
9901 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED16_MASK		0x1
9902 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED16_SHIFT		2
9903 #define XSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK			0x1
9904 #define XSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT		3
9905 #define XSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK			0x1
9906 #define XSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT		4
9907 #define XSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK			0x1
9908 #define XSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT		5
9909 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_MASK		0x1
9910 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_SHIFT		6
9911 #define XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_MASK	0x1
9912 #define XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_SHIFT	7
9913 	u8 flags12;
9914 #define XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_MASK	0x1
9915 #define XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_SHIFT	0
9916 #define XSTORM_FCOE_CONN_AG_CTX_RULE11EN_MASK	0x1
9917 #define XSTORM_FCOE_CONN_AG_CTX_RULE11EN_SHIFT	1
9918 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_MASK	0x1
9919 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_SHIFT	2
9920 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_MASK	0x1
9921 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_SHIFT	3
9922 #define XSTORM_FCOE_CONN_AG_CTX_RULE14EN_MASK	0x1
9923 #define XSTORM_FCOE_CONN_AG_CTX_RULE14EN_SHIFT	4
9924 #define XSTORM_FCOE_CONN_AG_CTX_RULE15EN_MASK	0x1
9925 #define XSTORM_FCOE_CONN_AG_CTX_RULE15EN_SHIFT	5
9926 #define XSTORM_FCOE_CONN_AG_CTX_RULE16EN_MASK	0x1
9927 #define XSTORM_FCOE_CONN_AG_CTX_RULE16EN_SHIFT	6
9928 #define XSTORM_FCOE_CONN_AG_CTX_RULE17EN_MASK	0x1
9929 #define XSTORM_FCOE_CONN_AG_CTX_RULE17EN_SHIFT	7
9930 	u8 flags13;
9931 #define XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_MASK	0x1
9932 #define XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_SHIFT	0
9933 #define XSTORM_FCOE_CONN_AG_CTX_RULE19EN_MASK		0x1
9934 #define XSTORM_FCOE_CONN_AG_CTX_RULE19EN_SHIFT		1
9935 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_MASK		0x1
9936 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_SHIFT		2
9937 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_MASK		0x1
9938 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_SHIFT		3
9939 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_MASK		0x1
9940 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_SHIFT		4
9941 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_MASK		0x1
9942 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_SHIFT		5
9943 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_MASK		0x1
9944 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_SHIFT		6
9945 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_MASK		0x1
9946 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_SHIFT		7
9947 	u8 flags14;
9948 #define XSTORM_FCOE_CONN_AG_CTX_BIT16_MASK	0x1
9949 #define XSTORM_FCOE_CONN_AG_CTX_BIT16_SHIFT	0
9950 #define XSTORM_FCOE_CONN_AG_CTX_BIT17_MASK	0x1
9951 #define XSTORM_FCOE_CONN_AG_CTX_BIT17_SHIFT	1
9952 #define XSTORM_FCOE_CONN_AG_CTX_BIT18_MASK	0x1
9953 #define XSTORM_FCOE_CONN_AG_CTX_BIT18_SHIFT	2
9954 #define XSTORM_FCOE_CONN_AG_CTX_BIT19_MASK	0x1
9955 #define XSTORM_FCOE_CONN_AG_CTX_BIT19_SHIFT	3
9956 #define XSTORM_FCOE_CONN_AG_CTX_BIT20_MASK	0x1
9957 #define XSTORM_FCOE_CONN_AG_CTX_BIT20_SHIFT	4
9958 #define XSTORM_FCOE_CONN_AG_CTX_BIT21_MASK	0x1
9959 #define XSTORM_FCOE_CONN_AG_CTX_BIT21_SHIFT	5
9960 #define XSTORM_FCOE_CONN_AG_CTX_CF23_MASK	0x3
9961 #define XSTORM_FCOE_CONN_AG_CTX_CF23_SHIFT	6
9962 	u8 byte2;
9963 	__le16 physical_q0;
9964 	__le16 word1;
9965 	__le16 word2;
9966 	__le16 sq_cons;
9967 	__le16 sq_prod;
9968 	__le16 xferq_prod;
9969 	__le16 xferq_cons;
9970 	u8 byte3;
9971 	u8 byte4;
9972 	u8 byte5;
9973 	u8 byte6;
9974 	__le32 remain_io;
9975 	__le32 reg1;
9976 	__le32 reg2;
9977 	__le32 reg3;
9978 	__le32 reg4;
9979 	__le32 reg5;
9980 	__le32 reg6;
9981 	__le16 respq_prod;
9982 	__le16 respq_cons;
9983 	__le16 word9;
9984 	__le16 word10;
9985 	__le32 reg7;
9986 	__le32 reg8;
9987 };
9988 
9989 /* The fcoe storm context of Ustorm */
9990 struct ustorm_fcoe_conn_st_ctx {
9991 	struct regpair respq_pbl_addr;
9992 	__le16 num_pages_in_pbl;
9993 	u8 ptu_log_page_size;
9994 	u8 log_page_size;
9995 	__le16 respq_prod;
9996 	u8 reserved[2];
9997 };
9998 
9999 struct tstorm_fcoe_conn_ag_ctx {
10000 	u8 reserved0;
10001 	u8 state;
10002 	u8 flags0;
10003 #define TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
10004 #define TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
10005 #define TSTORM_FCOE_CONN_AG_CTX_BIT1_MASK		0x1
10006 #define TSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT		1
10007 #define TSTORM_FCOE_CONN_AG_CTX_BIT2_MASK		0x1
10008 #define TSTORM_FCOE_CONN_AG_CTX_BIT2_SHIFT		2
10009 #define TSTORM_FCOE_CONN_AG_CTX_BIT3_MASK		0x1
10010 #define TSTORM_FCOE_CONN_AG_CTX_BIT3_SHIFT		3
10011 #define TSTORM_FCOE_CONN_AG_CTX_BIT4_MASK		0x1
10012 #define TSTORM_FCOE_CONN_AG_CTX_BIT4_SHIFT		4
10013 #define TSTORM_FCOE_CONN_AG_CTX_BIT5_MASK		0x1
10014 #define TSTORM_FCOE_CONN_AG_CTX_BIT5_SHIFT		5
10015 #define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_MASK	0x3
10016 #define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_SHIFT	6
10017 	u8 flags1;
10018 #define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_MASK		0x3
10019 #define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT		0
10020 #define TSTORM_FCOE_CONN_AG_CTX_CF2_MASK			0x3
10021 #define TSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT			2
10022 #define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK	0x3
10023 #define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT	4
10024 #define TSTORM_FCOE_CONN_AG_CTX_CF4_MASK			0x3
10025 #define TSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT			6
10026 	u8 flags2;
10027 #define TSTORM_FCOE_CONN_AG_CTX_CF5_MASK	0x3
10028 #define TSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT	0
10029 #define TSTORM_FCOE_CONN_AG_CTX_CF6_MASK	0x3
10030 #define TSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT	2
10031 #define TSTORM_FCOE_CONN_AG_CTX_CF7_MASK	0x3
10032 #define TSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT	4
10033 #define TSTORM_FCOE_CONN_AG_CTX_CF8_MASK	0x3
10034 #define TSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT	6
10035 	u8 flags3;
10036 #define TSTORM_FCOE_CONN_AG_CTX_CF9_MASK			0x3
10037 #define TSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT			0
10038 #define TSTORM_FCOE_CONN_AG_CTX_CF10_MASK			0x3
10039 #define TSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT			2
10040 #define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_MASK	0x1
10041 #define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_SHIFT	4
10042 #define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK		0x1
10043 #define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT		5
10044 #define TSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK			0x1
10045 #define TSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT			6
10046 #define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK	0x1
10047 #define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT	7
10048 	u8 flags4;
10049 #define TSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK		0x1
10050 #define TSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT		0
10051 #define TSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK		0x1
10052 #define TSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT		1
10053 #define TSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK		0x1
10054 #define TSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT		2
10055 #define TSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK		0x1
10056 #define TSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT		3
10057 #define TSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK		0x1
10058 #define TSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT		4
10059 #define TSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK		0x1
10060 #define TSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT		5
10061 #define TSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK		0x1
10062 #define TSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT		6
10063 #define TSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK		0x1
10064 #define TSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT	7
10065 	u8 flags5;
10066 #define TSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK		0x1
10067 #define TSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT	0
10068 #define TSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK		0x1
10069 #define TSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT	1
10070 #define TSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK		0x1
10071 #define TSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT	2
10072 #define TSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK		0x1
10073 #define TSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT	3
10074 #define TSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK		0x1
10075 #define TSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT	4
10076 #define TSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK		0x1
10077 #define TSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT	5
10078 #define TSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK		0x1
10079 #define TSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT	6
10080 #define TSTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK		0x1
10081 #define TSTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT	7
10082 	__le32 reg0;
10083 	__le32 reg1;
10084 };
10085 
10086 struct ustorm_fcoe_conn_ag_ctx {
10087 	u8 byte0;
10088 	u8 byte1;
10089 	u8 flags0;
10090 #define USTORM_FCOE_CONN_AG_CTX_BIT0_MASK	0x1
10091 #define USTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT	0
10092 #define USTORM_FCOE_CONN_AG_CTX_BIT1_MASK	0x1
10093 #define USTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT	1
10094 #define USTORM_FCOE_CONN_AG_CTX_CF0_MASK	0x3
10095 #define USTORM_FCOE_CONN_AG_CTX_CF0_SHIFT	2
10096 #define USTORM_FCOE_CONN_AG_CTX_CF1_MASK	0x3
10097 #define USTORM_FCOE_CONN_AG_CTX_CF1_SHIFT	4
10098 #define USTORM_FCOE_CONN_AG_CTX_CF2_MASK	0x3
10099 #define USTORM_FCOE_CONN_AG_CTX_CF2_SHIFT	6
10100 	u8 flags1;
10101 #define USTORM_FCOE_CONN_AG_CTX_CF3_MASK	0x3
10102 #define USTORM_FCOE_CONN_AG_CTX_CF3_SHIFT	0
10103 #define USTORM_FCOE_CONN_AG_CTX_CF4_MASK	0x3
10104 #define USTORM_FCOE_CONN_AG_CTX_CF4_SHIFT	2
10105 #define USTORM_FCOE_CONN_AG_CTX_CF5_MASK	0x3
10106 #define USTORM_FCOE_CONN_AG_CTX_CF5_SHIFT	4
10107 #define USTORM_FCOE_CONN_AG_CTX_CF6_MASK	0x3
10108 #define USTORM_FCOE_CONN_AG_CTX_CF6_SHIFT	6
10109 	u8 flags2;
10110 #define USTORM_FCOE_CONN_AG_CTX_CF0EN_MASK		0x1
10111 #define USTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT		0
10112 #define USTORM_FCOE_CONN_AG_CTX_CF1EN_MASK		0x1
10113 #define USTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT		1
10114 #define USTORM_FCOE_CONN_AG_CTX_CF2EN_MASK		0x1
10115 #define USTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT		2
10116 #define USTORM_FCOE_CONN_AG_CTX_CF3EN_MASK		0x1
10117 #define USTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT		3
10118 #define USTORM_FCOE_CONN_AG_CTX_CF4EN_MASK		0x1
10119 #define USTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT		4
10120 #define USTORM_FCOE_CONN_AG_CTX_CF5EN_MASK		0x1
10121 #define USTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT		5
10122 #define USTORM_FCOE_CONN_AG_CTX_CF6EN_MASK		0x1
10123 #define USTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT		6
10124 #define USTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK		0x1
10125 #define USTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT	7
10126 	u8 flags3;
10127 #define USTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK		0x1
10128 #define USTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT	0
10129 #define USTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK		0x1
10130 #define USTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT	1
10131 #define USTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK		0x1
10132 #define USTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT	2
10133 #define USTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK		0x1
10134 #define USTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT	3
10135 #define USTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK		0x1
10136 #define USTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT	4
10137 #define USTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK		0x1
10138 #define USTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT	5
10139 #define USTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK		0x1
10140 #define USTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT	6
10141 #define USTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK		0x1
10142 #define USTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT	7
10143 	u8 byte2;
10144 	u8 byte3;
10145 	__le16 word0;
10146 	__le16 word1;
10147 	__le32 reg0;
10148 	__le32 reg1;
10149 	__le32 reg2;
10150 	__le32 reg3;
10151 	__le16 word2;
10152 	__le16 word3;
10153 };
10154 
10155 /* The fcoe storm context of Tstorm */
10156 struct tstorm_fcoe_conn_st_ctx {
10157 	__le16 stat_ram_addr;
10158 	__le16 rx_max_fc_payload_len;
10159 	__le16 e_d_tov_val;
10160 	u8 flags;
10161 #define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_MASK	0x1
10162 #define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_SHIFT	0
10163 #define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_MASK	0x1
10164 #define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_SHIFT	1
10165 #define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_MASK		0x3F
10166 #define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_SHIFT		2
10167 	u8 timers_cleanup_invocation_cnt;
10168 	__le32 reserved1[2];
10169 	__le32 dst_mac_address_bytes_0_to_3;
10170 	__le16 dst_mac_address_bytes_4_to_5;
10171 	__le16 ramrod_echo;
10172 	u8 flags1;
10173 #define TSTORM_FCOE_CONN_ST_CTX_MODE_MASK	0x3
10174 #define TSTORM_FCOE_CONN_ST_CTX_MODE_SHIFT	0
10175 #define TSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK	0x3F
10176 #define TSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT	2
10177 	u8 cq_relative_offset;
10178 	u8 cmdq_relative_offset;
10179 	u8 bdq_resource_id;
10180 	u8 reserved0[4];
10181 };
10182 
10183 struct mstorm_fcoe_conn_ag_ctx {
10184 	u8 byte0;
10185 	u8 byte1;
10186 	u8 flags0;
10187 #define MSTORM_FCOE_CONN_AG_CTX_BIT0_MASK	0x1
10188 #define MSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT	0
10189 #define MSTORM_FCOE_CONN_AG_CTX_BIT1_MASK	0x1
10190 #define MSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT	1
10191 #define MSTORM_FCOE_CONN_AG_CTX_CF0_MASK	0x3
10192 #define MSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT	2
10193 #define MSTORM_FCOE_CONN_AG_CTX_CF1_MASK	0x3
10194 #define MSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT	4
10195 #define MSTORM_FCOE_CONN_AG_CTX_CF2_MASK	0x3
10196 #define MSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT	6
10197 	u8 flags1;
10198 #define MSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK		0x1
10199 #define MSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT		0
10200 #define MSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK		0x1
10201 #define MSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT		1
10202 #define MSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK		0x1
10203 #define MSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT		2
10204 #define MSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK		0x1
10205 #define MSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT	3
10206 #define MSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK		0x1
10207 #define MSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT	4
10208 #define MSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK		0x1
10209 #define MSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT	5
10210 #define MSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK		0x1
10211 #define MSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT	6
10212 #define MSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK		0x1
10213 #define MSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT	7
10214 	__le16 word0;
10215 	__le16 word1;
10216 	__le32 reg0;
10217 	__le32 reg1;
10218 };
10219 
10220 /* Fast path part of the fcoe storm context of Mstorm */
10221 struct fcoe_mstorm_fcoe_conn_st_ctx_fp {
10222 	__le16 xfer_prod;
10223 	u8 num_cqs;
10224 	u8 reserved1;
10225 	u8 protection_info;
10226 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_MASK  0x1
10227 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_SHIFT 0
10228 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_MASK               0x1
10229 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_SHIFT              1
10230 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_MASK           0x3F
10231 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_SHIFT          2
10232 	u8 q_relative_offset;
10233 	u8 reserved2[2];
10234 };
10235 
10236 /* Non fast path part of the fcoe storm context of Mstorm */
10237 struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp {
10238 	__le16 conn_id;
10239 	__le16 stat_ram_addr;
10240 	__le16 num_pages_in_pbl;
10241 	u8 ptu_log_page_size;
10242 	u8 log_page_size;
10243 	__le16 unsolicited_cq_count;
10244 	__le16 cmdq_count;
10245 	u8 bdq_resource_id;
10246 	u8 reserved0[3];
10247 	struct regpair xferq_pbl_addr;
10248 	struct regpair reserved1;
10249 	struct regpair reserved2[3];
10250 };
10251 
10252 /* The fcoe storm context of Mstorm */
10253 struct mstorm_fcoe_conn_st_ctx {
10254 	struct fcoe_mstorm_fcoe_conn_st_ctx_fp fp;
10255 	struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp non_fp;
10256 };
10257 
10258 /* fcoe connection context */
10259 struct fcoe_conn_context {
10260 	struct ystorm_fcoe_conn_st_ctx ystorm_st_context;
10261 	struct pstorm_fcoe_conn_st_ctx pstorm_st_context;
10262 	struct regpair pstorm_st_padding[2];
10263 	struct xstorm_fcoe_conn_st_ctx xstorm_st_context;
10264 	struct xstorm_fcoe_conn_ag_ctx xstorm_ag_context;
10265 	struct regpair xstorm_ag_padding[6];
10266 	struct ustorm_fcoe_conn_st_ctx ustorm_st_context;
10267 	struct regpair ustorm_st_padding[2];
10268 	struct tstorm_fcoe_conn_ag_ctx tstorm_ag_context;
10269 	struct regpair tstorm_ag_padding[2];
10270 	struct timers_context timer_context;
10271 	struct ustorm_fcoe_conn_ag_ctx ustorm_ag_context;
10272 	struct tstorm_fcoe_conn_st_ctx tstorm_st_context;
10273 	struct mstorm_fcoe_conn_ag_ctx mstorm_ag_context;
10274 	struct mstorm_fcoe_conn_st_ctx mstorm_st_context;
10275 };
10276 
10277 /* FCoE connection offload params passed by driver to FW in FCoE offload
10278  * ramrod.
10279  */
10280 struct fcoe_conn_offload_ramrod_params {
10281 	struct fcoe_conn_offload_ramrod_data offload_ramrod_data;
10282 };
10283 
10284 /* FCoE connection terminate params passed by driver to FW in FCoE terminate
10285  * conn ramrod.
10286  */
10287 struct fcoe_conn_terminate_ramrod_params {
10288 	struct fcoe_conn_terminate_ramrod_data terminate_ramrod_data;
10289 };
10290 
10291 /* FCoE event type */
10292 enum fcoe_event_type {
10293 	FCOE_EVENT_INIT_FUNC,
10294 	FCOE_EVENT_DESTROY_FUNC,
10295 	FCOE_EVENT_STAT_FUNC,
10296 	FCOE_EVENT_OFFLOAD_CONN,
10297 	FCOE_EVENT_TERMINATE_CONN,
10298 	FCOE_EVENT_ERROR,
10299 	MAX_FCOE_EVENT_TYPE
10300 };
10301 
10302 /* FCoE init params passed by driver to FW in FCoE init ramrod */
10303 struct fcoe_init_ramrod_params {
10304 	struct fcoe_init_func_ramrod_data init_ramrod_data;
10305 };
10306 
10307 /* FCoE ramrod Command IDs */
10308 enum fcoe_ramrod_cmd_id {
10309 	FCOE_RAMROD_CMD_ID_INIT_FUNC,
10310 	FCOE_RAMROD_CMD_ID_DESTROY_FUNC,
10311 	FCOE_RAMROD_CMD_ID_STAT_FUNC,
10312 	FCOE_RAMROD_CMD_ID_OFFLOAD_CONN,
10313 	FCOE_RAMROD_CMD_ID_TERMINATE_CONN,
10314 	MAX_FCOE_RAMROD_CMD_ID
10315 };
10316 
10317 /* FCoE statistics params buffer passed by driver to FW in FCoE statistics
10318  * ramrod.
10319  */
10320 struct fcoe_stat_ramrod_params {
10321 	struct fcoe_stat_ramrod_data stat_ramrod_data;
10322 };
10323 
10324 struct ystorm_fcoe_conn_ag_ctx {
10325 	u8 byte0;
10326 	u8 byte1;
10327 	u8 flags0;
10328 #define YSTORM_FCOE_CONN_AG_CTX_BIT0_MASK	0x1
10329 #define YSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT	0
10330 #define YSTORM_FCOE_CONN_AG_CTX_BIT1_MASK	0x1
10331 #define YSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT	1
10332 #define YSTORM_FCOE_CONN_AG_CTX_CF0_MASK	0x3
10333 #define YSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT	2
10334 #define YSTORM_FCOE_CONN_AG_CTX_CF1_MASK	0x3
10335 #define YSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT	4
10336 #define YSTORM_FCOE_CONN_AG_CTX_CF2_MASK	0x3
10337 #define YSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT	6
10338 	u8 flags1;
10339 #define YSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK		0x1
10340 #define YSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT		0
10341 #define YSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK		0x1
10342 #define YSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT		1
10343 #define YSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK		0x1
10344 #define YSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT		2
10345 #define YSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK		0x1
10346 #define YSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT	3
10347 #define YSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK		0x1
10348 #define YSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT	4
10349 #define YSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK		0x1
10350 #define YSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT	5
10351 #define YSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK		0x1
10352 #define YSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT	6
10353 #define YSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK		0x1
10354 #define YSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT	7
10355 	u8 byte2;
10356 	u8 byte3;
10357 	__le16 word0;
10358 	__le32 reg0;
10359 	__le32 reg1;
10360 	__le16 word1;
10361 	__le16 word2;
10362 	__le16 word3;
10363 	__le16 word4;
10364 	__le32 reg2;
10365 	__le32 reg3;
10366 };
10367 
10368 /* The iscsi storm connection context of Ystorm */
10369 struct ystorm_iscsi_conn_st_ctx {
10370 	__le32 reserved[8];
10371 };
10372 
10373 /* Combined iSCSI and TCP storm connection of Pstorm */
10374 struct pstorm_iscsi_tcp_conn_st_ctx {
10375 	__le32 tcp[32];
10376 	__le32 iscsi[4];
10377 };
10378 
10379 /* The combined tcp and iscsi storm context of Xstorm */
10380 struct xstorm_iscsi_tcp_conn_st_ctx {
10381 	__le32 reserved_tcp[4];
10382 	__le32 reserved_iscsi[44];
10383 };
10384 
10385 struct xstorm_iscsi_conn_ag_ctx {
10386 	u8 cdu_validation;
10387 	u8 state;
10388 	u8 flags0;
10389 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
10390 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
10391 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_MASK	0x1
10392 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_SHIFT	1
10393 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_MASK	0x1
10394 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_SHIFT	2
10395 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_MASK	0x1
10396 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_SHIFT	3
10397 #define XSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK		0x1
10398 #define XSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT		4
10399 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_MASK	0x1
10400 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_SHIFT	5
10401 #define XSTORM_ISCSI_CONN_AG_CTX_BIT6_MASK		0x1
10402 #define XSTORM_ISCSI_CONN_AG_CTX_BIT6_SHIFT		6
10403 #define XSTORM_ISCSI_CONN_AG_CTX_BIT7_MASK		0x1
10404 #define XSTORM_ISCSI_CONN_AG_CTX_BIT7_SHIFT		7
10405 	u8 flags1;
10406 #define XSTORM_ISCSI_CONN_AG_CTX_BIT8_MASK		0x1
10407 #define XSTORM_ISCSI_CONN_AG_CTX_BIT8_SHIFT		0
10408 #define XSTORM_ISCSI_CONN_AG_CTX_BIT9_MASK		0x1
10409 #define XSTORM_ISCSI_CONN_AG_CTX_BIT9_SHIFT		1
10410 #define XSTORM_ISCSI_CONN_AG_CTX_BIT10_MASK		0x1
10411 #define XSTORM_ISCSI_CONN_AG_CTX_BIT10_SHIFT		2
10412 #define XSTORM_ISCSI_CONN_AG_CTX_BIT11_MASK		0x1
10413 #define XSTORM_ISCSI_CONN_AG_CTX_BIT11_SHIFT		3
10414 #define XSTORM_ISCSI_CONN_AG_CTX_BIT12_MASK		0x1
10415 #define XSTORM_ISCSI_CONN_AG_CTX_BIT12_SHIFT		4
10416 #define XSTORM_ISCSI_CONN_AG_CTX_BIT13_MASK		0x1
10417 #define XSTORM_ISCSI_CONN_AG_CTX_BIT13_SHIFT		5
10418 #define XSTORM_ISCSI_CONN_AG_CTX_BIT14_MASK		0x1
10419 #define XSTORM_ISCSI_CONN_AG_CTX_BIT14_SHIFT		6
10420 #define XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_MASK	0x1
10421 #define XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_SHIFT	7
10422 	u8 flags2;
10423 #define XSTORM_ISCSI_CONN_AG_CTX_CF0_MASK			0x3
10424 #define XSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT			0
10425 #define XSTORM_ISCSI_CONN_AG_CTX_CF1_MASK			0x3
10426 #define XSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT			2
10427 #define XSTORM_ISCSI_CONN_AG_CTX_CF2_MASK			0x3
10428 #define XSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT			4
10429 #define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK		0x3
10430 #define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT	6
10431 	u8 flags3;
10432 #define XSTORM_ISCSI_CONN_AG_CTX_CF4_MASK	0x3
10433 #define XSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT	0
10434 #define XSTORM_ISCSI_CONN_AG_CTX_CF5_MASK	0x3
10435 #define XSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT	2
10436 #define XSTORM_ISCSI_CONN_AG_CTX_CF6_MASK	0x3
10437 #define XSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT	4
10438 #define XSTORM_ISCSI_CONN_AG_CTX_CF7_MASK	0x3
10439 #define XSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT	6
10440 	u8 flags4;
10441 #define XSTORM_ISCSI_CONN_AG_CTX_CF8_MASK	0x3
10442 #define XSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT	0
10443 #define XSTORM_ISCSI_CONN_AG_CTX_CF9_MASK	0x3
10444 #define XSTORM_ISCSI_CONN_AG_CTX_CF9_SHIFT	2
10445 #define XSTORM_ISCSI_CONN_AG_CTX_CF10_MASK	0x3
10446 #define XSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT	4
10447 #define XSTORM_ISCSI_CONN_AG_CTX_CF11_MASK	0x3
10448 #define XSTORM_ISCSI_CONN_AG_CTX_CF11_SHIFT	6
10449 	u8 flags5;
10450 #define XSTORM_ISCSI_CONN_AG_CTX_CF12_MASK				0x3
10451 #define XSTORM_ISCSI_CONN_AG_CTX_CF12_SHIFT				0
10452 #define XSTORM_ISCSI_CONN_AG_CTX_CF13_MASK				0x3
10453 #define XSTORM_ISCSI_CONN_AG_CTX_CF13_SHIFT				2
10454 #define XSTORM_ISCSI_CONN_AG_CTX_CF14_MASK				0x3
10455 #define XSTORM_ISCSI_CONN_AG_CTX_CF14_SHIFT				4
10456 #define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_MASK	0x3
10457 #define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_SHIFT	6
10458 	u8 flags6;
10459 #define XSTORM_ISCSI_CONN_AG_CTX_CF16_MASK		0x3
10460 #define XSTORM_ISCSI_CONN_AG_CTX_CF16_SHIFT		0
10461 #define XSTORM_ISCSI_CONN_AG_CTX_CF17_MASK		0x3
10462 #define XSTORM_ISCSI_CONN_AG_CTX_CF17_SHIFT		2
10463 #define XSTORM_ISCSI_CONN_AG_CTX_CF18_MASK		0x3
10464 #define XSTORM_ISCSI_CONN_AG_CTX_CF18_SHIFT		4
10465 #define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_MASK	0x3
10466 #define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_SHIFT	6
10467 	u8 flags7;
10468 #define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_MASK	0x3
10469 #define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_SHIFT	0
10470 #define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_MASK	0x3
10471 #define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_SHIFT	2
10472 #define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_MASK		0x3
10473 #define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_SHIFT		4
10474 #define XSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK			0x1
10475 #define XSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT			6
10476 #define XSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK			0x1
10477 #define XSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT			7
10478 	u8 flags8;
10479 #define XSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK			0x1
10480 #define XSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT			0
10481 #define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK	0x1
10482 #define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT	1
10483 #define XSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK			0x1
10484 #define XSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT			2
10485 #define XSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK			0x1
10486 #define XSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT			3
10487 #define XSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK			0x1
10488 #define XSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT			4
10489 #define XSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK			0x1
10490 #define XSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT			5
10491 #define XSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK			0x1
10492 #define XSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT			6
10493 #define XSTORM_ISCSI_CONN_AG_CTX_CF9EN_MASK			0x1
10494 #define XSTORM_ISCSI_CONN_AG_CTX_CF9EN_SHIFT			7
10495 	u8 flags9;
10496 #define XSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK				0x1
10497 #define XSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT			0
10498 #define XSTORM_ISCSI_CONN_AG_CTX_CF11EN_MASK				0x1
10499 #define XSTORM_ISCSI_CONN_AG_CTX_CF11EN_SHIFT			1
10500 #define XSTORM_ISCSI_CONN_AG_CTX_CF12EN_MASK				0x1
10501 #define XSTORM_ISCSI_CONN_AG_CTX_CF12EN_SHIFT			2
10502 #define XSTORM_ISCSI_CONN_AG_CTX_CF13EN_MASK				0x1
10503 #define XSTORM_ISCSI_CONN_AG_CTX_CF13EN_SHIFT			3
10504 #define XSTORM_ISCSI_CONN_AG_CTX_CF14EN_MASK				0x1
10505 #define XSTORM_ISCSI_CONN_AG_CTX_CF14EN_SHIFT			4
10506 #define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_MASK	0x1
10507 #define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_SHIFT	5
10508 #define XSTORM_ISCSI_CONN_AG_CTX_CF16EN_MASK				0x1
10509 #define XSTORM_ISCSI_CONN_AG_CTX_CF16EN_SHIFT			6
10510 #define XSTORM_ISCSI_CONN_AG_CTX_CF17EN_MASK				0x1
10511 #define XSTORM_ISCSI_CONN_AG_CTX_CF17EN_SHIFT			7
10512 	u8 flags10;
10513 #define XSTORM_ISCSI_CONN_AG_CTX_CF18EN_MASK				0x1
10514 #define XSTORM_ISCSI_CONN_AG_CTX_CF18EN_SHIFT			0
10515 #define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_MASK			0x1
10516 #define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT			1
10517 #define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_MASK		0x1
10518 #define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_SHIFT	2
10519 #define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_MASK		0x1
10520 #define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_SHIFT	3
10521 #define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_MASK			0x1
10522 #define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_SHIFT			4
10523 #define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_MASK		0x1
10524 #define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_SHIFT		5
10525 #define XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK			0x1
10526 #define XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT			6
10527 #define XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_MASK	0x1
10528 #define XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_SHIFT	7
10529 	u8 flags11;
10530 #define XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_MASK	0x1
10531 #define XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT	0
10532 #define XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK	0x1
10533 #define XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT	1
10534 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_MASK	0x1
10535 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_SHIFT	2
10536 #define XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK	0x1
10537 #define XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT	3
10538 #define XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK	0x1
10539 #define XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT	4
10540 #define XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK	0x1
10541 #define XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT	5
10542 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_MASK	0x1
10543 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_SHIFT	6
10544 #define XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_MASK	0x1
10545 #define XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_SHIFT	7
10546 	u8 flags12;
10547 #define XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_MASK		0x1
10548 #define XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_SHIFT	0
10549 #define XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_MASK		0x1
10550 #define XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_SHIFT		1
10551 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_MASK		0x1
10552 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_SHIFT		2
10553 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_MASK		0x1
10554 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_SHIFT		3
10555 #define XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_MASK		0x1
10556 #define XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_SHIFT		4
10557 #define XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_MASK		0x1
10558 #define XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_SHIFT		5
10559 #define XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_MASK		0x1
10560 #define XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_SHIFT		6
10561 #define XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_MASK		0x1
10562 #define XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_SHIFT		7
10563 	u8 flags13;
10564 #define XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_MASK	0x1
10565 #define XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_SHIFT	0
10566 #define XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_MASK		0x1
10567 #define XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_SHIFT	1
10568 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_MASK		0x1
10569 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_SHIFT		2
10570 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_MASK		0x1
10571 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_SHIFT		3
10572 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_MASK		0x1
10573 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_SHIFT		4
10574 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_MASK		0x1
10575 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_SHIFT		5
10576 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_MASK		0x1
10577 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_SHIFT		6
10578 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_MASK		0x1
10579 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_SHIFT		7
10580 	u8 flags14;
10581 #define XSTORM_ISCSI_CONN_AG_CTX_BIT16_MASK			0x1
10582 #define XSTORM_ISCSI_CONN_AG_CTX_BIT16_SHIFT			0
10583 #define XSTORM_ISCSI_CONN_AG_CTX_BIT17_MASK			0x1
10584 #define XSTORM_ISCSI_CONN_AG_CTX_BIT17_SHIFT			1
10585 #define XSTORM_ISCSI_CONN_AG_CTX_BIT18_MASK			0x1
10586 #define XSTORM_ISCSI_CONN_AG_CTX_BIT18_SHIFT			2
10587 #define XSTORM_ISCSI_CONN_AG_CTX_BIT19_MASK			0x1
10588 #define XSTORM_ISCSI_CONN_AG_CTX_BIT19_SHIFT			3
10589 #define XSTORM_ISCSI_CONN_AG_CTX_BIT20_MASK			0x1
10590 #define XSTORM_ISCSI_CONN_AG_CTX_BIT20_SHIFT			4
10591 #define XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_MASK	0x1
10592 #define XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_SHIFT	5
10593 #define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_MASK	0x3
10594 #define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_SHIFT	6
10595 	u8 byte2;
10596 	__le16 physical_q0;
10597 	__le16 physical_q1;
10598 	__le16 dummy_dorq_var;
10599 	__le16 sq_cons;
10600 	__le16 sq_prod;
10601 	__le16 word5;
10602 	__le16 slow_io_total_data_tx_update;
10603 	u8 byte3;
10604 	u8 byte4;
10605 	u8 byte5;
10606 	u8 byte6;
10607 	__le32 reg0;
10608 	__le32 reg1;
10609 	__le32 reg2;
10610 	__le32 more_to_send_seq;
10611 	__le32 reg4;
10612 	__le32 reg5;
10613 	__le32 hq_scan_next_relevant_ack;
10614 	__le16 r2tq_prod;
10615 	__le16 r2tq_cons;
10616 	__le16 hq_prod;
10617 	__le16 hq_cons;
10618 	__le32 remain_seq;
10619 	__le32 bytes_to_next_pdu;
10620 	__le32 hq_tcp_seq;
10621 	u8 byte7;
10622 	u8 byte8;
10623 	u8 byte9;
10624 	u8 byte10;
10625 	u8 byte11;
10626 	u8 byte12;
10627 	u8 byte13;
10628 	u8 byte14;
10629 	u8 byte15;
10630 	u8 e5_reserved;
10631 	__le16 word11;
10632 	__le32 reg10;
10633 	__le32 reg11;
10634 	__le32 exp_stat_sn;
10635 	__le32 ongoing_fast_rxmit_seq;
10636 	__le32 reg14;
10637 	__le32 reg15;
10638 	__le32 reg16;
10639 	__le32 reg17;
10640 };
10641 
10642 struct tstorm_iscsi_conn_ag_ctx {
10643 	u8 reserved0;
10644 	u8 state;
10645 	u8 flags0;
10646 #define TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
10647 #define TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
10648 #define TSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK		0x1
10649 #define TSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT		1
10650 #define TSTORM_ISCSI_CONN_AG_CTX_BIT2_MASK		0x1
10651 #define TSTORM_ISCSI_CONN_AG_CTX_BIT2_SHIFT		2
10652 #define TSTORM_ISCSI_CONN_AG_CTX_BIT3_MASK		0x1
10653 #define TSTORM_ISCSI_CONN_AG_CTX_BIT3_SHIFT		3
10654 #define TSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK		0x1
10655 #define TSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT		4
10656 #define TSTORM_ISCSI_CONN_AG_CTX_BIT5_MASK		0x1
10657 #define TSTORM_ISCSI_CONN_AG_CTX_BIT5_SHIFT		5
10658 #define TSTORM_ISCSI_CONN_AG_CTX_CF0_MASK		0x3
10659 #define TSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT		6
10660 	u8 flags1;
10661 #define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_MASK		0x3
10662 #define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_SHIFT		0
10663 #define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_MASK		0x3
10664 #define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_SHIFT		2
10665 #define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK		0x3
10666 #define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT	4
10667 #define TSTORM_ISCSI_CONN_AG_CTX_CF4_MASK			0x3
10668 #define TSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT			6
10669 	u8 flags2;
10670 #define TSTORM_ISCSI_CONN_AG_CTX_CF5_MASK	0x3
10671 #define TSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT	0
10672 #define TSTORM_ISCSI_CONN_AG_CTX_CF6_MASK	0x3
10673 #define TSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT	2
10674 #define TSTORM_ISCSI_CONN_AG_CTX_CF7_MASK	0x3
10675 #define TSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT	4
10676 #define TSTORM_ISCSI_CONN_AG_CTX_CF8_MASK	0x3
10677 #define TSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT	6
10678 	u8 flags3;
10679 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_MASK		0x3
10680 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_SHIFT		0
10681 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_MASK	0x3
10682 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_SHIFT	2
10683 #define TSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK			0x1
10684 #define TSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT			4
10685 #define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_MASK	0x1
10686 #define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_SHIFT	5
10687 #define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_MASK	0x1
10688 #define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_SHIFT	6
10689 #define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK	0x1
10690 #define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT	7
10691 	u8 flags4;
10692 #define TSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK		0x1
10693 #define TSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT		0
10694 #define TSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK		0x1
10695 #define TSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT		1
10696 #define TSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK		0x1
10697 #define TSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT		2
10698 #define TSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK		0x1
10699 #define TSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT		3
10700 #define TSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK		0x1
10701 #define TSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT		4
10702 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_MASK	0x1
10703 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT	5
10704 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_EN_MASK	0x1
10705 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_EN_SHIFT	6
10706 #define TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK	0x1
10707 #define TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT	7
10708 	u8 flags5;
10709 #define TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK	0x1
10710 #define TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT	0
10711 #define TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK	0x1
10712 #define TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT	1
10713 #define TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK	0x1
10714 #define TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT	2
10715 #define TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK	0x1
10716 #define TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT	3
10717 #define TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK	0x1
10718 #define TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT	4
10719 #define TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK	0x1
10720 #define TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT	5
10721 #define TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK	0x1
10722 #define TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT	6
10723 #define TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK	0x1
10724 #define TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT	7
10725 	__le32 reg0;
10726 	__le32 reg1;
10727 	__le32 rx_tcp_checksum_err_cnt;
10728 	__le32 reg3;
10729 	__le32 reg4;
10730 	__le32 reg5;
10731 	__le32 reg6;
10732 	__le32 reg7;
10733 	__le32 reg8;
10734 	u8 cid_offload_cnt;
10735 	u8 byte3;
10736 	__le16 word0;
10737 };
10738 
10739 struct ustorm_iscsi_conn_ag_ctx {
10740 	u8 byte0;
10741 	u8 byte1;
10742 	u8 flags0;
10743 #define USTORM_ISCSI_CONN_AG_CTX_BIT0_MASK	0x1
10744 #define USTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT	0
10745 #define USTORM_ISCSI_CONN_AG_CTX_BIT1_MASK	0x1
10746 #define USTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT	1
10747 #define USTORM_ISCSI_CONN_AG_CTX_CF0_MASK	0x3
10748 #define USTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT	2
10749 #define USTORM_ISCSI_CONN_AG_CTX_CF1_MASK	0x3
10750 #define USTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT	4
10751 #define USTORM_ISCSI_CONN_AG_CTX_CF2_MASK	0x3
10752 #define USTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT	6
10753 	u8 flags1;
10754 #define USTORM_ISCSI_CONN_AG_CTX_CF3_MASK	0x3
10755 #define USTORM_ISCSI_CONN_AG_CTX_CF3_SHIFT	0
10756 #define USTORM_ISCSI_CONN_AG_CTX_CF4_MASK	0x3
10757 #define USTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT	2
10758 #define USTORM_ISCSI_CONN_AG_CTX_CF5_MASK	0x3
10759 #define USTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT	4
10760 #define USTORM_ISCSI_CONN_AG_CTX_CF6_MASK	0x3
10761 #define USTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT	6
10762 	u8 flags2;
10763 #define USTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK		0x1
10764 #define USTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT		0
10765 #define USTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK		0x1
10766 #define USTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT		1
10767 #define USTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK		0x1
10768 #define USTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT		2
10769 #define USTORM_ISCSI_CONN_AG_CTX_CF3EN_MASK		0x1
10770 #define USTORM_ISCSI_CONN_AG_CTX_CF3EN_SHIFT		3
10771 #define USTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK		0x1
10772 #define USTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT		4
10773 #define USTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK		0x1
10774 #define USTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT		5
10775 #define USTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK		0x1
10776 #define USTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT		6
10777 #define USTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK	0x1
10778 #define USTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT	7
10779 	u8 flags3;
10780 #define USTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK	0x1
10781 #define USTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT	0
10782 #define USTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK	0x1
10783 #define USTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT	1
10784 #define USTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK	0x1
10785 #define USTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT	2
10786 #define USTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK	0x1
10787 #define USTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT	3
10788 #define USTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK	0x1
10789 #define USTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT	4
10790 #define USTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK	0x1
10791 #define USTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT	5
10792 #define USTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK	0x1
10793 #define USTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT	6
10794 #define USTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK	0x1
10795 #define USTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT	7
10796 	u8 byte2;
10797 	u8 byte3;
10798 	__le16 word0;
10799 	__le16 word1;
10800 	__le32 reg0;
10801 	__le32 reg1;
10802 	__le32 reg2;
10803 	__le32 reg3;
10804 	__le16 word2;
10805 	__le16 word3;
10806 };
10807 
10808 /* The iscsi storm connection context of Tstorm */
10809 struct tstorm_iscsi_conn_st_ctx {
10810 	__le32 reserved[44];
10811 };
10812 
10813 struct mstorm_iscsi_conn_ag_ctx {
10814 	u8 reserved;
10815 	u8 state;
10816 	u8 flags0;
10817 #define MSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK	0x1
10818 #define MSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT	0
10819 #define MSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK	0x1
10820 #define MSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT	1
10821 #define MSTORM_ISCSI_CONN_AG_CTX_CF0_MASK	0x3
10822 #define MSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT	2
10823 #define MSTORM_ISCSI_CONN_AG_CTX_CF1_MASK	0x3
10824 #define MSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT	4
10825 #define MSTORM_ISCSI_CONN_AG_CTX_CF2_MASK	0x3
10826 #define MSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT	6
10827 	u8 flags1;
10828 #define MSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK		0x1
10829 #define MSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT		0
10830 #define MSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK		0x1
10831 #define MSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT		1
10832 #define MSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK		0x1
10833 #define MSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT		2
10834 #define MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK	0x1
10835 #define MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT	3
10836 #define MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK	0x1
10837 #define MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT	4
10838 #define MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK	0x1
10839 #define MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT	5
10840 #define MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK	0x1
10841 #define MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT	6
10842 #define MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK	0x1
10843 #define MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT	7
10844 	__le16 word0;
10845 	__le16 word1;
10846 	__le32 reg0;
10847 	__le32 reg1;
10848 };
10849 
10850 /* Combined iSCSI and TCP storm connection of Mstorm */
10851 struct mstorm_iscsi_tcp_conn_st_ctx {
10852 	__le32 reserved_tcp[20];
10853 	__le32 reserved_iscsi[12];
10854 };
10855 
10856 /* The iscsi storm context of Ustorm */
10857 struct ustorm_iscsi_conn_st_ctx {
10858 	__le32 reserved[52];
10859 };
10860 
10861 /* iscsi connection context */
10862 struct iscsi_conn_context {
10863 	struct ystorm_iscsi_conn_st_ctx ystorm_st_context;
10864 	struct pstorm_iscsi_tcp_conn_st_ctx pstorm_st_context;
10865 	struct regpair pstorm_st_padding[2];
10866 	struct pb_context xpb2_context;
10867 	struct xstorm_iscsi_tcp_conn_st_ctx xstorm_st_context;
10868 	struct regpair xstorm_st_padding[2];
10869 	struct xstorm_iscsi_conn_ag_ctx xstorm_ag_context;
10870 	struct tstorm_iscsi_conn_ag_ctx tstorm_ag_context;
10871 	struct regpair tstorm_ag_padding[2];
10872 	struct timers_context timer_context;
10873 	struct ustorm_iscsi_conn_ag_ctx ustorm_ag_context;
10874 	struct pb_context upb_context;
10875 	struct tstorm_iscsi_conn_st_ctx tstorm_st_context;
10876 	struct regpair tstorm_st_padding[2];
10877 	struct mstorm_iscsi_conn_ag_ctx mstorm_ag_context;
10878 	struct mstorm_iscsi_tcp_conn_st_ctx mstorm_st_context;
10879 	struct ustorm_iscsi_conn_st_ctx ustorm_st_context;
10880 };
10881 
10882 /* iSCSI init params passed by driver to FW in iSCSI init ramrod */
10883 struct iscsi_init_ramrod_params {
10884 	struct iscsi_spe_func_init iscsi_init_spe;
10885 	struct tcp_init_params tcp_init;
10886 };
10887 
10888 struct ystorm_iscsi_conn_ag_ctx {
10889 	u8 byte0;
10890 	u8 byte1;
10891 	u8 flags0;
10892 #define YSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK	0x1
10893 #define YSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT	0
10894 #define YSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK	0x1
10895 #define YSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT	1
10896 #define YSTORM_ISCSI_CONN_AG_CTX_CF0_MASK	0x3
10897 #define YSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT	2
10898 #define YSTORM_ISCSI_CONN_AG_CTX_CF1_MASK	0x3
10899 #define YSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT	4
10900 #define YSTORM_ISCSI_CONN_AG_CTX_CF2_MASK	0x3
10901 #define YSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT	6
10902 	u8 flags1;
10903 #define YSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK		0x1
10904 #define YSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT		0
10905 #define YSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK		0x1
10906 #define YSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT		1
10907 #define YSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK		0x1
10908 #define YSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT		2
10909 #define YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK	0x1
10910 #define YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT	3
10911 #define YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK	0x1
10912 #define YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT	4
10913 #define YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK	0x1
10914 #define YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT	5
10915 #define YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK	0x1
10916 #define YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT	6
10917 #define YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK	0x1
10918 #define YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT	7
10919 	u8 byte2;
10920 	u8 byte3;
10921 	__le16 word0;
10922 	__le32 reg0;
10923 	__le32 reg1;
10924 	__le16 word1;
10925 	__le16 word2;
10926 	__le16 word3;
10927 	__le16 word4;
10928 	__le32 reg2;
10929 	__le32 reg3;
10930 };
10931 
10932 #endif
10933