Home
last modified time | relevance | path

Searched refs:WB_0 (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_encoder_phys_wb.c50 ot_params.num = hw_wb->idx - WB_0; in dpu_encoder_phys_wb_set_ot_limit()
88 qos_params.num = hw_wb->idx - WB_0; in dpu_encoder_phys_wb_set_qos_remap()
300 DPU_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0); in _dpu_encoder_phys_wb_update_flush()
303 DPU_DEBUG("[wb:%d] no ctl assigned\n", hw_wb->idx - WB_0); in _dpu_encoder_phys_wb_update_flush()
319 hw_wb->idx - WB_0); in _dpu_encoder_phys_wb_update_flush()
334 hw_wb->idx - WB_0, mode.name, in dpu_encoder_phys_wb_setup()
362 DPU_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0); in dpu_encoder_phys_wb_done_irq()
467 DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0); in dpu_encoder_phys_wb_prepare_for_kickoff()
491 DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0); in dpu_encoder_phys_wb_needs_single_flush()
502 DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0); in dpu_encoder_phys_wb_handle_post_kickoff()
[all …]
Ddpu_rm.h31 struct dpu_hw_wb *hw_wb[WB_MAX - WB_0];
112 return rm->hw_wb[wb_idx - WB_0]; in dpu_rm_get_wb()
Ddpu_hw_ctl.c272 case WB_0: in dpu_hw_ctl_update_pending_flush_wb()
285 ctx->pending_wb_flush_mask |= BIT(wb - WB_0); in dpu_hw_ctl_update_pending_flush_wb_v1()
531 wb_active |= BIT(cfg->wb - WB_0); in dpu_hw_ctl_intf_cfg_v1()
612 wb_active &= ~BIT(cfg->wb - WB_0); in dpu_hw_ctl_reset_intf_cfg_v1()
Ddpu_hw_mdss.h253 WB_0 = 1, enumerator
Ddpu_rm.c184 rm->hw_wb[wb->id - WB_0] = hw; in dpu_rm_init()
Ddpu_encoder.c352 phys_enc->hw_wb ? phys_enc->hw_wb->idx - WB_0 : -1, in dpu_encoder_helper_report_irq_timeout()
2125 phys->hw_wb ? phys->hw_wb->idx - WB_0 : -1, in _dpu_encoder_status_show()