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Searched refs:WREG32_PLL (Results 1 – 13 of 13) sorted by relevance

/drivers/gpu/drm/radeon/
Dradeon_clocks.c402 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); in radeon_legacy_set_engine_clock()
406 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_engine_clock()
412 WREG32_PLL(RADEON_SPLL_CNTL, tmp); in radeon_legacy_set_engine_clock()
418 WREG32_PLL(RADEON_SPLL_CNTL, tmp); in radeon_legacy_set_engine_clock()
425 WREG32_PLL(RADEON_M_SPLL_REF_FB_DIV, tmp); in radeon_legacy_set_engine_clock()
434 WREG32_PLL(RADEON_SPLL_CNTL, tmp); in radeon_legacy_set_engine_clock()
438 WREG32_PLL(RADEON_SPLL_CNTL, tmp); in radeon_legacy_set_engine_clock()
444 WREG32_PLL(RADEON_SPLL_CNTL, tmp); in radeon_legacy_set_engine_clock()
465 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_engine_clock()
471 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); in radeon_legacy_set_engine_clock()
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Drs600.c275 WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length); in rs600_pm_misc()
287 WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl); in rs600_pm_misc()
294 WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl); in rs600_pm_misc()
302 WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl); in rs600_pm_misc()
309 WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl); in rs600_pm_misc()
Dradeon_legacy_crtc.c891 WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl); in radeon_set_pll()
916 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); in radeon_set_pll()
996 WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl); in radeon_set_pll()
1022 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); in radeon_set_pll()
Dradeon_legacy_tv.c286 WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test & ~RADEON_PLL_MASK_READ_B); in radeon_wait_pll_lock()
295 WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test); in radeon_wait_pll_lock()
759 WREG32_PLL(RADEON_TV_PLL_CNTL, tv_pll_cntl); in radeon_legacy_tv_mode_set()
Dradeon_legacy_encoders.c133 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); in radeon_legacy_lvds_update()
661 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_primary_dac_detect()
704 WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl); in radeon_legacy_primary_dac_detect()
1595 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); in radeon_legacy_tv_dac_detect()
1669 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); in radeon_legacy_tv_dac_detect()
Drv515.c155 WREG32_PLL(0x000D, tmp); in rv515_gpu_init()
479 WREG32_PLL(R_00000F_CP_DYN_CNTL, in rv515_clock_startup()
481 WREG32_PLL(R_000011_E2_DYN_CNTL, in rv515_clock_startup()
483 WREG32_PLL(R_000013_IDCT_DYN_CNTL, in rv515_clock_startup()
Dr520.c87 WREG32_PLL(0x000D, tmp); in r520_gpu_init()
Dr420.c203 WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl); in r420_clock_resume()
Dradeon_combios.c2992 WREG32_PLL(reg, val); in radeon_combios_external_tmds_setup()
3109 WREG32_PLL(addr, val); in combios_parse_pll_table()
3122 WREG32_PLL(addr, tmp); in combios_parse_pll_table()
3161 WREG32_PLL(RADEON_MCLK_CNTL, in combios_parse_pll_table()
3165 WREG32_PLL in combios_parse_pll_table()
Dr100.c436 WREG32_PLL(SCLK_CNTL, sclk_cntl); in r100_pm_misc()
437 WREG32_PLL(SCLK_CNTL2, sclk_cntl2); in r100_pm_misc()
438 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl); in r100_pm_misc()
2699 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); in r100_set_common_regs()
3875 WREG32_PLL(R_00000D_SCLK_CNTL, tmp); in r100_clock_startup()
Dr300.c1366 WREG32_PLL(R_00000D_SCLK_CNTL, tmp); in r300_clock_startup()
Dradeon.h2512 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) macro
2547 WREG32_PLL(reg, tmp_); \
/drivers/gpu/drm/amd/amdgpu/
Damdgpu.h1211 WREG32_PLL(reg, tmp_); \