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Searched refs:X1CLK (Results 1 – 8 of 8) sorted by relevance

/drivers/net/hamradio/
Dz8530.h82 #define X1CLK 0x0 /* x1 clock mode */ macro
Dscc.c802 wr(scc,R4,X1CLK|SDLC); /* *1 clock, SDLC mode */ in init_channel()
/drivers/tty/serial/
Dzs.h135 #define X1CLK 0x0 /* x1 clock mode */ macro
Dip22zilog.h116 #define X1CLK 0x0 /* x1 clock mode */ macro
Dsunzilog.h108 #define X1CLK 0x0 /* x1 clock mode */ macro
Dpmac_zilog.h196 #define X1CLK 0x0 /* x1 clock mode */ macro
Dpmac_zilog.c759 write_zsreg(uap, 4, X1CLK | MONSYNC); in pmz_fix_zero_bug_scc()
965 uap->curregs[R4] = X1CLK; in pmz_convert_to_zs()
Dzs.c905 zport->regs[4] |= X1CLK; in zs_set_termios()