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Searched refs:__offset_PIPE (Results 1 – 1 of 1) sorted by relevance

/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5.xml.h546 static inline uint32_t __offset_PIPE(enum mdp5_pipe idx) in __offset_PIPE() function
565 static inline uint32_t REG_MDP5_PIPE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); } in REG_MDP5_PIPE()
567 static inline uint32_t REG_MDP5_PIPE_OP_MODE(enum mdp5_pipe i0) { return 0x00000200 + __offset_PIPE in REG_MDP5_PIPE_OP_MODE()
582 … uint32_t REG_MDP5_PIPE_HIST_CTL_BASE(enum mdp5_pipe i0) { return 0x000002c4 + __offset_PIPE(i0); } in REG_MDP5_PIPE_HIST_CTL_BASE()
584 … uint32_t REG_MDP5_PIPE_HIST_LUT_BASE(enum mdp5_pipe i0) { return 0x000002f0 + __offset_PIPE(i0); } in REG_MDP5_PIPE_HIST_LUT_BASE()
586 … uint32_t REG_MDP5_PIPE_HIST_LUT_SWAP(enum mdp5_pipe i0) { return 0x00000300 + __offset_PIPE(i0); } in REG_MDP5_PIPE_HIST_LUT_SWAP()
588 …_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(enum mdp5_pipe i0) { return 0x00000320 + __offset_PIPE(i0); } in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0()
602 …_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(enum mdp5_pipe i0) { return 0x00000324 + __offset_PIPE(i0); } in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1()
616 …_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(enum mdp5_pipe i0) { return 0x00000328 + __offset_PIPE(i0); } in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2()
630 …_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(enum mdp5_pipe i0) { return 0x0000032c + __offset_PIPE(i0); } in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3()
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