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Searched refs:_clk (Results 1 – 6 of 6) sorted by relevance

/drivers/clk/stm32/
Dclk-stm32-core.h166 #define STM32_CLOCK_CFG(_binding, _clk, _sec_id, _struct, _register)\ argument
170 .clock_cfg = (_struct) {_clk},\
174 #define STM32_MUX_CFG(_binding, _clk, _sec_id)\ argument
175 STM32_CLOCK_CFG(_binding, &(_clk), _sec_id, struct clk_stm32_mux *,\
178 #define STM32_GATE_CFG(_binding, _clk, _sec_id)\ argument
179 STM32_CLOCK_CFG(_binding, &(_clk), _sec_id, struct clk_stm32_gate *,\
182 #define STM32_DIV_CFG(_binding, _clk, _sec_id)\ argument
183 STM32_CLOCK_CFG(_binding, &(_clk), _sec_id, struct clk_stm32_div *,\
186 #define STM32_COMPOSITE_CFG(_binding, _clk, _sec_id)\ argument
187 STM32_CLOCK_CFG(_binding, &(_clk), _sec_id, struct clk_stm32_composite *,\
/drivers/clk/qcom/
Dclk-rpm.c35 static struct clk_rpm clk_rpm_##_name##_clk = { \
48 .peer = &clk_rpm_##_name##_clk, \
60 static struct clk_rpm clk_rpm_##_name##_clk = { \
72 static struct clk_rpm clk_rpm_##_name##_clk = { \
Dclk-smd-rpm.c108 __DEFINE_CLK_SMD_RPM(_name##_clk, _name##_a_clk, \
113 _name##_clk, _name##_a_clk, QCOM_SMD_RPM_BUS_CLK, r_id, \
118 _name##_clk, _name##_a_clk, QCOM_SMD_RPM_BUS_CLK, r_id, \
128 _name##_clk, _name##_a_clk, \
137 __DEFINE_CLK_SMD_RPM(_name##_clk, _name##_a_clk, \
/drivers/ufs/host/
Dufs-exynos.c497 unsigned long clk = 0, _clk, clk_period; in exynos_ufs_calc_pwm_clk_div() local
502 _clk = NSEC_PER_SEC * mult / (clk_period * divs[i] * div); in exynos_ufs_calc_pwm_clk_div()
503 if (_clk >= pwm_min && _clk <= pwm_max) { in exynos_ufs_calc_pwm_clk_div()
504 if (_clk > clk) { in exynos_ufs_calc_pwm_clk_div()
506 clk = _clk; in exynos_ufs_calc_pwm_clk_div()
/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dgm20b.c852 struct gm20b_clk *_clk = gm20b_clk(base); in gm20b_clk_init() local
856 _clk->uv = nvkm_volt_get(volt); in gm20b_clk_init()
859 ret = gm20b_clk_init_dvfs(_clk); in gm20b_clk_init()
/drivers/clk/renesas/
Dr9a06g032-clocks.c153 #define I_GATE(_clk, _rst, _rdy, _midle, _scon, _mirack, _mistat) { \ argument
154 .gate = _clk, \