| /drivers/misc/ |
| D | pch_phub.c | 492 unsigned int addr_offset; in pch_phub_bin_read() local
525 addr_offset = 0; in pch_phub_bin_read()
529 addr_offset = 0; in pch_phub_bin_read()
533 for (addr_offset = 0; addr_offset < count; addr_offset++) { in pch_phub_bin_read()
535 chip->pch_opt_rom_start_address + addr_offset + off, in pch_phub_bin_read()
536 &buf[addr_offset]); in pch_phub_bin_read()
545 return addr_offset; in pch_phub_bin_read()
560 unsigned int addr_offset; in pch_phub_bin_write() local
570 addr_offset = 0; in pch_phub_bin_write()
574 addr_offset = 0; in pch_phub_bin_write()
[all …]
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| /drivers/nvmem/ |
| D | rockchip-efuse.c | 99 unsigned int addr_start, addr_end, addr_offset, addr_len; in rockchip_rk3328_efuse_read() local
114 addr_offset = offset % RK3399_NBYTES; in rockchip_rk3328_efuse_read()
141 memcpy(val, buf + addr_offset, bytes); in rockchip_rk3328_efuse_read()
154 unsigned int addr_start, addr_end, addr_offset, addr_len; in rockchip_rk3399_efuse_read() local
167 addr_offset = offset % RK3399_NBYTES; in rockchip_rk3399_efuse_read()
197 memcpy(val, buf + addr_offset, bytes); in rockchip_rk3399_efuse_read()
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| /drivers/spi/ |
| D | spi-fsl-qspi.c | 645 u32 addr_offset = 0; in fsl_qspi_exec_op() local
658 addr_offset = q->memmap_phy; in fsl_qspi_exec_op()
661 q->selected * q->devtype_data->ahb_buf_size + addr_offset, in fsl_qspi_exec_op()
723 u32 reg, addr_offset = 0; in fsl_qspi_default_setup() local
776 addr_offset = q->memmap_phy; in fsl_qspi_default_setup()
785 qspi_writel(q, q->devtype_data->ahb_buf_size + addr_offset, in fsl_qspi_default_setup()
787 qspi_writel(q, q->devtype_data->ahb_buf_size * 2 + addr_offset, in fsl_qspi_default_setup()
789 qspi_writel(q, q->devtype_data->ahb_buf_size * 3 + addr_offset, in fsl_qspi_default_setup()
791 qspi_writel(q, q->devtype_data->ahb_buf_size * 4 + addr_offset, in fsl_qspi_default_setup()
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| /drivers/net/can/m_can/ |
| D | m_can.h | 67 int (*read_fifo)(struct m_can_classdev *cdev, int addr_offset, void *val, size_t val_count);
68 int (*write_fifo)(struct m_can_classdev *cdev, int addr_offset,
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| D | tcan4x5x-core.c | 189 static int tcan4x5x_read_fifo(struct m_can_classdev *cdev, int addr_offset, in tcan4x5x_read_fifo() argument
194 return regmap_bulk_read(priv->regmap, TCAN4X5X_MRAM_START + addr_offset, val, val_count); in tcan4x5x_read_fifo()
205 int addr_offset, const void *val, size_t val_count) in tcan4x5x_write_fifo() argument
209 return regmap_bulk_write(priv->regmap, TCAN4X5X_MRAM_START + addr_offset, val, val_count); in tcan4x5x_write_fifo()
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| D | m_can.c | 338 u32 addr_offset = cdev->mcfg[MRAM_RXF0].off + fgi * RXF0_ELEMENT_SIZE + in m_can_fifo_read() local
344 return cdev->ops->read_fifo(cdev, addr_offset, val, val_count); in m_can_fifo_read()
351 u32 addr_offset = cdev->mcfg[MRAM_TXB].off + fpi * TXB_ELEMENT_SIZE + in m_can_fifo_write() local
357 return cdev->ops->write_fifo(cdev, addr_offset, val, val_count); in m_can_fifo_write()
369 u32 addr_offset = cdev->mcfg[MRAM_TXE].off + fgi * TXE_ELEMENT_SIZE + in m_can_txe_fifo_read() local
372 return cdev->ops->read_fifo(cdev, addr_offset, val, 1); in m_can_txe_fifo_read()
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| /drivers/mtd/nand/raw/ingenic/ |
| D | ingenic_nand_drv.c | 31 unsigned long addr_offset; member
273 cs->base + nfc->soc_info->addr_offset); in ingenic_nand_exec_instr()
537 .addr_offset = 0x00010000,
544 .addr_offset = 0x00010000,
551 .addr_offset = 0x00800000,
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| /drivers/input/rmi4/ |
| D | rmi_i2c.c | 134 u8 addr_offset = addr & 0xff; in rmi_i2c_read_block() local
139 .len = sizeof(addr_offset), in rmi_i2c_read_block()
140 .buf = &addr_offset, in rmi_i2c_read_block()
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| /drivers/ntb/ |
| D | msi.c | 211 msi_desc->addr_offset = addr - ntb->msi->base_addr; in ntb_msi_set_desc()
375 idx = desc->addr_offset / sizeof(*ntb->msi->peer_mws[peer]); in ntb_msi_peer_trigger()
410 *msi_addr = mw_phys_addr + desc->addr_offset; in ntb_msi_peer_addr()
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| D | ntb_transport.c | 704 qp->peer_msi_desc.addr_offset = in ntb_transport_setup_qp_peer_msi()
710 qp_num, qp->peer_msi_desc.addr_offset, qp->peer_msi_desc.data); in ntb_transport_setup_qp_peer_msi()
712 if (qp->peer_msi_desc.addr_offset) { in ntb_transport_setup_qp_peer_msi()
750 rc = ntb_spad_write(qp->ndev, spad, qp->msi_desc.addr_offset); in ntb_transport_setup_qp_msi()
759 qp_num, qp->msi_irq, qp->msi_desc.addr_offset, in ntb_transport_setup_qp_msi()
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| /drivers/ntb/test/ |
| D | ntb_msi_test.c | 88 nm->isr_ctx[i].desc.addr_offset); in ntb_msit_setup_work()
113 nm->isr_ctx[i].desc.addr_offset); in ntb_msit_desc_changed()
138 desc[i].addr_offset = ntb_peer_spad_read(nm->ntb, peer, in ntb_msit_copy_peer_desc()
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| /drivers/staging/axis-fifo/ |
| D | axis-fifo.c | 148 size_t count, unsigned int addr_offset) in sysfs_write() argument
158 iowrite32(tmp, fifo->base_addr + addr_offset); in sysfs_write()
164 unsigned int addr_offset) in sysfs_read() argument
171 read_val = ioread32(fifo->base_addr + addr_offset); in sysfs_read()
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| /drivers/net/ethernet/alacritech/ |
| D | slicoss.c | 441 buff->addr_offset = offset; in slic_refill_rx_queue()
570 buff->addr_offset + sizeof(*desc), in slic_handle_receive()
578 buff->addr_offset + in slic_handle_receive()
807 stq->addr_offset[i] = offset; in slic_init_stat_queue()
817 stq->descs[i] - stq->addr_offset[i], in slic_init_stat_queue()
818 stq->paddr[i] - stq->addr_offset[i]); in slic_init_stat_queue()
831 stq->descs[i] - stq->addr_offset[i], in slic_free_stat_queue()
832 stq->paddr[i] - stq->addr_offset[i]); in slic_free_stat_queue()
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| D | slic.h | 478 unsigned int addr_offset[SLIC_NUM_STAT_DESC_ARRAYS]; member
525 unsigned int addr_offset; member
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| /drivers/net/ethernet/huawei/hinic/ |
| D | hinic_hw_qp.c | 83 qp_ctxt_hdr->addr_offset = SQ_CTXT_OFFSET(max_sqs, max_rqs, 0); in hinic_qp_prepare_header()
85 qp_ctxt_hdr->addr_offset = RQ_CTXT_OFFSET(max_sqs, max_rqs, 0); in hinic_qp_prepare_header()
87 qp_ctxt_hdr->addr_offset = SIZE_16BYTES(qp_ctxt_hdr->addr_offset); in hinic_qp_prepare_header()
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| D | hinic_hw_qp_ctxt.h | 151 u32 addr_offset; member
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| D | hinic_hw_io.c | 227 ctxt_block->cmdq_hdr.addr_offset = 0; in hinic_clean_queue_offload_ctxt()
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| /drivers/staging/media/atomisp/pci/hive_isp_css_common/host/ |
| D | input_system.c | 744 int addr_offset; in input_switch_cfg() local
750 for (addr_offset = 0; addr_offset < N_RX_CHANNEL_ID * 2; addr_offset++) { in input_switch_cfg()
751 assert(addr_offset * SIZEOF_HRT_REG + _REG_GP_IFMT_input_switch_lut_reg0 <= in input_switch_cfg()
754 _REG_GP_IFMT_input_switch_lut_reg0 + addr_offset * SIZEOF_HRT_REG, in input_switch_cfg()
755 cfg->hsync_data_reg[addr_offset]); in input_switch_cfg()
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| /drivers/net/wireless/intel/iwlwifi/fw/api/ |
| D | dbg-tlv.h | 278 __le32 addr_offset; member
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| /drivers/crypto/intel/qat/qat_common/ |
| D | icp_qat_uclo.h | 331 unsigned int addr_offset; member
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| /drivers/net/wireless/intel/iwlwifi/ |
| D | iwl-dbg-tlv.c | 862 u32 offset = le32_to_cpu(config_list->addr_offset); in iwl_dbg_tlv_apply_config()
918 le32_to_cpu(config_list->addr_offset)); in iwl_dbg_tlv_apply_config()
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| /drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/ |
| D | phy_n.c | 14713 u16 addr_offset[] = { 0x186, 0x195, 0x2c5}; in wlc_phy_ipa_set_tx_digi_filts_nphy() local
14717 write_phy_reg(pi, addr_offset[type] + j, in wlc_phy_ipa_set_tx_digi_filts_nphy()
17045 u16 addr_offset = 0x2c5; in wlc_phy_extpa_set_tx_digi_filts_nphy() local
17048 write_phy_reg(pi, addr_offset + j, in wlc_phy_extpa_set_tx_digi_filts_nphy()
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