| /drivers/gpu/drm/amd/display/modules/freesync/ |
| D | freesync.c | 191 in_out_vrr->adjust.v_total_max); in update_v_total_for_static_ramp()
252 in_out_vrr->adjust.v_total_min = v_total; in update_v_total_for_static_ramp()
253 in_out_vrr->adjust.v_total_max = v_total; in update_v_total_for_static_ramp()
293 in_out_vrr->adjust.v_total_min = in apply_below_the_range()
296 in_out_vrr->adjust.v_total_max = in apply_below_the_range()
458 in_out_vrr->adjust.v_total_min = in apply_fixed_refresh()
461 in_out_vrr->adjust.v_total_max = in apply_fixed_refresh()
462 in_out_vrr->adjust.v_total_min; in apply_fixed_refresh()
464 in_out_vrr->adjust.v_total_min = in apply_fixed_refresh()
467 in_out_vrr->adjust.v_total_max = in apply_fixed_refresh()
[all …]
|
| /drivers/gpu/drm/amd/display/modules/hdcp/ |
| D | hdcp.c | 43 hdcp->connection.link.adjust.hdcp1.disable = 1; in push_error_status()
47 hdcp->connection.link.adjust.hdcp2.disable = 1; in push_error_status()
60 hdcp->displays[i].adjust.disable != MOD_HDCP_DISPLAY_DISABLE_AUTHENTICATION) { in is_cp_desired_hdcp1()
67 !hdcp->connection.link.adjust.hdcp1.disable && in is_cp_desired_hdcp1()
80 hdcp->displays[i].adjust.disable != MOD_HDCP_DISPLAY_DISABLE_AUTHENTICATION) { in is_cp_desired_hdcp2()
87 !hdcp->connection.link.adjust.hdcp2.disable && in is_cp_desired_hdcp2()
262 display->adjust.disable == true && in update_display_adjustments()
264 display->adjust.disable = false; in update_display_adjustments()
271 display->adjust.disable = true; in update_display_adjustments()
275 memcmp(adj, &display->adjust, in update_display_adjustments()
[all …]
|
| D | hdcp1_transition.c | 35 struct mod_hdcp_link_adjustment *adjust = &hdcp->connection.link.adjust; in mod_hdcp_hdcp1_transition() local
51 adjust->hdcp1.disable = 1; in mod_hdcp_hdcp1_transition()
111 adjust->hdcp1.postpone_encryption = 1; in mod_hdcp_hdcp1_transition()
158 struct mod_hdcp_link_adjustment *adjust = &hdcp->connection.link.adjust; in mod_hdcp_hdcp1_dp_transition() local
167 adjust->hdcp1.disable = 1; in mod_hdcp_hdcp1_dp_transition()
177 adjust->hdcp1.disable = 1; in mod_hdcp_hdcp1_dp_transition()
233 } else if (conn->hdcp1_retry_count < conn->link.adjust.hdcp1.min_auth_retries_wa) { in mod_hdcp_hdcp1_dp_transition()
263 adjust->hdcp1.postpone_encryption = 1; in mod_hdcp_hdcp1_dp_transition()
287 adjust->hdcp1.postpone_encryption = 1; in mod_hdcp_hdcp1_dp_transition()
|
| D | hdcp2_transition.c | 35 struct mod_hdcp_link_adjustment *adjust = &hdcp->connection.link.adjust; in mod_hdcp_hdcp2_transition() local
41 adjust->hdcp2.disable = 1; in mod_hdcp_hdcp2_transition()
53 adjust->hdcp2.disable = 1; in mod_hdcp_hdcp2_transition()
91 !adjust->hdcp2.force_no_stored_km) { in mod_hdcp_hdcp2_transition()
104 if (adjust->hdcp2.increase_h_prime_timeout) in mod_hdcp_hdcp2_transition()
180 adjust->hdcp2.force_no_stored_km = 1; in mod_hdcp_hdcp2_transition()
376 struct mod_hdcp_link_adjustment *adjust = &hdcp->connection.link.adjust; in mod_hdcp_hdcp2_dp_transition() local
382 adjust->hdcp2.disable = 1; in mod_hdcp_hdcp2_dp_transition()
394 adjust->hdcp2.disable = 1; in mod_hdcp_hdcp2_dp_transition()
416 !adjust->hdcp2.force_no_stored_km) { in mod_hdcp_hdcp2_dp_transition()
[all …]
|
| /drivers/gpu/drm/tegra/ |
| D | dp.c | 442 struct drm_dp_link_train_set *adjust = &train->adjust; in drm_dp_link_train_init() local
447 adjust->voltage_swing[i] = 0; in drm_dp_link_train_init()
450 adjust->pre_emphasis[i] = 0; in drm_dp_link_train_init()
453 adjust->post_cursor[i] = 0; in drm_dp_link_train_init()
550 struct drm_dp_link_train_set *adjust = &link->train.adjust; in drm_dp_link_get_adjustments() local
563 adjust->voltage_swing[i] = in drm_dp_link_get_adjustments()
567 adjust->pre_emphasis[i] = in drm_dp_link_get_adjustments()
571 adjust->post_cursor[i] = in drm_dp_link_get_adjustments()
579 struct drm_dp_link_train_set *adjust = &train->adjust; in drm_dp_link_train_adjust() local
583 if (request->voltage_swing[i] != adjust->voltage_swing[i]) in drm_dp_link_train_adjust()
[all …]
|
| /drivers/tty/ |
| D | tty_ldsem.c | 78 long adjust, count; in __ldsem_wake_readers() local
85 adjust = sem->wait_readers * (LDSEM_ACTIVE_BIAS - LDSEM_WAIT_BIAS); in __ldsem_wake_readers()
86 count = atomic_long_add_return(adjust, &sem->count); in __ldsem_wake_readers()
90 if (atomic_long_try_cmpxchg(&sem->count, &count, count - adjust)) in __ldsem_wake_readers()
159 long adjust = -LDSEM_ACTIVE_BIAS + LDSEM_WAIT_BIAS; in down_read_failed() local
170 if (atomic_long_try_cmpxchg(&sem->count, &count, count + adjust)) { in down_read_failed()
171 count += adjust; in down_read_failed()
233 long adjust = -LDSEM_ACTIVE_BIAS; in down_write_failed() local
245 if (atomic_long_try_cmpxchg(&sem->count, &count, count + adjust)) in down_write_failed()
|
| /drivers/gpu/drm/nouveau/nvkm/subdev/pmu/ |
| D | gm20b.c | 66 gm20b_pmu_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust) in gm20b_pmu_acr_bld_patch() argument
73 hdr.code_dma_base = lower_32_bits((addr + adjust) >> 8); in gm20b_pmu_acr_bld_patch()
74 hdr.code_dma_base1 = upper_32_bits((addr + adjust) >> 8); in gm20b_pmu_acr_bld_patch()
76 hdr.data_dma_base = lower_32_bits((addr + adjust) >> 8); in gm20b_pmu_acr_bld_patch()
77 hdr.data_dma_base1 = upper_32_bits((addr + adjust) >> 8); in gm20b_pmu_acr_bld_patch()
79 hdr.overlay_dma_base = lower_32_bits((addr + adjust) << 8); in gm20b_pmu_acr_bld_patch()
80 hdr.overlay_dma_base1 = upper_32_bits((addr + adjust) << 8); in gm20b_pmu_acr_bld_patch()
|
| /drivers/gpu/drm/nouveau/nvkm/engine/gr/ |
| D | gm20b.c | 34 gm20b_gr_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust) in gm20b_gr_acr_bld_patch() argument
41 hdr.code_dma_base = lower_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch()
42 hdr.code_dma_base1 = upper_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch()
44 hdr.data_dma_base = lower_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch()
45 hdr.data_dma_base1 = upper_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch()
|
| D | gp108.c | 29 gp108_gr_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust) in gp108_gr_acr_bld_patch() argument
33 hdr.code_dma_base = hdr.code_dma_base + adjust; in gp108_gr_acr_bld_patch()
34 hdr.data_dma_base = hdr.data_dma_base + adjust; in gp108_gr_acr_bld_patch()
|
| D | gm200.c | 46 gm200_gr_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust) in gm200_gr_acr_bld_patch() argument
50 hdr.code_dma_base = hdr.code_dma_base + adjust; in gm200_gr_acr_bld_patch()
51 hdr.data_dma_base = hdr.data_dma_base + adjust; in gm200_gr_acr_bld_patch()
|
| /drivers/gpu/drm/nouveau/nvkm/engine/sec2/ |
| D | gp102.c | 78 gp102_sec2_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust) in gp102_sec2_acr_bld_patch() argument
82 hdr.code_dma_base = hdr.code_dma_base + adjust; in gp102_sec2_acr_bld_patch()
83 hdr.data_dma_base = hdr.data_dma_base + adjust; in gp102_sec2_acr_bld_patch()
84 hdr.overlay_dma_base = hdr.overlay_dma_base + adjust; in gp102_sec2_acr_bld_patch()
241 gp102_sec2_acr_bld_patch_1(struct nvkm_acr *acr, u32 bld, s64 adjust) in gp102_sec2_acr_bld_patch_1() argument
245 hdr.code_dma_base = hdr.code_dma_base + adjust; in gp102_sec2_acr_bld_patch_1()
246 hdr.data_dma_base = hdr.data_dma_base + adjust; in gp102_sec2_acr_bld_patch_1()
|
| /drivers/media/platform/samsung/exynos4-is/ |
| D | fimc-is-param.c | 99 __hw_param_copy(&par->isp.adjust, &cfg->isp.adjust); in __fimc_is_hw_update_param()
372 isp->adjust.contrast = val; in __is_set_isp_adjust()
375 isp->adjust.saturation = val; in __is_set_isp_adjust()
378 isp->adjust.sharpness = val; in __is_set_isp_adjust()
381 isp->adjust.exposure = val; in __is_set_isp_adjust()
384 isp->adjust.brightness = val; in __is_set_isp_adjust()
387 isp->adjust.hue = val; in __is_set_isp_adjust()
390 isp->adjust.contrast = 0; in __is_set_isp_adjust()
391 isp->adjust.saturation = 0; in __is_set_isp_adjust()
392 isp->adjust.sharpness = 0; in __is_set_isp_adjust()
[all …]
|
| /drivers/iio/common/inv_sensors/ |
| D | inv_sensors_timestamp.c | 112 int64_t adjust; in inv_align_timestamp_it() local
122 adjust = add_max; in inv_align_timestamp_it()
124 adjust = sub_max; in inv_align_timestamp_it()
126 adjust = 0; in inv_align_timestamp_it()
128 ts->timestamp += adjust; in inv_align_timestamp_it()
|
| /drivers/gpu/drm/amd/display/dc/dce60/ |
| D | dce60_hw_sequencer.c | 275 struct xfm_grph_csc_adjustment adjust; in dce60_program_front_end_for_pipe() local
283 memset(&adjust, 0, sizeof(adjust)); in dce60_program_front_end_for_pipe()
284 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; in dce60_program_front_end_for_pipe()
303 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; in dce60_program_front_end_for_pipe()
306 adjust.temperature_matrix[i] = in dce60_program_front_end_for_pipe()
310 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); in dce60_program_front_end_for_pipe()
|
| /drivers/net/ethernet/intel/igc/ |
| D | igc_ptp.c | 475 int adjust; in igc_ptp_rx_pktstamp() local
494 adjust = IGC_I225_RX_LATENCY_10; in igc_ptp_rx_pktstamp()
497 adjust = IGC_I225_RX_LATENCY_100; in igc_ptp_rx_pktstamp()
500 adjust = IGC_I225_RX_LATENCY_1000; in igc_ptp_rx_pktstamp()
503 adjust = IGC_I225_RX_LATENCY_2500; in igc_ptp_rx_pktstamp()
506 adjust = 0; in igc_ptp_rx_pktstamp()
511 return ktime_sub_ns(timestamp, adjust); in igc_ptp_rx_pktstamp()
715 int adjust = 0; in igc_ptp_tx_reg_to_stamp() local
726 adjust = IGC_I225_TX_LATENCY_10; in igc_ptp_tx_reg_to_stamp()
729 adjust = IGC_I225_TX_LATENCY_100; in igc_ptp_tx_reg_to_stamp()
[all …]
|
| /drivers/ata/ |
| D | pata_hpt37x.c | 948 int dpll, adjust; in hpt37x_init_one() local
963 for (adjust = 0; adjust < 8; adjust++) { in hpt37x_init_one()
970 if (adjust & 1) in hpt37x_init_one()
971 f_low -= adjust >> 1; in hpt37x_init_one()
973 f_high += adjust >> 1; in hpt37x_init_one()
977 if (adjust == 8) { in hpt37x_init_one()
|
| D | pata_hpt3x2n.c | 496 int adjust; in hpt3x2n_init_one() local
575 for (adjust = 0; adjust < 8; adjust++) { in hpt3x2n_init_one()
580 if (adjust == 8) { in hpt3x2n_init_one()
|
| /drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/ |
| D | dce110_clk_mgr.c | 102 struct dc_crtc_timing_adjust adjust = stream->adjust; in dce110_get_min_vblank_time_us() local
103 if (adjust.v_total_max != adjust.v_total_min) in dce110_get_min_vblank_time_us()
104 vertical_total_min = adjust.v_total_min; in dce110_get_min_vblank_time_us()
|
| /drivers/media/tuners/ |
| D | tda9887.c | 311 static char *adjust[32] = { in dump_write_message() local
361 adjust[buf[2] & 0x1f]); in dump_write_message()
436 static unsigned int adjust = UNSET; variable
441 module_param(adjust, int, 0644);
468 if (adjust < 0x20) { in tda9887_set_insmod()
470 buf[2] |= adjust; in tda9887_set_insmod()
|
| /drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_dwb_cm.c | 357 struct cm_grph_csc_adjustment adjust = params->csc_params; in dwb3_set_gamut_remap() local
360 if (adjust.gamut_adjust_type != CM_GAMUT_ADJUST_TYPE_SW) { in dwb3_set_gamut_remap()
362 dwb3_program_gamut_remap(dwbc, NULL, adjust.gamut_coef_format, CM_GAMUT_REMAP_MODE_BYPASS); in dwb3_set_gamut_remap()
369 arr_matrix[i] = adjust.temperature_matrix[i]; in dwb3_set_gamut_remap()
377 adjust.gamut_coef_format, CM_GAMUT_REMAP_MODE_RAMB_COEFF); in dwb3_set_gamut_remap()
380 adjust.gamut_coef_format, CM_GAMUT_REMAP_MODE_RAMA_COEFF); in dwb3_set_gamut_remap()
|
| /drivers/net/ethernet/intel/igb/ |
| D | igb_ptp.c | 953 int adjust = 0; in igb_ptp_tx_hwtstamp() local
963 adjust = IGB_I210_TX_LATENCY_10; in igb_ptp_tx_hwtstamp()
966 adjust = IGB_I210_TX_LATENCY_100; in igb_ptp_tx_hwtstamp()
969 adjust = IGB_I210_TX_LATENCY_1000; in igb_ptp_tx_hwtstamp()
975 ktime_add_ns(shhwtstamps.hwtstamp, adjust); in igb_ptp_tx_hwtstamp()
1009 int adjust = 0; in igb_ptp_rx_pktstamp() local
1029 adjust = IGB_I210_RX_LATENCY_10; in igb_ptp_rx_pktstamp()
1032 adjust = IGB_I210_RX_LATENCY_100; in igb_ptp_rx_pktstamp()
1035 adjust = IGB_I210_RX_LATENCY_1000; in igb_ptp_rx_pktstamp()
1040 *timestamp = ktime_sub_ns(ts.hwtstamp, adjust); in igb_ptp_rx_pktstamp()
[all …]
|
| /drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_hw_sequencer.c | 1553 params.vertical_total_min = stream->adjust.v_total_min; in apply_single_controller_ctx_to_hw()
1554 params.vertical_total_max = stream->adjust.v_total_max; in apply_single_controller_ctx_to_hw()
1560 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0) in apply_single_controller_ctx_to_hw()
1911 int num_pipes, struct dc_crtc_timing_adjust adjust) in set_drr() argument
1920 params.vertical_total_max = adjust.v_total_max; in set_drr()
1921 params.vertical_total_min = adjust.v_total_min; in set_drr()
1931 if (adjust.v_total_max != 0 && adjust.v_total_min != 0) in set_drr()
2402 struct xfm_grph_csc_adjustment adjust; in program_gamut_remap() local
2403 memset(&adjust, 0, sizeof(adjust)); in program_gamut_remap()
2404 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; in program_gamut_remap()
[all …]
|
| /drivers/mmc/host/ |
| D | meson-gx-mmc.c | 140 unsigned int adjust; member
509 unsigned int val = readl(host->regs + host->data->adjust); in meson_mmc_disable_resampling()
512 writel(val, host->regs + host->data->adjust); in meson_mmc_disable_resampling()
521 val = readl(host->regs + host->data->adjust); in meson_mmc_reset_resampling()
523 writel(val, host->regs + host->data->adjust); in meson_mmc_reset_resampling()
536 val = readl(host->regs + host->data->adjust); in meson_mmc_resampling_tuning()
538 writel(val, host->regs + host->data->adjust); in meson_mmc_resampling_tuning()
548 writel(val, host->regs + host->data->adjust); in meson_mmc_resampling_tuning()
1313 .adjust = SD_EMMC_ADJUST,
1321 .adjust = SD_EMMC_V3_ADJUST,
|
| /drivers/gpu/drm/nouveau/nvkm/engine/dma/ |
| D | usernv04.c | 47 u64 adjust = dmaobj->base.start & 0x00000fff; in nv04_dmaobj_bind() local
65 nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0 | (adjust << 20)); in nv04_dmaobj_bind()
|
| /drivers/rtc/ |
| D | sysfs.c | 161 int adjust = 0; in wakealarm_store() local
178 adjust = 1; in wakealarm_store()
184 if (adjust) in wakealarm_store()
|