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/drivers/clk/bcm/
Dclk-bcm63xx-gate.c18 u8 bit; member
32 .bit = BCM3368_CLK_MAC,
35 .bit = BCM3368_CLK_TC,
38 .bit = BCM3368_CLK_US_TOP,
41 .bit = BCM3368_CLK_DS_TOP,
44 .bit = BCM3368_CLK_ACM,
47 .bit = BCM3368_CLK_SPI,
50 .bit = BCM3368_CLK_USBS,
53 .bit = BCM3368_CLK_BMU,
56 .bit = BCM3368_CLK_PCM,
[all …]
Dclk-bcm63268-timer.c32 u8 bit; member
38 .bit = BCM63268_TCLK_EPHY1,
41 .bit = BCM63268_TCLK_EPHY2,
44 .bit = BCM63268_TCLK_EPHY3,
47 .bit = BCM63268_TCLK_GPHY1,
50 .bit = BCM63268_TCLK_DSL,
53 .bit = BCM63268_TCLK_WAKEON_EPHY,
56 .bit = BCM63268_TCLK_WAKEON_DSL,
59 .bit = BCM63268_TCLK_FAP1,
62 .bit = BCM63268_TCLK_FAP2,
[all …]
/drivers/pmdomain/bcm/
Dbcm63xx-power.c34 uint8_t bit; member
114 max_bit = max(max_bit, entry->bit); in bcm63xx_power_probe()
143 pmd->mask = BIT(entry->bit); in bcm63xx_power_probe()
156 power->genpd[entry->bit] = &pmd->genpd; in bcm63xx_power_probe()
177 .bit = BCM6318_POWER_DOMAIN_PCIE,
180 .bit = BCM6318_POWER_DOMAIN_USB,
183 .bit = BCM6318_POWER_DOMAIN_EPHY0,
186 .bit = BCM6318_POWER_DOMAIN_EPHY1,
189 .bit = BCM6318_POWER_DOMAIN_EPHY2,
192 .bit = BCM6318_POWER_DOMAIN_EPHY3,
[all …]
/drivers/acpi/pmic/
Dintel_pmic_bxtwc.c31 .bit = VR_MODE_AUTO,
36 .bit = VR_MODE_AUTO,
41 .bit = VR_MODE_AUTO,
46 .bit = VR_MODE_AUTO,
51 .bit = VR_MODE_NORMAL,
56 .bit = VR_MODE_NORMAL,
61 .bit = VR_MODE_NORMAL,
66 .bit = VR_MODE_NORMAL,
71 .bit = VR_MODE_NORMAL,
76 .bit = VR_MODE_NORMAL,
[all …]
Dintel_pmic_chtwc.c77 .bit = 0x01,
82 .bit = 0x07,
87 .bit = 0x01,
92 .bit = 0x07,
97 .bit = 0x07,
102 .bit = 0x07,
107 .bit = 0x01,
112 .bit = 0x07,
117 .bit = 0x07,
142 .bit = 0x07,
[all …]
Dintel_pmic_bytcrc.c28 .bit = 0x00,
33 .bit = 0x00,
38 .bit = 0x00,
43 .bit = 0x00,
48 .bit = 0x00,
53 .bit = 0x00,
58 .bit = 0x00,
68 .bit = 0x00,
78 .bit = 0x00,
83 .bit = 0x00,
[all …]
Dintel_pmic_xpower.c33 .bit = 0x05,
38 .bit = 0x06,
43 .bit = 0x07,
48 .bit = 0x03,
53 .bit = 0x04,
58 .bit = 0x05,
63 .bit = 0x06,
68 .bit = 0x00,
73 .bit = 0x01,
78 .bit = 0x02,
[all …]
/drivers/memory/tegra/
Dtegra210.c22 .bit = 1,
38 .bit = 2,
54 .bit = 3,
70 .bit = 4,
86 .bit = 5,
102 .bit = 6,
118 .bit = 14,
134 .bit = 15,
150 .bit = 16,
166 .bit = 17,
[all …]
Dtegra114.c33 .bit = 1,
49 .bit = 2,
65 .bit = 3,
81 .bit = 4,
97 .bit = 5,
113 .bit = 6,
129 .bit = 9,
145 .bit = 10,
161 .bit = 11,
177 .bit = 15,
[all …]
Dtegra124.c34 .bit = 1,
50 .bit = 2,
66 .bit = 3,
82 .bit = 4,
98 .bit = 5,
114 .bit = 6,
130 .bit = 14,
146 .bit = 15,
162 .bit = 16,
178 .bit = 17,
[all …]
Dtegra30.c56 .bit = 1,
73 .bit = 2,
90 .bit = 3,
107 .bit = 4,
124 .bit = 5,
141 .bit = 6,
158 .bit = 7,
175 .bit = 8,
192 .bit = 9,
209 .bit = 10,
[all …]
/drivers/net/wireless/zydas/zd1211rw/
Dzd_rf_rf2959.c39 static int bit(u32 rw, int bit)
41 return bits(rw, bit, bit);
54 bits(rw, 14, 15), bit(rw, 3), bit(rw, 2), bit(rw, 1),
55 bit(rw, 0));
61 bit(rw, 17), bit(rw, 16), bit(rw, 15), bit(rw, 14),
62 bit(rw, 13), bit(rw, 12), bit(rw, 11), bit(rw, 10),
80 bit(rw, 17), bit(rw, 16), bit(rw, 15), bit(rw, 14),
81 bit(rw, 13), bit(rw, 12), bit(rw, 11), bit(rw, 10),
104 bit(rw, 17), bits(rw, 15, 16), bits(rw, 10, 14),
105 bits(rw, 7, 9), bits(rw, 4, 6), bit(rw, 3), bit(rw, 2),
[all …]
/drivers/gpio/
Dgpio-xilinx.c77 static inline int xgpio_from_bit(struct xgpio_instance *chip, int bit) in xgpio_from_bit() argument
79 return bitmap_bitremap(bit, chip->hw_map, chip->sw_map, 64); in xgpio_from_bit()
87 static inline u32 xgpio_get_value32(const unsigned long *map, int bit) in xgpio_get_value32() argument
89 const size_t index = BIT_WORD(bit); in xgpio_get_value32()
90 const unsigned long offset = (bit % BITS_PER_LONG) & BIT(5); in xgpio_get_value32()
95 static inline void xgpio_set_value32(unsigned long *map, int bit, u32 v) in xgpio_set_value32() argument
97 const size_t index = BIT_WORD(bit); in xgpio_set_value32()
98 const unsigned long offset = (bit % BITS_PER_LONG) & BIT(5); in xgpio_set_value32()
116 static void xgpio_read_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a) in xgpio_read_ch() argument
118 void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32); in xgpio_read_ch()
[all …]
/drivers/clk/ux500/
Dreset-prcc.c22 #define PRCC_RESET_LINE(prcc_num, bit) \ argument
23 (((prcc_num) * PRCC_PERIPHS_PER_CLUSTER) + (bit))
72 unsigned int bit = id % PRCC_PERIPHS_PER_CLUSTER; in u8500_prcc_reset() local
74 pr_debug("PRCC cycle reset id %lu, bit %u\n", id, bit); in u8500_prcc_reset()
80 writel(BIT(bit), base + PRCC_K_SOFTRST_CLEAR); in u8500_prcc_reset()
82 writel(BIT(bit), base + PRCC_K_SOFTRST_SET); in u8500_prcc_reset()
93 unsigned int bit = id % PRCC_PERIPHS_PER_CLUSTER; in u8500_prcc_reset_assert() local
95 pr_debug("PRCC assert reset id %lu, bit %u\n", id, bit); in u8500_prcc_reset_assert()
96 writel(BIT(bit), base + PRCC_K_SOFTRST_CLEAR); in u8500_prcc_reset_assert()
106 unsigned int bit = id % PRCC_PERIPHS_PER_CLUSTER; in u8500_prcc_reset_deassert() local
[all …]
/drivers/auxdisplay/
Dks0108.c58 #define bit(n) (((unsigned char)1)<<(n)) macro
68 parport_write_control(ks0108_parport, byte ^ (bit(0) | bit(1) | bit(3))); in ks0108_writecontrol()
73 ks0108_writedata((state ? bit(0) : 0) | bit(1) | bit(2) | bit(3) | bit(4) | bit(5)); in ks0108_displaystate()
78 ks0108_writedata(min_t(unsigned char, startline, 63) | bit(6) | in ks0108_startline()
79 bit(7)); in ks0108_startline()
84 ks0108_writedata(min_t(unsigned char, address, 63) | bit(6)); in ks0108_address()
89 ks0108_writedata(min_t(unsigned char, page, 7) | bit(3) | bit(4) | in ks0108_page()
90 bit(5) | bit(7)); in ks0108_page()
/drivers/pinctrl/
Dpinctrl-rockchip.c402 .bit = 0,
408 .bit = 2,
414 .bit = 4,
420 .bit = 6,
426 .bit = 8,
432 .bit = 10,
438 .bit = 12,
444 .bit = 14,
450 .bit = 0,
456 .bit = 2,
[all …]
/drivers/media/test-drivers/vivid/
Dvivid-vbi-gen.c29 unsigned bit = 0; in vivid_vbi_gen_wss_raw() local
33 wss_insert(wss + bit, 0x1f1c71c7, 29); bit += 29; in vivid_vbi_gen_wss_raw()
34 wss_insert(wss + bit, 0x1e3c1f, 24); bit += 24; in vivid_vbi_gen_wss_raw()
37 for (i = 0; i <= 13; i++, bit += 6) in vivid_vbi_gen_wss_raw()
38 wss_insert(wss + bit, (wss_data & (1 << i)) ? one : zero, 6); in vivid_vbi_gen_wss_raw()
40 for (i = 0, bit = 0; bit < sizeof(wss); bit++) { in vivid_vbi_gen_wss_raw()
41 unsigned n = ((bit + 1) * sampling_rate) / rate; in vivid_vbi_gen_wss_raw()
44 buf[i++] = wss[bit]; in vivid_vbi_gen_wss_raw()
53 unsigned bit = 0; in vivid_vbi_gen_teletext_raw() local
60 for (i = 0, bit = 0; bit < sizeof(teletext) * 8; bit++) { in vivid_vbi_gen_teletext_raw()
[all …]
/drivers/platform/x86/
Dmsi-ec.c59 .bit = 1,
63 .bit = 4,
67 .bit = 7,
107 .bit = 2,
139 .bit = 1,
143 .bit = 4,
147 .bit = 7,
187 .bit = 2,
216 .bit = 1,
220 .bit = 4,
[all …]
/drivers/s390/cio/
Dairq.c227 unsigned long bit, i, flags; in airq_iv_alloc() local
232 bit = find_first_bit_inv(iv->avail, iv->bits); in airq_iv_alloc()
233 while (bit + num <= iv->bits) { in airq_iv_alloc()
235 if (!test_bit_inv(bit + i, iv->avail)) in airq_iv_alloc()
240 clear_bit_inv(bit + i, iv->avail); in airq_iv_alloc()
241 if (bit + num >= iv->end) in airq_iv_alloc()
242 iv->end = bit + num + 1; in airq_iv_alloc()
245 bit = find_next_bit_inv(iv->avail, iv->bits, bit + i + 1); in airq_iv_alloc()
247 if (bit + num > iv->bits) in airq_iv_alloc()
248 bit = -1UL; in airq_iv_alloc()
[all …]
/drivers/media/tuners/
Dmxl5005s.c237 u16 bit[25]; /* Array of bit pos in Reg Addr for each bit pos */ member
301 static void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit,
730 state->Init_Ctrl[0].bit[0] = 7; in MXL5005_ControlInit()
736 state->Init_Ctrl[1].bit[0] = 2; in MXL5005_ControlInit()
742 state->Init_Ctrl[2].bit[0] = 1; in MXL5005_ControlInit()
745 state->Init_Ctrl[2].bit[1] = 0; in MXL5005_ControlInit()
751 state->Init_Ctrl[3].bit[0] = 0; in MXL5005_ControlInit()
757 state->Init_Ctrl[4].bit[0] = 5; in MXL5005_ControlInit()
760 state->Init_Ctrl[4].bit[1] = 6; in MXL5005_ControlInit()
763 state->Init_Ctrl[4].bit[2] = 7; in MXL5005_ControlInit()
[all …]
/drivers/pinctrl/meson/
Dpinctrl-meson.c99 unsigned int *reg, unsigned int *bit) in meson_calc_reg_and_bit() argument
103 *bit = (desc->bit + pin - bank->first) * meson_bit_strides[reg_type]; in meson_calc_reg_and_bit()
104 *reg = (desc->reg + (*bit / 32)) * 4; in meson_calc_reg_and_bit()
105 *bit &= 0x1f; in meson_calc_reg_and_bit()
185 unsigned int reg, bit; in meson_pinconf_set_gpio_bit() local
192 meson_calc_reg_and_bit(bank, pin, reg_type, &reg, &bit); in meson_pinconf_set_gpio_bit()
193 return regmap_update_bits(pc->reg_gpio, reg, BIT(bit), in meson_pinconf_set_gpio_bit()
194 arg ? BIT(bit) : 0); in meson_pinconf_set_gpio_bit()
202 unsigned int reg, bit, val; in meson_pinconf_get_gpio_bit() local
209 meson_calc_reg_and_bit(bank, pin, reg_type, &reg, &bit); in meson_pinconf_get_gpio_bit()
[all …]
/drivers/net/ethernet/mellanox/mlxsw/
Dspectrum2_kvdl.c61 unsigned int bit; in mlxsw_sp2_kvdl_part_find_zero_bits() local
68 bit = start_bit; in mlxsw_sp2_kvdl_part_find_zero_bits()
70 bit = find_next_zero_bit(part->usage, part->usage_bit_count, bit); in mlxsw_sp2_kvdl_part_find_zero_bits()
71 if (!wrap && bit + bit_count >= part->usage_bit_count) { in mlxsw_sp2_kvdl_part_find_zero_bits()
73 bit = 0; in mlxsw_sp2_kvdl_part_find_zero_bits()
76 if (wrap && bit + bit_count >= start_bit) in mlxsw_sp2_kvdl_part_find_zero_bits()
79 if (test_bit(bit + i, part->usage)) { in mlxsw_sp2_kvdl_part_find_zero_bits()
80 bit += bit_count; in mlxsw_sp2_kvdl_part_find_zero_bits()
84 *p_bit = bit; in mlxsw_sp2_kvdl_part_find_zero_bits()
93 unsigned int bit; in mlxsw_sp2_kvdl_part_alloc() local
[all …]
/drivers/net/wireguard/
Dallowedips.c63 push_rcu(stack, node->bit[0], &len); in root_free_rcu()
64 push_rcu(stack, node->bit[1], &len); in root_free_rcu()
75 push_rcu(stack, node->bit[0], &len); in root_remove_peer_lists()
76 push_rcu(stack, node->bit[1], &len); in root_remove_peer_lists()
121 node = rcu_dereference_bh(node->bit[choose(node, key)]); in find_node()
163 node = rcu_dereference_protected(parent->bit[choose(parent, key)], lockdep_is_held(lock)); in node_placement()
169 static inline void connect_node(struct allowedips_node __rcu **parent, u8 bit, struct allowedips_no… in connect_node() argument
171 node->parent_bit_packed = (unsigned long)parent | bit; in connect_node()
177 u8 bit = choose(parent, node->bits); in choose_and_connect_node() local
178 connect_node(&parent->bit[bit], bit, node); in choose_and_connect_node()
[all …]
/drivers/hwmon/
Demc1403.c169 static SENSOR_DEVICE_ATTR_2_RO(temp1_min_alarm, bit, 0x36, 0x01);
170 static SENSOR_DEVICE_ATTR_2_RO(temp1_max_alarm, bit, 0x35, 0x01);
171 static SENSOR_DEVICE_ATTR_2_RO(temp1_crit_alarm, bit, 0x37, 0x01);
180 static SENSOR_DEVICE_ATTR_2_RO(temp2_fault, bit, 0x1b, 0x02);
181 static SENSOR_DEVICE_ATTR_2_RO(temp2_min_alarm, bit, 0x36, 0x02);
182 static SENSOR_DEVICE_ATTR_2_RO(temp2_max_alarm, bit, 0x35, 0x02);
183 static SENSOR_DEVICE_ATTR_2_RO(temp2_crit_alarm, bit, 0x37, 0x02);
192 static SENSOR_DEVICE_ATTR_2_RO(temp3_fault, bit, 0x1b, 0x04);
193 static SENSOR_DEVICE_ATTR_2_RO(temp3_min_alarm, bit, 0x36, 0x04);
194 static SENSOR_DEVICE_ATTR_2_RO(temp3_max_alarm, bit, 0x35, 0x04);
[all …]
/drivers/pinctrl/renesas/
Dpinctrl-rzg2l.c468 u32 cfg, u32 port, u8 bit) in rzg2l_validate_gpio_pin() argument
474 if (bit >= pincount || port >= pctrl->data->n_port_pins) in rzg2l_validate_gpio_pin()
485 u8 bit, u32 mask) in rzg2l_read_pin_config() argument
490 if (bit >= 4) { in rzg2l_read_pin_config()
491 bit -= 4; in rzg2l_read_pin_config()
495 return (readl(addr) >> (bit * 8)) & mask; in rzg2l_read_pin_config()
499 u8 bit, u32 mask, u32 val) in rzg2l_rmw_pin_config() argument
506 if (bit >= 4) { in rzg2l_rmw_pin_config()
507 bit -= 4; in rzg2l_rmw_pin_config()
512 reg = readl(addr) & ~(mask << (bit * 8)); in rzg2l_rmw_pin_config()
[all …]

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