| /drivers/clk/ |
| D | clk-gate.c | 71 reg = BIT(gate->bit_idx + 16); in clk_gate_endisable()
73 reg |= BIT(gate->bit_idx); in clk_gate_endisable()
78 reg |= BIT(gate->bit_idx); in clk_gate_endisable()
80 reg &= ~BIT(gate->bit_idx); in clk_gate_endisable()
112 reg ^= BIT(gate->bit_idx); in clk_gate_is_enabled()
114 reg &= BIT(gate->bit_idx); in clk_gate_is_enabled()
132 void __iomem *reg, u8 bit_idx, in __clk_hw_register_gate() argument
141 if (bit_idx > 15) { in __clk_hw_register_gate()
165 gate->bit_idx = bit_idx; in __clk_hw_register_gate()
187 void __iomem *reg, u8 bit_idx, in clk_register_gate() argument
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| D | clk-stm32f4.c | 49 u8 bit_idx; member
410 u8 bit_idx; member
420 if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx)) in clk_apb_mul_recalc_rate()
432 if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx)) in clk_apb_mul_round_rate()
464 unsigned long flags, u8 bit_idx) in clk_register_apb_mul() argument
474 am->bit_idx = bit_idx; in clk_register_apb_mul()
539 u8 bit_idx; member
811 pll->gate.bit_idx = vco->bit_idx; in stm32f4_rcc_register_pll()
817 pll->status = (readl(base + STM32F4_RCC_CR) >> vco->bit_idx) & 0x1; in stm32f4_rcc_register_pll()
959 void __iomem *reg, u8 bit_idx, u8 bit_rdy_idx, in clk_register_rgate() argument
[all …]
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| D | clk-stm32h7.c | 217 void __iomem *reg, u8 bit_idx, u8 bit_rdy, in clk_register_ready_gate() argument
238 rgate->gate.bit_idx = bit_idx; in clk_register_ready_gate()
253 u8 bit_idx; member
332 static struct clk_gate *_get_cgate(void __iomem *reg, u8 bit_idx, u32 flags, in _get_cgate() argument
342 gate->bit_idx = bit_idx; in _get_cgate()
402 cfg->gate->bit_idx, in get_cfg_composite_div()
593 u8 bit_idx; member
603 .bit_idx = _bit_idx,\
622 u8 bit_idx; member
637 .bit_idx = 24,
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| /drivers/net/wireless/ath/wcn36xx/ |
| D | firmware.c | 84 int arr_idx, bit_idx; in wcn36xx_firmware_set_feat_caps() local
92 bit_idx = cap % 32; in wcn36xx_firmware_set_feat_caps()
93 bitmap[arr_idx] |= (1 << bit_idx); in wcn36xx_firmware_set_feat_caps()
99 int arr_idx, bit_idx; in wcn36xx_firmware_get_feat_caps() local
107 bit_idx = cap % 32; in wcn36xx_firmware_get_feat_caps()
109 return (bitmap[arr_idx] & (1 << bit_idx)) ? 1 : 0; in wcn36xx_firmware_get_feat_caps()
115 int arr_idx, bit_idx; in wcn36xx_firmware_clear_feat_caps() local
123 bit_idx = cap % 32; in wcn36xx_firmware_clear_feat_caps()
124 bitmap[arr_idx] &= ~(1 << bit_idx); in wcn36xx_firmware_clear_feat_caps()
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| /drivers/xen/events/ |
| D | events_2l.c | 170 int word_idx, bit_idx; in evtchn_2l_handle_events() local
180 bit_idx = evtchn % BITS_PER_LONG; in evtchn_2l_handle_events()
181 if (active_evtchns(cpu, s, word_idx) & (1ULL << bit_idx)) in evtchn_2l_handle_events()
207 bit_idx = 0; in evtchn_2l_handle_events()
213 bit_idx = 0; /* usually scan entire word from start */ in evtchn_2l_handle_events()
228 bit_idx = start_bit_idx; in evtchn_2l_handle_events()
235 bits = MASK_LSBS(pending_bits, bit_idx); in evtchn_2l_handle_events()
241 bit_idx = EVTCHN_FIRST_BIT(bits); in evtchn_2l_handle_events()
244 port = (word_idx * BITS_PER_EVTCHN_WORD) + bit_idx; in evtchn_2l_handle_events()
247 bit_idx = (bit_idx + 1) % BITS_PER_EVTCHN_WORD; in evtchn_2l_handle_events()
[all …]
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| /drivers/clk/imx/ |
| D | clk-gate2.c | 31 u8 bit_idx; member
47 reg &= ~(gate->cgr_mask << gate->bit_idx); in clk_gate2_do_shared_clks()
49 reg |= (gate->cgr_val & gate->cgr_mask) << gate->bit_idx; in clk_gate2_do_shared_clks()
89 static int clk_gate2_reg_is_enabled(void __iomem *reg, u8 bit_idx, in clk_gate2_reg_is_enabled() argument
94 if (((val >> bit_idx) & cgr_mask) == cgr_val) in clk_gate2_reg_is_enabled()
108 ret = clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx, in clk_gate2_is_enabled()
138 void __iomem *reg, u8 bit_idx, u8 cgr_val, u8 cgr_mask, in clk_hw_register_gate2() argument
153 gate->bit_idx = bit_idx; in clk_hw_register_gate2()
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| D | clk-lpcg-scu.c | 35 u8 bit_idx; member
53 reg &= ~(CLK_GATE_SCU_LPCG_MASK << clk->bit_idx); in clk_lpcg_scu_enable()
59 reg |= val << clk->bit_idx; in clk_lpcg_scu_enable()
76 reg &= ~(CLK_GATE_SCU_LPCG_MASK << clk->bit_idx); in clk_lpcg_scu_disable()
89 void __iomem *reg, u8 bit_idx, bool hw_gate) in __imx_clk_lpcg_scu() argument
101 clk->bit_idx = bit_idx; in __imx_clk_lpcg_scu()
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| D | clk-gate-93.c | 38 u32 bit_idx; member
58 val &= ~(gate->mask << gate->bit_idx); in imx93_clk_gate_do_hardware()
60 val |= (gate->val & gate->mask) << gate->bit_idx; in imx93_clk_gate_do_hardware()
111 if (((val >> gate->bit_idx) & gate->mask) == gate->val) in imx93_clk_gate_reg_is_enabled()
158 unsigned long flags, void __iomem *reg, u32 bit_idx, u32 val, in imx93_clk_gate() argument
173 gate->bit_idx = bit_idx; in imx93_clk_gate()
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| D | clk-scu.h | 44 void __iomem *reg, u8 bit_idx, bool hw_gate);
65 void __iomem *reg, u8 bit_idx, bool hw_gate) in imx_clk_lpcg_scu_dev() argument
68 bit_idx, hw_gate); in imx_clk_lpcg_scu_dev()
73 u8 bit_idx, bool hw_gate) in imx_clk_lpcg_scu() argument
76 bit_idx, hw_gate); in imx_clk_lpcg_scu()
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| /drivers/clk/hisilicon/ |
| D | clkgate-separated.c | 27 u8 bit_idx; /* bits in enable/disable register */ member
41 reg = BIT(sclk->bit_idx); in clkgate_separated_enable()
58 reg = BIT(sclk->bit_idx); in clkgate_separated_disable()
72 reg &= BIT(sclk->bit_idx); in clkgate_separated_is_enabled()
86 void __iomem *reg, u8 bit_idx, in hisi_register_clkgate_sep() argument
104 sclk->bit_idx = bit_idx; in hisi_register_clkgate_sep()
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| /drivers/clk/meson/ |
| D | a1-peripherals.c | 23 .bit_idx = 0,
38 .bit_idx = 1,
53 .bit_idx = 2,
68 .bit_idx = 3,
83 .bit_idx = 4,
98 .bit_idx = 5,
113 .bit_idx = 6,
128 .bit_idx = 31,
193 .bit_idx = 24,
227 .bit_idx = 30,
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| D | axg.c | 340 .bit_idx = 27,
367 .bit_idx = 28,
405 .bit_idx = 29,
431 .bit_idx = 30,
459 .bit_idx = 31,
525 .bit_idx = 14,
576 .bit_idx = 14,
632 .bit_idx = 14,
683 .bit_idx = 0,
833 .bit_idx = 4,
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| D | meson8b.c | 333 .bit_idx = 27,
361 .bit_idx = 28,
389 .bit_idx = 29,
417 .bit_idx = 30,
445 .bit_idx = 31,
510 .bit_idx = 14,
555 .bit_idx = 14,
600 .bit_idx = 14,
657 .bit_idx = 7,
839 .bit_idx = 8,
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| D | gxbb.c | 574 .bit_idx = 27,
601 .bit_idx = 28,
639 .bit_idx = 29,
665 .bit_idx = 30,
691 .bit_idx = 31,
778 .bit_idx = 14,
830 .bit_idx = 14,
873 .bit_idx = 14,
935 .bit_idx = 7,
986 .bit_idx = 8,
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| D | g12a-aoclk.c | 50 .bit_idx = (_bit), \
82 .bit_idx = 14,
109 .bit_idx = 31,
182 .bit_idx = 30,
200 .bit_idx = 31,
273 .bit_idx = 30,
361 .bit_idx = 8,
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| D | g12a.c | 222 .bit_idx = 24,
239 .bit_idx = 24,
295 .bit_idx = 24,
332 .bit_idx = 20,
1136 .bit_idx = 1,
1155 .bit_idx = 1,
1215 .bit_idx = 1,
1249 .bit_idx = 17,
1283 .bit_idx = 18,
1327 .bit_idx = 23,
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| D | axg-aoclk.c | 41 .bit_idx = (_bit), \
65 .bit_idx = 14,
80 .bit_idx = 31,
163 .bit_idx = 30,
251 .bit_idx = 8,
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| D | a1-pll.c | 65 .bit_idx = 20,
157 .bit_idx = 21,
195 .bit_idx = 22,
228 .bit_idx = 23,
261 .bit_idx = 24,
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| D | clk-regmap.c | 18 return regmap_update_bits(clk->map, gate->offset, BIT(gate->bit_idx), in clk_regmap_gate_endisable()
19 set ? BIT(gate->bit_idx) : 0); in clk_regmap_gate_endisable()
40 val ^= BIT(gate->bit_idx); in clk_regmap_gate_is_enabled()
42 val &= BIT(gate->bit_idx); in clk_regmap_gate_is_enabled()
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| D | gxbb-aoclk.c | 30 .bit_idx = (_bit), \
53 .bit_idx = 6,
68 .bit_idx = 31,
147 .bit_idx = 30,
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| /drivers/clk/actions/ |
| D | owl-gate.c | 27 reg |= BIT(gate_hw->bit_idx); in owl_gate_set()
29 reg &= ~BIT(gate_hw->bit_idx); in owl_gate_set()
60 reg ^= BIT(gate_hw->bit_idx); in owl_gate_clk_is_enabled()
62 return !!(reg & BIT(gate_hw->bit_idx)); in owl_gate_clk_is_enabled()
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| D | owl-gate.h | 18 u8 bit_idx; member
30 .bit_idx = _bit_idx, \
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| /drivers/clk/mvebu/ |
| D | cp110-system-controller.c | 116 u8 bit_idx; member
126 BIT(gate->bit_idx), BIT(gate->bit_idx)); in cp110_gate_enable()
136 BIT(gate->bit_idx), 0); in cp110_gate_disable()
146 return val & BIT(gate->bit_idx); in cp110_gate_is_enabled()
157 struct regmap *regmap, u8 bit_idx) in cp110_register_gate() argument
176 gate->bit_idx = bit_idx; in cp110_register_gate()
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| /drivers/mmc/host/ |
| D | meson-mx-sdhc-clkc.c | 115 clkc_data->mod_clk_en.bit_idx = 15; in meson_mx_sdhc_register_clkc()
123 clkc_data->tx_clk_en.bit_idx = 14; in meson_mx_sdhc_register_clkc()
131 clkc_data->rx_clk_en.bit_idx = 13; in meson_mx_sdhc_register_clkc()
139 clkc_data->sd_clk_en.bit_idx = 12; in meson_mx_sdhc_register_clkc()
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| /drivers/clk/ralink/ |
| D | clk-mt7621.c | 58 u32 bit_idx; member
67 .bit_idx = _shift \
104 clk_gate->bit_idx, clk_gate->bit_idx); in mt7621_gate_enable()
112 regmap_update_bits(sysc, SYSC_REG_CLKCFG1, clk_gate->bit_idx, 0); in mt7621_gate_disable()
124 return val & clk_gate->bit_idx; in mt7621_gate_is_enabled()
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