Searched refs:cascade (Results 1 – 7 of 7) sorted by relevance
94 u8 val = readb(docg3->cascade->base + reg); in doc_readb()102 u16 val = readw(docg3->cascade->base + reg); in doc_readw()110 writeb(val, docg3->cascade->base + reg); in doc_writeb()116 writew(val, docg3->cascade->base + reg); in doc_writew()650 numerrs = bch_decode(docg3->cascade->bch, NULL, in doc_ecc_bch_fix_data()898 mutex_lock(&docg3->cascade->lock); in doc_read_oob()977 mutex_unlock(&docg3->cascade->lock); in doc_read_oob()1199 mutex_lock(&docg3->cascade->lock); in doc_erase()1207 mutex_unlock(&docg3->cascade->lock); in doc_erase()1436 mutex_lock(&docg3->cascade->lock); in doc_write_oob()[all …]
291 struct docg3_cascade *cascade; member
406 parent_irq[0] = irq_create_mapping(parent, acpi_liointc->cascade[0]); in liointc_acpi_init()407 parent_irq[1] = irq_create_mapping(parent, acpi_liointc->cascade[1]); in liointc_acpi_init()
210 fwspec.param[0] = acpi_pchlpc->cascade + GSI_MIN_PCH_IRQ; in pch_lpc_acpi_init()
312 parent_irq[i] = irq_create_mapping(parent, acpi_htvec->cascade[i]); in htvec_acpi_init()
438 parent_irq = irq_create_mapping(parent, acpi_eiointc->cascade); in eiointc_acpi_init()
618 XWAY SoC. The STP allows the SoC to drive a shift registers cascade,