| /drivers/gpu/drm/i915/display/ |
| D | intel_cdclk.c | 78 u8 (*calc_voltage_level)(int cdclk);
84 dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config); in intel_cdclk_get_cdclk()
91 dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe); in intel_cdclk_set_cdclk()
97 return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(cdclk_config); in intel_cdclk_modeset_calc_cdclk()
101 int cdclk) in intel_cdclk_calc_voltage_level() argument
103 return dev_priv->display.funcs.cdclk->calc_voltage_level(cdclk); in intel_cdclk_calc_voltage_level()
109 cdclk_config->cdclk = 133333; in fixed_133mhz_get_cdclk()
115 cdclk_config->cdclk = 200000; in fixed_200mhz_get_cdclk()
121 cdclk_config->cdclk = 266667; in fixed_266mhz_get_cdclk()
127 cdclk_config->cdclk = 333333; in fixed_333mhz_get_cdclk()
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| D | intel_cdclk.h | 19 unsigned int cdclk, vco, ref, bypass; member
83 …k_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->display.cdclk.obj))
85 …k_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->display.cdclk.obj))
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| D | intel_audio.c | 427 unsigned int fec_coeff, cdclk, vdsc_bpp; in calc_hblank_early_prog() local
435 cdclk = i915->display.cdclk.hw.cdclk; in calc_hblank_early_prog()
443 h_active, link_clk, lanes, vdsc_bpp, cdclk); in calc_hblank_early_prog()
445 if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bpp || !cdclk)) in calc_hblank_early_prog()
454 hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk), in calc_hblank_early_prog()
455 mul_u32_u32(link_clk, cdclk)); in calc_hblank_early_prog()
887 static void get_aud_ts_cdclk_m_n(int refclk, int cdclk, struct aud_ts_cdclk_m_n *aud_ts) in get_aud_ts_cdclk_m_n() argument
890 aud_ts->n = cdclk * aud_ts->m / 24000; in get_aud_ts_cdclk_m_n()
898 get_aud_ts_cdclk_m_n(i915->display.cdclk.hw.ref, i915->display.cdclk.hw.cdclk, &aud_ts); in intel_audio_cdclk_change_post()
1044 return i915->display.cdclk.hw.cdclk; in i915_audio_component_get_cdclk_freq()
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| D | intel_display_driver.c | 86 cdclk_state = to_intel_cdclk_state(i915->display.cdclk.obj.state); in intel_display_driver_init_hw()
89 intel_cdclk_dump_config(i915, &i915->display.cdclk.hw, "Current CDCLK"); in intel_display_driver_init_hw()
90 cdclk_state->logical = cdclk_state->actual = i915->display.cdclk.hw; in intel_display_driver_init_hw()
314 if (i915->display.cdclk.max_cdclk_freq == 0) in intel_display_driver_probe_nogem()
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| D | intel_display_core.h | 276 const struct intel_cdclk_funcs *cdclk; member
334 } cdclk; member
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| D | hsw_ips.c | 209 crtc_state->pixel_rate > i915->display.cdclk.max_cdclk_freq * 95 / 100) in hsw_crtc_state_ips_capable()
248 if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100) in hsw_ips_compute_config()
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| D | intel_pmdemand.c | 292 (new_cdclk_state->actual.cdclk != in intel_pmdemand_needs_update()
293 old_cdclk_state->actual.cdclk || in intel_pmdemand_needs_update()
348 DIV_ROUND_UP(new_cdclk_state->actual.cdclk, 1000); in intel_pmdemand_atomic_check()
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| D | intel_dp_aux.c | 89 freq = dev_priv->display.cdclk.hw.cdclk; in ilk_get_aux_clock_divider()
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| D | intel_modeset_setup.c | 158 to_intel_cdclk_state(i915->display.cdclk.obj.state); in intel_crtc_disable_noatomic_complete()
678 to_intel_cdclk_state(i915->display.cdclk.obj.state); in intel_modeset_readout_hw_state()
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| D | intel_backlight.c | 1095 clock = KHz(i915->display.cdclk.hw.cdclk); in i9xx_hz_to_pwm()
1113 clock = KHz(i915->display.cdclk.hw.cdclk); in i965_hz_to_pwm()
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| D | intel_fbc.c | 1167 if (crtc_state->pixel_rate >= cdclk_state->logical.cdclk * 95 / 100) { in intel_fbc_check_plane()
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| D | intel_display_power_well.c | 982 intel_cdclk_needs_modeset(&dev_priv->display.cdclk.hw, in gen9_disable_dc_states()
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| D | intel_dpll_mgr.c | 1873 i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref; in skl_update_dpll_ref_clks()
3945 i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref; in icl_update_dpll_ref_clks()
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| D | intel_display_power.c | 1367 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); in hsw_restore_lcpll()
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| D | intel_dp.c | 796 i915->display.cdclk.max_cdclk_freq * 48 / in intel_dp_dsc_get_output_bpp()
830 if (mode_clock >= ((i915->display.cdclk.max_cdclk_freq * 85) / 100)) in intel_dp_dsc_get_slice_count()
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| D | intel_display.c | 2305 clock_limit = i915->display.cdclk.max_cdclk_freq * 9 / 10; in intel_crtc_compute_pipe_mode()
4207 cdclk_state->logical.cdclk); in hsw_ips_linetime_wm()
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| /drivers/clk/samsung/ |
| D | clk-s5pv210-audss.c | 70 struct clk *hclk, *pll_ref, *pll_in, *cdclk, *sclk_audio; in s5pv210_audss_clk_probe() local
105 cdclk = devm_clk_get(&pdev->dev, "iiscdclk0"); in s5pv210_audss_clk_probe()
119 if (!IS_ERR(cdclk)) in s5pv210_audss_clk_probe()
120 mout_i2s_p[1] = __clk_get_name(cdclk); in s5pv210_audss_clk_probe()
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| D | clk-exynos-audss.c | 128 struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in; in exynos_audss_clk_probe() local
188 cdclk = devm_clk_get(dev, "cdclk"); in exynos_audss_clk_probe()
190 if (!IS_ERR(cdclk)) in exynos_audss_clk_probe()
191 mout_i2s_p[1] = __clk_get_name(cdclk); in exynos_audss_clk_probe()
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| /drivers/gpu/drm/i915/gt/ |
| D | intel_gt_pm_debugfs.c | 396 drm_printf(p, "Current CD clock frequency: %d kHz\n", i915->display.cdclk.hw.cdclk); in intel_gt_pm_frequency_dump()
397 drm_printf(p, "Max CD clock frequency: %d kHz\n", i915->display.cdclk.max_cdclk_freq); in intel_gt_pm_frequency_dump()
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| /drivers/gpu/drm/i915/ |
| D | i915_reg.h | 5399 #define DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, num_pipes, voltage_level) \ argument
5400 ((DISPLAY_TO_PCODE_CDCLK(cdclk)) | \
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