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Searched refs:clk_out (Results 1 – 14 of 14) sorted by relevance

/drivers/clk/
Dclk-versaclock5.c198 struct vc5_out_data clk_out[VC5_MAX_CLK_OUT_NUM]; member
743 return &vc5->clk_out[idx].hw; in vc5_of_clk_get()
764 struct vc5_out_data *clk_out) in vc5_update_mode() argument
769 clk_out->clk_output_cfg0_mask |= VC5_CLK_OUTPUT_CFG0_CFG_MASK; in vc5_update_mode()
778 clk_out->clk_output_cfg0 |= in vc5_update_mode()
789 struct vc5_out_data *clk_out) in vc5_update_power() argument
795 clk_out->clk_output_cfg0_mask |= VC5_CLK_OUTPUT_CFG0_PWR_MASK; in vc5_update_power()
798 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_PWR_18; in vc5_update_power()
801 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_PWR_25; in vc5_update_power()
804 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_PWR_33; in vc5_update_power()
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Dclk-versaclock3.c211 static struct clk_hw *clk_out[6]; variable
987 if (idx >= ARRAY_SIZE(clk_out)) { in vc3_of_clk_get()
1083 for (i = 0; i < ARRAY_SIZE(clk_out); i++) { in vc3_probe()
1108 clk_out[i] = devm_clk_hw_register_fixed_factor_index(dev, in vc3_probe()
1111 clk_out[i] = devm_clk_hw_register_fixed_factor_parent_hw(dev, in vc3_probe()
1114 if (IS_ERR(clk_out[i])) in vc3_probe()
1115 return PTR_ERR(clk_out[i]); in vc3_probe()
1118 ret = devm_of_clk_add_hw_provider(dev, vc3_of_clk_get, clk_out); in vc3_probe()
Dclk-versaclock7.c163 struct vc7_out_data clk_out[VC7_NUM_OUT]; member
186 return &vc7->clk_out[idx].hw; in vc7_of_clk_get()
702 vc7->clk_out[idx].out_dis = val & VC7_REG_OUT_DIS; in vc7_read_output()
716 vc7->clk_out[idx].out_dis); in vc7_write_output()
1212 vc7->clk_out[i].num = i; in vc7_probe()
1213 vc7->clk_out[i].vc7 = vc7; in vc7_probe()
1214 vc7->clk_out[i].hw.init = &clk_init; in vc7_probe()
1215 ret = devm_clk_hw_register(&client->dev, &vc7->clk_out[i].hw); in vc7_probe()
/drivers/clk/zynqmp/
Dclkc.c592 char *clk_out[MAX_NODES]; in zynqmp_register_clk_topology() local
606 clk_out[j] = kasprintf(GFP_KERNEL, "%s%s", clk_name, in zynqmp_register_clk_topology()
609 clk_out[j] = kasprintf(GFP_KERNEL, "%s", clk_name); in zynqmp_register_clk_topology()
615 hw = (*clk_topology[nodes[j].type])(clk_out[j], clk_dev_id, in zynqmp_register_clk_topology()
624 parent_names[0] = clk_out[j]; in zynqmp_register_clk_topology()
628 kfree(clk_out[j]); in zynqmp_register_clk_topology()
/drivers/media/dvb-frontends/
Dts2020.c30 u8 clk_out:2; member
112 switch (priv->clk_out) { in ts2020_init()
585 dev->clk_out = pdata->clk_out; in ts2020_probe()
642 switch (dev->clk_out) { in ts2020_probe()
Dts2020.h30 u8 clk_out:2; member
Dm88ds3103.h71 enum m88ds3103_clock_out clk_out; member
Dm88ds3103.c1681 pdata.clk_out = cfg->clock_out; in m88ds3103_attach()
1785 dev->config.clock_out = pdata->clk_out; in m88ds3103_probe()
/drivers/media/usb/dvb-usb-v2/
Ddvbsky.c285 m88ds3103_pdata.clk_out = 0; in dvbsky_s960_attach()
388 m88ds3103_pdata.clk_out = 0; in dvbsky_s960c_attach()
/drivers/gpu/drm/tegra/
Dsor.c417 struct clk *clk_out; member
506 err = clk_set_parent(sor->clk_out, parent); in tegra_sor_set_parent_clock()
3842 sor->clk_out = devm_clk_get(&pdev->dev, name); in tegra_sor_probe()
3843 if (IS_ERR(sor->clk_out)) { in tegra_sor_probe()
3844 err = PTR_ERR(sor->clk_out); in tegra_sor_probe()
3851 sor->clk_out = sor->clk; in tegra_sor_probe()
3899 err = clk_set_parent(sor->clk_out, sor->clk_safe); in tegra_sor_probe()
/drivers/ufs/host/
Dufs-qcom.c205 const char *name, struct clk **clk_out, bool optional) in ufs_qcom_host_clk_get() argument
212 *clk_out = clk; in ufs_qcom_host_clk_get()
219 *clk_out = NULL; in ufs_qcom_host_clk_get()
Dufs-mediatek.c464 struct clk **clk_out) in ufs_mtk_get_host_clk() argument
473 *clk_out = clk; in ufs_mtk_get_host_clk()
/drivers/media/usb/dvb-usb/
Ddw2102.c1668 m88ds3103_pdata.clk_out = M88DS3103_CLOCK_OUT_ENABLED; in tt_s2_4600_frontend_attach()
/drivers/media/pci/cx23885/
Dcx23885-dvb.c2098 m88ds3103_pdata.clk_out = M88DS3103_CLOCK_OUT_DISABLED; in dvb_register()