| /drivers/clk/mxs/ |
| D | clk-pll.c | 23 struct clk_pll { struct
30 #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw) argument
34 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_prepare()
45 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_unprepare()
52 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_enable()
61 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_disable()
69 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_recalc_rate()
85 struct clk_pll *pll; in mxs_clk_pll()
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| /drivers/clk/at91/ |
| D | clk-pll.c | 32 #define to_clk_pll(hw) container_of(hw, struct clk_pll, hw)
34 struct clk_pll { struct
57 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_prepare() argument
100 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_is_prepared()
107 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_unprepare()
116 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_recalc_rate()
124 static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate, in clk_pll_get_best_div_mul()
237 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_round_rate()
246 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_set_rate()
266 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_save_context()
[all …]
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| /drivers/clk/qcom/ |
| D | clk-pll.c | 26 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_enable()
67 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_disable()
82 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_recalc_rate()
128 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_determine_rate()
143 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_set_rate()
179 static int wait_for_pll(struct clk_pll *pll) in wait_for_pll()
203 struct clk_pll *p = to_clk_pll(clk_hw_get_parent(hw)); in clk_pll_vote_enable()
218 static void clk_pll_configure(struct clk_pll *pll, struct regmap *regmap, in clk_pll_configure()
245 void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap, in clk_pll_configure_sr()
254 void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap, in clk_pll_configure_sr_hpm_lp()
[all …]
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| D | clk-pll.h | 39 struct clk_pll { struct
59 #define to_clk_pll(_hw) container_of(to_clk_regmap(_hw), struct clk_pll, clkr) argument
76 void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap,
78 void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap,
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| D | a53-pll.c | 93 struct clk_pll *pll; in qcom_a53pll_probe()
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| D | gcc-msm8939.c | 52 static struct clk_pll gpll0 = {
83 static struct clk_pll gpll1 = {
114 static struct clk_pll gpll2 = {
145 static struct clk_pll bimc_pll = {
176 static struct clk_pll gpll3 = {
223 static struct clk_pll gpll4 = {
269 static struct clk_pll gpll5 = {
300 static struct clk_pll gpll6 = {
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| D | gcc-ipq806x.c | 32 static struct clk_pll pll0 = {
61 static struct clk_pll pll3 = {
90 static struct clk_pll pll8 = {
197 static struct clk_pll pll14 = {
242 static struct clk_pll pll18 = {
261 static struct clk_pll pll11 = {
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| D | gcc-mdm9615.c | 47 static struct clk_pll pll0 = {
89 static struct clk_pll pll8 = {
118 static struct clk_pll pll14 = {
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| D | lcc-ipq806x.c | 26 static struct clk_pll pll4 = {
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| D | mmcc-apq8084.c | 43 static struct clk_pll mmpll0 = {
74 static struct clk_pll mmpll1 = {
105 static struct clk_pll mmpll2 = {
122 static struct clk_pll mmpll3 = {
140 static struct clk_pll mmpll4 = {
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| D | lcc-msm8960.c | 29 static struct clk_pll pll4 = {
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| D | mmcc-msm8974.c | 44 static struct clk_pll mmpll0 = {
75 static struct clk_pll mmpll1 = {
106 static struct clk_pll mmpll2 = {
123 static struct clk_pll mmpll3 = {
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| /drivers/clk/ |
| D | clk-nomadik.c | 145 struct clk_pll { struct
164 #define to_pll(_hw) container_of(_hw, struct clk_pll, hw) argument
169 struct clk_pll *pll = to_pll(hw); in pll_clk_enable()
189 struct clk_pll *pll = to_pll(hw); in pll_clk_disable()
208 struct clk_pll *pll = to_pll(hw); in pll_clk_is_enabled()
224 struct clk_pll *pll = to_pll(hw); in pll_clk_recalc_rate()
264 struct clk_pll *pll; in pll_clk_register()
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| D | clk-versaclock3.c | 691 static struct vc3_hw_data clk_pll[] = { variable
750 { .hw = &clk_pll[VC3_PLL1].hw },
754 { .hw = &clk_pll[VC3_PLL2].hw },
755 { .hw = &clk_pll[VC3_PLL3].hw }
758 { .hw = &clk_pll[VC3_PLL2].hw },
836 &clk_pll[VC3_PLL1].hw
890 &clk_pll[VC3_PLL3].hw
1047 for (i = 0; i < ARRAY_SIZE(clk_pll); i++) { in vc3_probe()
1048 clk_pll[i].regmap = regmap; in vc3_probe()
1049 ret = devm_clk_hw_register(dev, &clk_pll[i].hw); in vc3_probe()
[all …]
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| D | clk-vt8500.c | 41 struct clk_pll { struct
308 #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
549 struct clk_pll *pll = to_clk_pll(hw); in vtwm_pll_set_rate()
600 struct clk_pll *pll = to_clk_pll(hw); in vtwm_pll_round_rate()
639 struct clk_pll *pll = to_clk_pll(hw); in vtwm_pll_recalc_rate()
677 struct clk_pll *pll_clk; in vtwm_pll_clk_init()
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| D | clk-versaclock5.c | 196 struct vc5_hw_data clk_pll; member
1101 vc5->clk_pll.num = 0; in vc5_probe()
1102 vc5->clk_pll.vc5 = vc5; in vc5_probe()
1103 vc5->clk_pll.hw.init = &init; in vc5_probe()
1104 ret = devm_clk_hw_register(&client->dev, &vc5->clk_pll.hw); in vc5_probe()
1122 parent_names[0] = clk_hw_get_name(&vc5->clk_pll.hw); in vc5_probe()
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| /drivers/clk/spear/ |
| D | clk-vco-pll.c | 63 #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
84 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_round_rate_index()
124 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_recalc_rate()
144 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_set_rate()
280 struct clk_pll *pll; in clk_register_vco_pll()
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| D | clk.h | 99 struct clk_pll { struct
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| /drivers/clk/keystone/ |
| D | pll.c | 68 struct clk_pll { struct
73 #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw) argument
78 struct clk_pll *pll = to_clk_pll(hw); in clk_pllclk_recalc()
126 struct clk_pll *pll; in clk_register_pll()
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| /drivers/gpu/drm/imx/ipuv3/ |
| D | imx-ldb.c | 103 struct clk *clk_pll[2]; /* upstream clock we can adjust */ member
172 clk_get_rate(ldb->clk_pll[chno]), serial_clk); in imx_ldb_set_clock()
173 clk_set_rate(ldb->clk_pll[chno], serial_clk); in imx_ldb_set_clock()
176 clk_get_rate(ldb->clk_pll[chno])); in imx_ldb_set_clock()
428 ldb->clk_pll[chno] = devm_clk_get(ldb->dev, clkname); in imx_ldb_get_clk()
430 return PTR_ERR_OR_ZERO(ldb->clk_pll[chno]); in imx_ldb_get_clk()
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| /drivers/staging/most/dim2/ |
| D | dim2.c | 92 struct clk *clk_pll; member
939 dev->clk_pll = devm_clk_get(&pdev->dev, "pll8_mlb"); in fsl_mx6_enable()
940 if (IS_ERR_OR_NULL(dev->clk_pll)) { in fsl_mx6_enable()
947 clk_prepare_enable(dev->clk_pll); in fsl_mx6_enable()
958 clk_disable_unprepare(dev->clk_pll); in fsl_mx6_disable()
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| /drivers/clk/mediatek/ |
| D | clk-pllfh.c | 24 return container_of(pll, struct mtk_fh, clk_pll); in to_mtk_fh()
169 hw = mtk_clk_register_pll_ops(&fh->clk_pll, pll_data, base, in mtk_clk_register_pllfh()
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| D | clk-pllfh.h | 58 struct mtk_clk_pll clk_pll; member
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| D | clk-fhctl.c | 187 struct mtk_clk_pll *pll = &fh->clk_pll; in fhctl_hopping()
217 struct mtk_clk_pll *pll = &fh->clk_pll; in fhctl_ssc_enable()
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| /drivers/clk/ti/ |
| D | fapll.c | 76 struct clk *clk_pll; member
515 synth->clk_pll = pll_clk; in ti_fapll_synth_setup()
|