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Searched refs:clkrate (Results 1 – 21 of 21) sorted by relevance

/drivers/w1/masters/
Dmxc_w1.c94 unsigned long clkrate; in mxc_w1_probe() local
111 clkrate = clk_get_rate(mdev->clk); in mxc_w1_probe()
112 if (clkrate < 10000000) in mxc_w1_probe()
116 clkdiv = DIV_ROUND_CLOSEST(clkrate, 1000000); in mxc_w1_probe()
117 clkrate /= clkdiv; in mxc_w1_probe()
118 if ((clkrate < 980000) || (clkrate > 1020000)) in mxc_w1_probe()
120 "Incorrect time base frequency %lu Hz\n", clkrate); in mxc_w1_probe()
/drivers/pwm/
Dpwm-apple.c37 u64 clkrate; member
57 on_cycles = mul_u64_u64_div_u64(fpwm->clkrate, in apple_pwm_apply()
62 off_cycles = mul_u64_u64_div_u64(fpwm->clkrate, in apple_pwm_apply()
92 state->duty_cycle = DIV64_U64_ROUND_UP((u64)on_cycles * NSEC_PER_SEC, fpwm->clkrate); in apple_pwm_get_state()
94 NSEC_PER_SEC, fpwm->clkrate); in apple_pwm_get_state()
129 fpwm->clkrate = clk_get_rate(clk); in apple_pwm_probe()
130 if (fpwm->clkrate > NSEC_PER_SEC) in apple_pwm_probe()
Dpwm-atmel.c193 unsigned long clkrate, in atmel_pwm_calculate_cprd_and_pres() argument
202 cycles *= clkrate; in atmel_pwm_calculate_cprd_and_pres()
228 unsigned long clkrate, unsigned long cprd, in atmel_pwm_calculate_cdty() argument
233 cycles *= clkrate; in atmel_pwm_calculate_cdty()
305 unsigned long clkrate = clk_get_rate(atmel_pwm->clk); in atmel_pwm_apply() local
316 atmel_pwm_calculate_cdty(state, clkrate, cprd, pres, &cdty); in atmel_pwm_apply()
321 ret = atmel_pwm_calculate_cprd_and_pres(chip, clkrate, state, &cprd, in atmel_pwm_apply()
329 atmel_pwm_calculate_cdty(state, clkrate, cprd, pres, &cdty); in atmel_pwm_apply()
Dpwm-imx27.c224 unsigned long long clkrate; in pwm_imx27_apply() local
230 clkrate = clk_get_rate(imx->clk_per); in pwm_imx27_apply()
231 c = clkrate * state->period; in pwm_imx27_apply()
239 c = clkrate * state->duty_cycle; in pwm_imx27_apply()
/drivers/watchdog/
Dst_lpc_wdt.c47 unsigned long clkrate; member
83 unsigned long clkrate = st_wdog->clkrate; in st_wdog_load_timer() local
85 writel_relaxed(timeout * clkrate, st_wdog->base + LPC_LPA_LSB_OFF); in st_wdog_load_timer()
204 st_wdog->clkrate = clk_get_rate(st_wdog->clk); in st_wdog_probe()
206 if (!st_wdog->clkrate) { in st_wdog_probe()
210 st_wdog_dev.max_timeout = 0xFFFFFFFF / st_wdog->clkrate; in st_wdog_probe()
/drivers/i2c/busses/
Di2c-lpc2k.c350 u32 clkrate; in i2c_lpc2k_probe() local
390 clkrate = clk_get_rate(i2c->clk); in i2c_lpc2k_probe()
391 if (clkrate == 0) { in i2c_lpc2k_probe()
397 clkrate = clkrate / bus_clk_rate; in i2c_lpc2k_probe()
399 scl_high = (clkrate * I2C_STD_MODE_DUTY) / 100; in i2c_lpc2k_probe()
401 scl_high = (clkrate * I2C_FAST_MODE_DUTY) / 100; in i2c_lpc2k_probe()
403 scl_high = (clkrate * I2C_FAST_MODE_PLUS_DUTY) / 100; in i2c_lpc2k_probe()
406 writel(clkrate - scl_high, i2c->base + LPC24XX_I2SCLL); in i2c_lpc2k_probe()
Di2c-s3c2410.c108 unsigned long clkrate; member
834 i2c->clkrate = clkin; in s3c24xx_i2c_clockrate()
Di2c-omap.c1390 omap->speed = pdata->clkrate; in omap_i2c_probe()
/drivers/rtc/
Drtc-st-lpc.c45 unsigned long clkrate; member
96 do_div(lpt, rtc->clkrate); in st_rtc_read_time()
110 lpt = (unsigned long long)secs * rtc->clkrate; in st_rtc_set_time()
168 lpa = (unsigned long long)alarm_secs * rtc->clkrate; in st_rtc_set_alarm()
236 rtc->clkrate = clk_get_rate(rtc->clk); in st_rtc_probe()
237 if (!rtc->clkrate) { in st_rtc_probe()
248 do_div(rtc->rtc_dev->range_max, rtc->clkrate); in st_rtc_probe()
/drivers/mtd/nand/raw/
Dlpc32xx_mlc.c233 uint32_t clkrate, tmp; in lpc32xx_nand_setup() local
240 clkrate = clk_get_rate(host->clk); in lpc32xx_nand_setup()
241 if (clkrate == 0) in lpc32xx_nand_setup()
242 clkrate = 104000000; in lpc32xx_nand_setup()
258 tmp |= MLCTIMEREG_TCEA_DELAY(clkrate / host->ncfg->tcea_delay + 1); in lpc32xx_nand_setup()
259 tmp |= MLCTIMEREG_BUSY_DELAY(clkrate / host->ncfg->busy_delay + 1); in lpc32xx_nand_setup()
260 tmp |= MLCTIMEREG_NAND_TA(clkrate / host->ncfg->nand_ta + 1); in lpc32xx_nand_setup()
261 tmp |= MLCTIMEREG_RD_HIGH(clkrate / host->ncfg->rd_high + 1); in lpc32xx_nand_setup()
262 tmp |= MLCTIMEREG_RD_LOW(clkrate / host->ncfg->rd_low); in lpc32xx_nand_setup()
263 tmp |= MLCTIMEREG_WR_HIGH(clkrate / host->ncfg->wr_high + 1); in lpc32xx_nand_setup()
[all …]
Dlpc32xx_slc.c238 uint32_t clkrate, tmp; in lpc32xx_nand_setup() local
251 clkrate = clk_get_rate(host->clk); in lpc32xx_nand_setup()
252 if (clkrate == 0) in lpc32xx_nand_setup()
253 clkrate = LPC32XX_DEF_BUS_RATE; in lpc32xx_nand_setup()
257 SLCTAC_WWIDTH(clkrate, host->ncfg->wwidth) | in lpc32xx_nand_setup()
258 SLCTAC_WHOLD(clkrate, host->ncfg->whold) | in lpc32xx_nand_setup()
259 SLCTAC_WSETUP(clkrate, host->ncfg->wsetup) | in lpc32xx_nand_setup()
261 SLCTAC_RWIDTH(clkrate, host->ncfg->rwidth) | in lpc32xx_nand_setup()
262 SLCTAC_RHOLD(clkrate, host->ncfg->rhold) | in lpc32xx_nand_setup()
263 SLCTAC_RSETUP(clkrate, host->ncfg->rsetup); in lpc32xx_nand_setup()
Ds3c2410.c289 unsigned long clkrate = clk_get_rate(info->clk); in s3c2410_nand_setrate() local
295 info->clk_rate = clkrate; in s3c2410_nand_setrate()
296 clkrate /= 1000; /* turn clock into kHz for ease of use */ in s3c2410_nand_setrate()
299 tacls = s3c_nand_calc_rate(plat->tacls, clkrate, tacls_max); in s3c2410_nand_setrate()
300 twrph0 = s3c_nand_calc_rate(plat->twrph0, clkrate, 8); in s3c2410_nand_setrate()
301 twrph1 = s3c_nand_calc_rate(plat->twrph1, clkrate, 8); in s3c2410_nand_setrate()
315 tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate), in s3c2410_nand_setrate()
316 twrph1, to_ns(twrph1, clkrate)); in s3c2410_nand_setrate()
/drivers/spi/
Dspi-npcm-fiu.c242 unsigned long clkrate; member
252 unsigned long clkrate; member
561 if (fiu->clkrate != chip->clkrate) { in npcm_fiu_exec_op()
562 ret = clk_set_rate(fiu->clk, chip->clkrate); in npcm_fiu_exec_op()
565 chip->clkrate, fiu->clkrate); in npcm_fiu_exec_op()
567 fiu->clkrate = chip->clkrate; in npcm_fiu_exec_op()
676 chip->clkrate = spi->max_speed_hz; in npcm_fiu_setup()
678 fiu->clkrate = clk_get_rate(fiu->clk); in npcm_fiu_setup()
Dspi-fsl-dspi.c602 unsigned long clkrate) in hz_to_spi_baud() argument
613 scale_needed = clkrate / speed_hz; in hz_to_spi_baud()
614 if (clkrate % speed_hz) in hz_to_spi_baud()
632 speed_hz, clkrate); in hz_to_spi_baud()
639 unsigned long clkrate) in ns_delay_scale() argument
646 scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC, in ns_delay_scale()
666 delay_ns, clkrate); in ns_delay_scale()
1012 unsigned long clkrate; in dspi_setup() local
1049 clkrate = clk_get_rate(dspi->clk); in dspi_setup()
1050 hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate); in dspi_setup()
[all …]
/drivers/ata/
Dpata_imx.c59 unsigned long clkrate; in pata_imx_set_timing() local
62 clkrate = clk_get_rate(priv->clk); in pata_imx_set_timing()
65 !clkrate) in pata_imx_set_timing()
68 T = 1000000000 / clkrate; in pata_imx_set_timing()
/drivers/net/dsa/sja1105/
Dsja1105_ptp.c611 s64 clkrate; in sja1105_ptp_adjfine() local
614 clkrate = (s64)scaled_ppm * SJA1105_CC_MULT_NUM; in sja1105_ptp_adjfine()
615 clkrate = div_s64(clkrate, SJA1105_CC_MULT_DEM); in sja1105_ptp_adjfine()
618 clkrate = SJA1105_CC_MULT + clkrate; in sja1105_ptp_adjfine()
619 WARN_ON(abs(clkrate) >= GENMASK_ULL(31, 0)); in sja1105_ptp_adjfine()
620 clkrate32 = clkrate; in sja1105_ptp_adjfine()
/drivers/mmc/host/
Dpxamci.c55 unsigned long clkrate; member
174 clks = (unsigned long long)data->timeout_ns * host->clkrate; in pxamci_setup_data()
445 unsigned long rate = host->clkrate; in pxamci_set_ios()
663 host->clkrate = clk_get_rate(host->clk); in pxamci_probe()
668 mmc->f_min = (host->clkrate + 63) / 64; in pxamci_probe()
669 mmc->f_max = (mmc_has_26MHz()) ? 26000000 : host->clkrate; in pxamci_probe()
/drivers/gpu/ipu-v3/
Dipu-di.c440 unsigned long rate, clkrate; in ipu_di_config_clock() local
443 clkrate = clk_get_rate(di->clk_ipu); in ipu_di_config_clock()
444 div = DIV_ROUND_CLOSEST(clkrate, sig->mode.pixelclock); in ipu_di_config_clock()
446 rate = clkrate / div; in ipu_di_config_clock()
/drivers/mtd/spi-nor/controllers/
Dhisi-sfc.c84 u32 clkrate; member
155 ret = clk_set_rate(host->clk, priv->clkrate); in hisi_spi_nor_prep()
361 &priv->clkrate); in hisi_spi_nor_register()
/drivers/gpu/drm/arm/
Dhdlcd_drv.c212 unsigned long clkrate = clk_get_rate(hdlcd->clk); in hdlcd_show_pxlclock() local
215 seq_printf(m, "hw : %lu\n", clkrate); in hdlcd_show_pxlclock()
/drivers/gpu/drm/tiny/
Darcpgu.c344 unsigned long clkrate = clk_get_rate(arcpgu->clk); in arcpgu_show_pxlclock() local
347 seq_printf(m, "hw : %lu\n", clkrate); in arcpgu_show_pxlclock()