| /drivers/clk/imx/ |
| D | clk-imx8ulp.c | 149 struct clk_hw **clks; in imx8ulp_clk_cgc1_init() local
158 clks = clk_data->hws; in imx8ulp_clk_cgc1_init()
160 clks[IMX8ULP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8ulp_clk_cgc1_init()
167 …clks[IMX8ULP_CLK_SPLL2_PRE_SEL] = imx_clk_hw_mux_flags("spll2_pre_sel", base + 0x510, 0, 1, pll_pr… in imx8ulp_clk_cgc1_init()
168 …clks[IMX8ULP_CLK_SPLL3_PRE_SEL] = imx_clk_hw_mux_flags("spll3_pre_sel", base + 0x610, 0, 1, pll_pr… in imx8ulp_clk_cgc1_init()
170 …clks[IMX8ULP_CLK_SPLL2] = imx_clk_hw_pllv4(IMX_PLLV4_IMX8ULP_1GHZ, "spll2", "spll2_pre_sel", base … in imx8ulp_clk_cgc1_init()
171 …clks[IMX8ULP_CLK_SPLL3] = imx_clk_hw_pllv4(IMX_PLLV4_IMX8ULP, "spll3", "spll3_pre_sel", base + 0x6… in imx8ulp_clk_cgc1_init()
172 clks[IMX8ULP_CLK_SPLL3_VCODIV] = imx_clk_hw_divider("spll3_vcodiv", "spll3", base + 0x604, 0, 6); in imx8ulp_clk_cgc1_init()
174 …clks[IMX8ULP_CLK_SPLL3_PFD0] = imx_clk_hw_pfdv2(IMX_PFDV2_IMX8ULP, "spll3_pfd0", "spll3_vcodiv", b… in imx8ulp_clk_cgc1_init()
175 …clks[IMX8ULP_CLK_SPLL3_PFD1] = imx_clk_hw_pfdv2(IMX_PFDV2_IMX8ULP, "spll3_pfd1", "spll3_vcodiv", b… in imx8ulp_clk_cgc1_init()
[all …]
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| D | clk-imx93.c | 258 static struct clk_hw **clks; variable
275 clks = clk_hw_data->hws; in imx93_clocks_probe()
277 clks[IMX93_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx93_clocks_probe()
278 clks[IMX93_CLK_24M] = imx_get_clk_hw_by_name(np, "osc_24m"); in imx93_clocks_probe()
279 clks[IMX93_CLK_32K] = imx_get_clk_hw_by_name(np, "osc_32k"); in imx93_clocks_probe()
280 clks[IMX93_CLK_EXT1] = imx_get_clk_hw_by_name(np, "clk_ext1"); in imx93_clocks_probe()
282 clks[IMX93_CLK_SYS_PLL_PFD0] = imx_clk_hw_fixed("sys_pll_pfd0", 1000000000); in imx93_clocks_probe()
283 clks[IMX93_CLK_SYS_PLL_PFD0_DIV2] = imx_clk_hw_fixed_factor("sys_pll_pfd0_div2", in imx93_clocks_probe()
285 clks[IMX93_CLK_SYS_PLL_PFD1] = imx_clk_hw_fixed("sys_pll_pfd1", 800000000); in imx93_clocks_probe()
286 clks[IMX93_CLK_SYS_PLL_PFD1_DIV2] = imx_clk_hw_fixed_factor("sys_pll_pfd1_div2", in imx93_clocks_probe()
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| /drivers/clk/hisilicon/ |
| D | clk.c | 51 clk_data->clk_data.clks = clk_table; in hisi_clk_alloc()
80 clk_data->clk_data.clks = clk_table; in hisi_clk_init()
91 int hisi_clk_register_fixed_rate(const struct hisi_fixed_rate_clock *clks, in hisi_clk_register_fixed_rate() argument
98 clk = clk_register_fixed_rate(NULL, clks[i].name, in hisi_clk_register_fixed_rate()
99 clks[i].parent_name, in hisi_clk_register_fixed_rate()
100 clks[i].flags, in hisi_clk_register_fixed_rate()
101 clks[i].fixed_rate); in hisi_clk_register_fixed_rate()
104 __func__, clks[i].name); in hisi_clk_register_fixed_rate()
107 data->clk_data.clks[clks[i].id] = clk; in hisi_clk_register_fixed_rate()
114 clk_unregister_fixed_rate(data->clk_data.clks[clks[i].id]); in hisi_clk_register_fixed_rate()
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| D | clk-hisi-phase.c | 94 const struct hisi_phase_clock *clks, in clk_register_hisi_phase() argument
104 init.name = clks->name; in clk_register_hisi_phase()
106 init.flags = clks->flags; in clk_register_hisi_phase()
107 init.parent_names = clks->parent_names ? &clks->parent_names : NULL; in clk_register_hisi_phase()
108 init.num_parents = clks->parent_names ? 1 : 0; in clk_register_hisi_phase()
110 phase->reg = base + clks->offset; in clk_register_hisi_phase()
111 phase->shift = clks->shift; in clk_register_hisi_phase()
112 phase->mask = (BIT(clks->width) - 1) << clks->shift; in clk_register_hisi_phase()
114 phase->phase_degrees = clks->phase_degrees; in clk_register_hisi_phase()
115 phase->phase_regvals = clks->phase_regvals; in clk_register_hisi_phase()
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| /drivers/clk/mmp/ |
| D | clk.c | 21 unit->clk_data.clks = clk_table; in mmp_clk_init()
27 struct mmp_param_fixed_rate_clk *clks, in mmp_register_fixed_rate_clks() argument
34 clk = clk_register_fixed_rate(NULL, clks[i].name, in mmp_register_fixed_rate_clks()
35 clks[i].parent_name, in mmp_register_fixed_rate_clks()
36 clks[i].flags, in mmp_register_fixed_rate_clks()
37 clks[i].fixed_rate); in mmp_register_fixed_rate_clks()
40 __func__, clks[i].name); in mmp_register_fixed_rate_clks()
43 if (clks[i].id) in mmp_register_fixed_rate_clks()
44 unit->clk_table[clks[i].id] = clk; in mmp_register_fixed_rate_clks()
49 struct mmp_param_fixed_factor_clk *clks, in mmp_register_fixed_factor_clks() argument
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| /drivers/clk/mxs/ |
| D | clk-imx28.c | 145 static struct clk *clks[clk_max]; variable
167 clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000); in mx28_clocks_init()
168 clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000); in mx28_clocks_init()
169 clks[pll1] = mxs_clk_pll("pll1", "ref_xtal", PLL1CTRL0, 17, 480000000); in mx28_clocks_init()
170 clks[pll2] = mxs_clk_pll("pll2", "ref_xtal", PLL2CTRL0, 23, 50000000); in mx28_clocks_init()
171 clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll0", FRAC0, 0); in mx28_clocks_init()
172 clks[ref_emi] = mxs_clk_ref("ref_emi", "pll0", FRAC0, 1); in mx28_clocks_init()
173 clks[ref_io1] = mxs_clk_ref("ref_io1", "pll0", FRAC0, 2); in mx28_clocks_init()
174 clks[ref_io0] = mxs_clk_ref("ref_io0", "pll0", FRAC0, 3); in mx28_clocks_init()
175 clks[ref_pix] = mxs_clk_ref("ref_pix", "pll0", FRAC1, 0); in mx28_clocks_init()
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| D | clk-imx23.c | 90 static struct clk *clks[clk_max]; variable
112 clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000); in mx23_clocks_init()
113 clks[pll] = mxs_clk_pll("pll", "ref_xtal", PLLCTRL0, 16, 480000000); in mx23_clocks_init()
114 clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll", FRAC, 0); in mx23_clocks_init()
115 clks[ref_emi] = mxs_clk_ref("ref_emi", "pll", FRAC, 1); in mx23_clocks_init()
116 clks[ref_pix] = mxs_clk_ref("ref_pix", "pll", FRAC, 2); in mx23_clocks_init()
117 clks[ref_io] = mxs_clk_ref("ref_io", "pll", FRAC, 3); in mx23_clocks_init()
118 clks[saif_sel] = mxs_clk_mux("saif_sel", CLKSEQ, 0, 1, sel_pll, ARRAY_SIZE(sel_pll)); in mx23_clocks_init()
119 clks[lcdif_sel] = mxs_clk_mux("lcdif_sel", CLKSEQ, 1, 1, sel_pix, ARRAY_SIZE(sel_pix)); in mx23_clocks_init()
120 clks[gpmi_sel] = mxs_clk_mux("gpmi_sel", CLKSEQ, 4, 1, sel_io, ARRAY_SIZE(sel_io)); in mx23_clocks_init()
[all …]
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| /drivers/clk/ |
| D | clk-bulk.c | 16 struct clk_bulk_data *clks) in of_clk_bulk_get() argument
22 clks[i].id = NULL; in of_clk_bulk_get()
23 clks[i].clk = NULL; in of_clk_bulk_get()
27 of_property_read_string_index(np, "clock-names", i, &clks[i].id); in of_clk_bulk_get()
28 clks[i].clk = of_clk_get(np, i); in of_clk_bulk_get()
29 if (IS_ERR(clks[i].clk)) { in of_clk_bulk_get()
30 ret = PTR_ERR(clks[i].clk); in of_clk_bulk_get()
33 clks[i].clk = NULL; in of_clk_bulk_get()
41 clk_bulk_put(i, clks); in of_clk_bulk_get()
47 struct clk_bulk_data **clks) in of_clk_bulk_get_all() argument
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| D | clk-bm1880.c | 525 static int bm1880_clk_register_plls(struct bm1880_pll_hw_clock *clks, in bm1880_clk_register_plls() argument
534 struct bm1880_pll_hw_clock *bm1880_clk = &clks[i]; in bm1880_clk_register_plls()
543 data->hw_data.hws[clks[i].pll.id] = hw; in bm1880_clk_register_plls()
550 clk_hw_unregister(data->hw_data.hws[clks[i].pll.id]); in bm1880_clk_register_plls()
555 static int bm1880_clk_register_mux(const struct bm1880_mux_clock *clks, in bm1880_clk_register_mux() argument
564 hw = clk_hw_register_mux(NULL, clks[i].name, in bm1880_clk_register_mux()
565 clks[i].parents, in bm1880_clk_register_mux()
566 clks[i].num_parents, in bm1880_clk_register_mux()
567 clks[i].flags, in bm1880_clk_register_mux()
568 sys_base + clks[i].reg, in bm1880_clk_register_mux()
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| D | clk-devres.c | 103 struct clk_bulk_data *clks; member
111 clk_bulk_put(devres->num_clks, devres->clks); in devm_clk_bulk_release()
115 struct clk_bulk_data *clks, bool optional) in __devm_clk_bulk_get() argument
126 ret = clk_bulk_get_optional(dev, num_clks, clks); in __devm_clk_bulk_get()
128 ret = clk_bulk_get(dev, num_clks, clks); in __devm_clk_bulk_get()
130 devres->clks = clks; in __devm_clk_bulk_get()
141 struct clk_bulk_data *clks) in devm_clk_bulk_get() argument
143 return __devm_clk_bulk_get(dev, num_clks, clks, false); in devm_clk_bulk_get()
148 struct clk_bulk_data *clks) in devm_clk_bulk_get_optional() argument
150 return __devm_clk_bulk_get(dev, num_clks, clks, true); in devm_clk_bulk_get_optional()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| D | dcn20_clk_mgr.c | 109 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; in dcn20_update_clocks_update_dpp_dto()
136 if (clk_mgr->base.clks.dppclk_khz == 0 || clk_mgr->base.clks.dispclk_khz == 0) in dcn20_update_clocks_update_dentist()
140 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz; in dcn20_update_clocks_update_dentist()
142 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz; in dcn20_update_clocks_update_dentist()
237 if (clk_mgr_base->clks.dispclk_khz == 0 || in dcn2_update_clocks()
262 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { in dcn2_update_clocks()
263 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in dcn2_update_clocks()
265 …pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz… in dcn2_update_clocks()
269 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { in dcn2_update_clocks()
270 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; in dcn2_update_clocks()
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| /drivers/clk/axis/ |
| D | clk-artpec6.c | 43 struct clk **clks; in of_artpec6_clkctrl_setup() local
56 clks = clkdata->clk_table; in of_artpec6_clkctrl_setup()
59 clks[i] = ERR_PTR(-EPROBE_DEFER); in of_artpec6_clkctrl_setup()
85 clks[ARTPEC6_CLK_CPU] = in of_artpec6_clkctrl_setup()
88 clks[ARTPEC6_CLK_CPU_PERIPH] = in of_artpec6_clkctrl_setup()
92 clks[ARTPEC6_CLK_UART_PCLK] = in of_artpec6_clkctrl_setup()
94 clks[ARTPEC6_CLK_UART_REFCLK] = in of_artpec6_clkctrl_setup()
98 clks[ARTPEC6_CLK_SPI_PCLK] = in of_artpec6_clkctrl_setup()
100 clks[ARTPEC6_CLK_SPI_SSPCLK] = in of_artpec6_clkctrl_setup()
104 clks[ARTPEC6_CLK_DBG_PCLK] = in of_artpec6_clkctrl_setup()
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| /drivers/clk/socfpga/ |
| D | clk-gate-s10.c | 127 struct clk_hw *s10_register_gate(const struct stratix10_gate_clock *clks, void __iomem *regbase) in s10_register_gate() argument
132 const char *parent_name = clks->parent_name; in s10_register_gate()
139 socfpga_clk->hw.reg = regbase + clks->gate_reg; in s10_register_gate()
140 socfpga_clk->hw.bit_idx = clks->gate_idx; in s10_register_gate()
145 socfpga_clk->fixed_div = clks->fixed_div; in s10_register_gate()
147 if (clks->div_reg) in s10_register_gate()
148 socfpga_clk->div_reg = regbase + clks->div_reg; in s10_register_gate()
152 socfpga_clk->width = clks->div_width; in s10_register_gate()
153 socfpga_clk->shift = clks->div_offset; in s10_register_gate()
155 if (clks->bypass_reg) in s10_register_gate()
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| D | clk-periph-s10.c | 101 struct clk_hw *s10_register_periph(const struct stratix10_perip_c_clock *clks, in s10_register_periph() argument
107 const char *name = clks->name; in s10_register_periph()
108 const char *parent_name = clks->parent_name; in s10_register_periph()
115 periph_clk->hw.reg = reg + clks->offset; in s10_register_periph()
119 init.flags = clks->flags; in s10_register_periph()
121 init.num_parents = clks->num_parents; in s10_register_periph()
124 init.parent_data = clks->parent_data; in s10_register_periph()
137 struct clk_hw *n5x_register_periph(const struct n5x_perip_c_clock *clks, in n5x_register_periph() argument
143 const char *name = clks->name; in n5x_register_periph()
144 const char *parent_name = clks->parent_name; in n5x_register_periph()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/ |
| D | dcn201_clk_mgr.c | 79 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); in dcn201_init_clocks()
80 clk_mgr->clks.p_state_change_support = true; in dcn201_init_clocks()
81 clk_mgr->clks.prev_p_state_change_support = true; in dcn201_init_clocks()
82 clk_mgr->clks.max_supported_dppclk_khz = 1200000; in dcn201_init_clocks()
83 clk_mgr->clks.max_supported_dispclk_khz = 1200000; in dcn201_init_clocks()
103 if (clk_mgr_base->clks.dispclk_khz == 0 || in dcn201_update_clocks()
112 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) in dcn201_update_clocks()
113 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz; in dcn201_update_clocks()
119 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) in dcn201_update_clocks()
120 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in dcn201_update_clocks()
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| /drivers/clk/zynq/ |
| D | clkc.c | 62 static struct clk *clks[clk_max]; variable
147 clks[fclk] = clk_register_gate(NULL, clk_name, in zynq_clk_register_fclk()
152 if (clk_prepare_enable(clks[fclk])) in zynq_clk_register_fclk()
171 clks[fclk] = ERR_PTR(-ENOMEM); in zynq_clk_register_fclk()
197 clks[clk0] = clk_register_gate(NULL, clk_name0, div_name, in zynq_clk_register_periph_clk()
200 clks[clk1] = clk_register_gate(NULL, clk_name1, div_name, in zynq_clk_register_periph_clk()
209 clks[clk0] = ERR_PTR(-ENOMEM); in zynq_clk_register_periph_clk()
211 clks[clk1] = ERR_PTR(-ENOMEM); in zynq_clk_register_periph_clk()
260 clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll], in zynq_clk_setup()
266 clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll], in zynq_clk_setup()
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| /drivers/clk/microchip/ |
| D | clk-pic32mzda.c | 128 struct clk *clks[MAXCLKS]; member
157 struct clk **clks; in pic32mzda_clk_probe() local
173 clks = &cd->clks[0]; in pic32mzda_clk_probe()
176 clks[POSCCLK] = clk_register_fixed_rate(&pdev->dev, "posc_clk", NULL, in pic32mzda_clk_probe()
178 clks[FRCCLK] = clk_register_fixed_rate(&pdev->dev, "frc_clk", NULL, in pic32mzda_clk_probe()
180 clks[BFRCCLK] = clk_register_fixed_rate(&pdev->dev, "bfrc_clk", NULL, in pic32mzda_clk_probe()
182 clks[LPRCCLK] = clk_register_fixed_rate(&pdev->dev, "lprc_clk", NULL, in pic32mzda_clk_probe()
184 clks[UPLLCLK] = clk_register_fixed_rate(&pdev->dev, "usbphy_clk", NULL, in pic32mzda_clk_probe()
189 clks[SOSCCLK] = pic32_sosc_clk_register(&sosc_clk, core); in pic32mzda_clk_probe()
192 clks[FRCDIVCLK] = clk_register_divider(&pdev->dev, "frcdiv_clk", in pic32mzda_clk_probe()
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| /drivers/cpufreq/ |
| D | imx6q-cpufreq.c | 40 static struct clk_bulk_data clks[] = { variable
68 old_freq = clk_get_rate(clks[ARM].clk) / 1000; in imx6q_set_target()
127 clk_set_rate(clks[ARM].clk, (old_freq >> 1) * 1000); in imx6q_set_target()
128 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); in imx6q_set_target()
129 if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk)) in imx6q_set_target()
130 clk_set_parent(clks[SECONDARY_SEL].clk, in imx6q_set_target()
131 clks[PLL2_BUS].clk); in imx6q_set_target()
133 clk_set_parent(clks[SECONDARY_SEL].clk, in imx6q_set_target()
134 clks[PLL2_PFD2_396M].clk); in imx6q_set_target()
135 clk_set_parent(clks[STEP].clk, clks[SECONDARY_SEL].clk); in imx6q_set_target()
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| /drivers/pci/controller/dwc/ |
| D | pcie-qcom.c | 156 struct clk_bulk_data clks[QCOM_PCIE_1_0_0_MAX_CLOCKS]; member
165 struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS]; member
174 struct clk_bulk_data clks[QCOM_PCIE_2_3_2_MAX_CLOCKS]; member
181 struct clk_bulk_data clks[QCOM_PCIE_2_3_3_MAX_CLOCKS]; member
188 struct clk_bulk_data clks[QCOM_PCIE_2_4_0_MAX_CLOCKS]; member
197 struct clk_bulk_data clks[QCOM_PCIE_2_7_0_MAX_CLOCKS]; member
205 struct clk_bulk_data clks[QCOM_PCIE_2_9_0_MAX_CLOCKS]; member
315 res->clks[0].id = "iface"; in qcom_pcie_get_resources_2_1_0()
316 res->clks[1].id = "core"; in qcom_pcie_get_resources_2_1_0()
317 res->clks[2].id = "phy"; in qcom_pcie_get_resources_2_1_0()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/ |
| D | rv1_clk_mgr.c | 39 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); in rv1_init_clocks()
45 bool dispclk_increase = new_clocks->dispclk_khz > clk_mgr->base.clks.dispclk_khz; in rv1_determine_dppclk_threshold()
47 bool cur_dpp_div = clk_mgr->base.clks.dispclk_khz > clk_mgr->base.clks.dppclk_khz; in rv1_determine_dppclk_threshold()
77 if (clk_mgr->base.clks.dispclk_khz <= disp_clk_threshold) in rv1_determine_dppclk_threshold()
185 clk_mgr->base.clks.dispclk_khz = new_clocks->dispclk_khz; in ramp_up_dispclk_with_dpp()
186 clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz; in ramp_up_dispclk_with_dpp()
187 clk_mgr->base.clks.max_supported_dppclk_khz = new_clocks->max_supported_dppclk_khz; in ramp_up_dispclk_with_dpp()
227 if (new_clocks->dispclk_khz > clk_mgr_base->clks.dispclk_khz in rv1_update_clocks()
228 || new_clocks->phyclk_khz > clk_mgr_base->clks.phyclk_khz in rv1_update_clocks()
229 || new_clocks->fclk_khz > clk_mgr_base->clks.fclk_khz in rv1_update_clocks()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| D | dcn32_clk_mgr.c | 162 memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks)); in dcn32_init_clocks()
163 clk_mgr_base->clks.p_state_change_support = true; in dcn32_init_clocks()
164 clk_mgr_base->clks.prev_p_state_change_support = true; in dcn32_init_clocks()
165 clk_mgr_base->clks.fclk_prev_p_state_change_support = true; in dcn32_init_clocks()
298 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; in dcn32_update_clocks_update_dpp_dto()
338 if (clk_mgr->base.clks.dispclk_khz == 0) in dcn32_update_clocks_update_dentist()
342 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz; in dcn32_update_clocks_update_dentist()
422 …dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, khz_to_mhz_ceil(clk_mgr->base.clks.dispclk_… in dcn32_update_clocks_update_dentist()
472 if (clk_mgr_base->clks.dispclk_khz == 0 || in dcn32_update_clocks()
494 …clk_mgr_base->clks.fclk_prev_p_state_change_support = clk_mgr_base->clks.fclk_p_state_change_suppo… in dcn32_update_clocks()
[all …]
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| D | dcn30_clk_mgr.c | 113 memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks)); in dcn3_init_clocks()
114 clk_mgr_base->clks.p_state_change_support = true; in dcn3_init_clocks()
115 clk_mgr_base->clks.prev_p_state_change_support = true; in dcn3_init_clocks()
213 if (clk_mgr_base->clks.dispclk_khz == 0 || in dcn3_update_clocks()
234 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { in dcn3_update_clocks()
235 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in dcn3_update_clocks()
236 …dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCEFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_k… in dcn3_update_clocks()
239 …if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_d… in dcn3_update_clocks()
240 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; in dcn3_update_clocks()
241 …dcn30_smu_set_min_deep_sleep_dcef_clk(clk_mgr, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_slee… in dcn3_update_clocks()
[all …]
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| /drivers/misc/ |
| D | xilinx_sdfec.c | 215 struct xsdfec_clks clks; member
1195 struct xsdfec_clks *clks) in xsdfec_clk_init() argument
1199 clks->core_clk = devm_clk_get(&pdev->dev, "core_clk"); in xsdfec_clk_init()
1200 if (IS_ERR(clks->core_clk)) { in xsdfec_clk_init()
1202 return PTR_ERR(clks->core_clk); in xsdfec_clk_init()
1205 clks->axi_clk = devm_clk_get(&pdev->dev, "s_axi_aclk"); in xsdfec_clk_init()
1206 if (IS_ERR(clks->axi_clk)) { in xsdfec_clk_init()
1208 return PTR_ERR(clks->axi_clk); in xsdfec_clk_init()
1211 clks->din_words_clk = devm_clk_get(&pdev->dev, "s_axis_din_words_aclk"); in xsdfec_clk_init()
1212 if (IS_ERR(clks->din_words_clk)) { in xsdfec_clk_init()
[all …]
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| /drivers/clk/visconti/ |
| D | clkc.c | 78 const struct visconti_clk_gate_table *clks, in visconti_clk_register_gate() argument
102 init.flags = clks->flags; in visconti_clk_register_gate()
107 gate->ckon_offset = clks->ckon_offset; in visconti_clk_register_gate()
108 gate->ckoff_offset = clks->ckoff_offset; in visconti_clk_register_gate()
109 gate->ck_idx = clks->ck_idx; in visconti_clk_register_gate()
125 const struct visconti_clk_gate_table *clks, in visconti_clk_register_gates() argument
134 const char *parent_div_name = clks[i].parent_data[0].name; in visconti_clk_register_gates()
146 dev_name = devm_kasprintf(dev, GFP_KERNEL, "%s_div", clks[i].name); in visconti_clk_register_gates()
150 if (clks[i].rs_id != NO_RESET) { in visconti_clk_register_gates()
151 rson_offset = reset[clks[i].rs_id].rson_offset; in visconti_clk_register_gates()
[all …]
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| /drivers/clk/sunxi/ |
| D | clk-a10-pll2.c | 42 struct clk **clks, *base_clk, *prediv_clk; in sun4i_pll2_setup() local
57 clks = kcalloc(SUN4I_PLL2_OUTPUTS, sizeof(struct clk *), GFP_KERNEL); in sun4i_pll2_setup()
58 if (!clks) in sun4i_pll2_setup()
122 clks[SUN4I_A10_PLL2_1X] = clk_register_fixed_factor(NULL, clk_name, in sun4i_pll2_setup()
127 WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_1X])); in sun4i_pll2_setup()
137 clks[SUN4I_A10_PLL2_2X] = clk_register_fixed_factor(NULL, clk_name, in sun4i_pll2_setup()
141 WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_2X])); in sun4i_pll2_setup()
146 clks[SUN4I_A10_PLL2_4X] = clk_register_fixed_factor(NULL, clk_name, in sun4i_pll2_setup()
150 WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_4X])); in sun4i_pll2_setup()
155 clks[SUN4I_A10_PLL2_8X] = clk_register_fixed_factor(NULL, clk_name, in sun4i_pll2_setup()
[all …]
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