| /drivers/net/ethernet/mellanox/mlx5/core/lib/ |
| D | clock.c | 120 struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info); in mlx5_ptp_getmaxphase() local
123 mdev = container_of(clock, struct mlx5_core_dev, clock); in mlx5_ptp_getmaxphase()
132 s64 max = mlx5_ptp_getmaxphase(&mdev->clock.ptp_info); in mlx5_is_mtutc_time_adj_cap()
180 struct mlx5_clock *clock = container_of(timer, struct mlx5_clock, timer); in read_internal_timer() local
181 struct mlx5_core_dev *mdev = container_of(clock, struct mlx5_core_dev, in read_internal_timer()
182 clock); in read_internal_timer()
190 struct mlx5_clock *clock = &mdev->clock; in mlx5_update_clock_info_page() local
201 timer = &clock->timer; in mlx5_update_clock_info_page()
215 struct mlx5_clock *clock = container_of(pps_info, struct mlx5_clock, in mlx5_pps_out() local
217 struct mlx5_core_dev *mdev = container_of(clock, struct mlx5_core_dev, in mlx5_pps_out()
[all …]
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| /drivers/net/ethernet/cavium/common/ |
| D | cavium_ptp.c | 95 struct cavium_ptp *clock = in cavium_ptp_adjfine() local
122 comp = ((u64)1000000000ull << 32) / clock->clock_rate; in cavium_ptp_adjfine()
128 spin_lock_irqsave(&clock->spin_lock, flags); in cavium_ptp_adjfine()
129 writeq(comp, clock->reg_base + PTP_CLOCK_COMP); in cavium_ptp_adjfine()
130 spin_unlock_irqrestore(&clock->spin_lock, flags); in cavium_ptp_adjfine()
142 struct cavium_ptp *clock = in cavium_ptp_adjtime() local
146 spin_lock_irqsave(&clock->spin_lock, flags); in cavium_ptp_adjtime()
147 timecounter_adjtime(&clock->time_counter, delta); in cavium_ptp_adjtime()
148 spin_unlock_irqrestore(&clock->spin_lock, flags); in cavium_ptp_adjtime()
164 struct cavium_ptp *clock = in cavium_ptp_gettime() local
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| /drivers/clk/renesas/ |
| D | clk-div6.c | 48 struct div6_clock *clock = to_div6_clock(hw); in cpg_div6_clock_enable() local
51 val = (readl(clock->reg) & ~(CPG_DIV6_DIV_MASK | CPG_DIV6_CKSTP)) in cpg_div6_clock_enable()
52 | CPG_DIV6_DIV(clock->div - 1); in cpg_div6_clock_enable()
53 writel(val, clock->reg); in cpg_div6_clock_enable()
60 struct div6_clock *clock = to_div6_clock(hw); in cpg_div6_clock_disable() local
63 val = readl(clock->reg); in cpg_div6_clock_disable()
73 writel(val, clock->reg); in cpg_div6_clock_disable()
78 struct div6_clock *clock = to_div6_clock(hw); in cpg_div6_clock_is_enabled() local
80 return !(readl(clock->reg) & CPG_DIV6_CKSTP); in cpg_div6_clock_is_enabled()
86 struct div6_clock *clock = to_div6_clock(hw); in cpg_div6_clock_recalc_rate() local
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| D | Kconfig | 4 bool "Renesas SoC clock support" if COMPILE_TEST && !ARCH_RENESAS
47 bool "Emma Mobile EV2 clock support" if COMPILE_TEST
50 bool "RZ/A1H clock support" if COMPILE_TEST
54 bool "RZ/A2 clock support" if COMPILE_TEST
58 bool "R-Mobile APE6 clock support" if COMPILE_TEST
63 bool "R-Mobile A1 clock support" if COMPILE_TEST
68 bool "RZ/G1H clock support" if COMPILE_TEST
72 bool "RZ/G1M clock support" if COMPILE_TEST
76 bool "RZ/G1E clock support" if COMPILE_TEST
80 bool "RZ/G1C clock support" if COMPILE_TEST
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| /drivers/gpu/drm/i915/display/ |
| D | intel_dpll.c | 313 int pnv_calc_dpll_params(int refclk, struct dpll *clock) in pnv_calc_dpll_params() argument
315 clock->m = clock->m2 + 2; in pnv_calc_dpll_params()
316 clock->p = clock->p1 * clock->p2; in pnv_calc_dpll_params()
317 if (WARN_ON(clock->n == 0 || clock->p == 0)) in pnv_calc_dpll_params()
319 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); in pnv_calc_dpll_params()
320 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); in pnv_calc_dpll_params()
322 return clock->dot; in pnv_calc_dpll_params()
330 int i9xx_calc_dpll_params(int refclk, struct dpll *clock) in i9xx_calc_dpll_params() argument
332 clock->m = i9xx_dpll_compute_m(clock); in i9xx_calc_dpll_params()
333 clock->p = clock->p1 * clock->p2; in i9xx_calc_dpll_params()
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| /drivers/gpu/drm/gma500/ |
| D | cdv_intel_display.c | 214 struct gma_clock_t *clock, bool is_lvds, u32 ddi_select) in cdv_dpll_set_clock_cdv() argument
272 m |= ((clock->m2) << SB_M_DIVIDER_SHIFT); in cdv_dpll_set_clock_cdv()
288 n_vco |= ((clock->n) << SB_N_DIVIDER_SHIFT); in cdv_dpll_set_clock_cdv()
290 if (clock->vco < 2250000) { in cdv_dpll_set_clock_cdv()
293 } else if (clock->vco < 2750000) { in cdv_dpll_set_clock_cdv()
296 } else if (clock->vco < 3300000) { in cdv_dpll_set_clock_cdv()
312 p |= SET_FIELD(clock->p1, SB_P1_DIVIDER); in cdv_dpll_set_clock_cdv()
313 switch (clock->p2) { in cdv_dpll_set_clock_cdv()
327 DRM_ERROR("Bad P2 clock: %d\n", clock->p2); in cdv_dpll_set_clock_cdv()
393 static void cdv_intel_clock(int refclk, struct gma_clock_t *clock) in cdv_intel_clock() argument
[all …]
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| D | oaktrail_crtc.c | 114 static void mrst_lvds_clock(int refclk, struct gma_clock_t *clock) in mrst_lvds_clock() argument
116 clock->dot = (refclk * clock->m) / (14 * clock->p1); in mrst_lvds_clock()
119 static void mrst_print_pll(struct gma_clock_t *clock) in mrst_print_pll() argument
122 clock->dot, clock->m, clock->m1, clock->m2, clock->n, in mrst_print_pll()
123 clock->p1, clock->p2); in mrst_print_pll()
130 struct gma_clock_t clock; in mrst_sdvo_find_best_pll() local
135 memset(&clock, 0, sizeof(clock)); in mrst_sdvo_find_best_pll()
137 for (clock.m = limit->m.min; clock.m <= limit->m.max; clock.m++) { in mrst_sdvo_find_best_pll()
138 for (clock.n = limit->n.min; clock.n <= limit->n.max; in mrst_sdvo_find_best_pll()
139 clock.n++) { in mrst_sdvo_find_best_pll()
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| D | psb_intel_display.c | 68 static void psb_intel_clock(int refclk, struct gma_clock_t *clock) in psb_intel_clock() argument
70 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); in psb_intel_clock()
71 clock->p = clock->p1 * clock->p2; in psb_intel_clock()
72 clock->vco = refclk * clock->m / (clock->n + 2); in psb_intel_clock()
73 clock->dot = clock->vco / clock->p; in psb_intel_clock()
106 struct gma_clock_t clock; in psb_intel_crtc_mode_set() local
148 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, in psb_intel_crtc_mode_set()
149 &clock); in psb_intel_crtc_mode_set()
152 adjusted_mode->clock, clock.dot); in psb_intel_crtc_mode_set()
156 fp = clock.n << 16 | clock.m1 << 8 | clock.m2; in psb_intel_crtc_mode_set()
[all …]
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| D | gma_display.c | 721 struct gma_clock_t *clock) in gma_pll_is_valid() argument
723 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) in gma_pll_is_valid()
725 if (clock->p < limit->p.min || limit->p.max < clock->p) in gma_pll_is_valid()
727 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) in gma_pll_is_valid()
729 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) in gma_pll_is_valid()
732 if (clock->m1 <= clock->m2 && clock->m1 != 0) in gma_pll_is_valid()
734 if (clock->m < limit->m.min || limit->m.max < clock->m) in gma_pll_is_valid()
736 if (clock->n < limit->n.min || limit->n.max < clock->n) in gma_pll_is_valid()
738 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) in gma_pll_is_valid()
744 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) in gma_pll_is_valid()
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| /drivers/soc/fsl/qe/ |
| D | ucc.c | 118 int ucc_set_qe_mux_rxtx(unsigned int ucc_num, enum qe_clock clock, in ucc_set_qe_mux_rxtx() argument
138 switch (clock) { in ucc_set_qe_mux_rxtx()
153 switch (clock) { in ucc_set_qe_mux_rxtx()
168 switch (clock) { in ucc_set_qe_mux_rxtx()
184 switch (clock) { in ucc_set_qe_mux_rxtx()
215 static int ucc_get_tdm_common_clk(u32 tdm_num, enum qe_clock clock) in ucc_get_tdm_common_clk() argument
230 switch (clock) { in ucc_get_tdm_common_clk()
251 switch (clock) { in ucc_get_tdm_common_clk()
275 static int ucc_get_tdm_rx_clk(u32 tdm_num, enum qe_clock clock) in ucc_get_tdm_rx_clk() argument
281 switch (clock) { in ucc_get_tdm_rx_clk()
[all …]
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| /drivers/net/phy/ |
| D | dp83640.c | 107 struct dp83640_clock *clock; member
231 if (dp83640->clock->page != page) { in ext_read()
233 dp83640->clock->page = page; in ext_read()
246 if (dp83640->clock->page != page) { in ext_write()
248 dp83640->clock->page = page; in ext_write()
303 static int periodic_output(struct dp83640_clock *clock, in periodic_output() argument
307 struct dp83640_private *dp83640 = clock->chosen; in periodic_output()
313 gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PEROUT, in periodic_output()
331 mutex_lock(&clock->extreg_lock); in periodic_output()
334 mutex_unlock(&clock->extreg_lock); in periodic_output()
[all …]
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| /drivers/video/fbdev/via/ |
| D | via_clock.c | 282 void via_clock_init(struct via_clock *clock, int gfx_chip) in via_clock_init() argument
287 clock->set_primary_clock_state = dummy_set_clock_state; in via_clock_init()
288 clock->set_primary_clock_source = dummy_set_clock_source; in via_clock_init()
289 clock->set_primary_pll_state = dummy_set_pll_state; in via_clock_init()
290 clock->set_primary_pll = cle266_set_primary_pll; in via_clock_init()
292 clock->set_secondary_clock_state = dummy_set_clock_state; in via_clock_init()
293 clock->set_secondary_clock_source = dummy_set_clock_source; in via_clock_init()
294 clock->set_secondary_pll_state = dummy_set_pll_state; in via_clock_init()
295 clock->set_secondary_pll = cle266_set_secondary_pll; in via_clock_init()
297 clock->set_engine_pll_state = dummy_set_pll_state; in via_clock_init()
[all …]
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| /drivers/platform/x86/intel/int3472/ |
| D | clk_and_regulator.c | 130 if (int3472->clock.cl) in skl_int3472_register_dsm_clock()
140 int3472->clock.frequency = skl_int3472_get_clk_frequency(int3472); in skl_int3472_register_dsm_clock()
141 int3472->clock.clk_hw.init = &init; in skl_int3472_register_dsm_clock()
142 int3472->clock.clk = clk_register(&adev->dev, &int3472->clock.clk_hw); in skl_int3472_register_dsm_clock()
143 if (IS_ERR(int3472->clock.clk)) { in skl_int3472_register_dsm_clock()
144 ret = PTR_ERR(int3472->clock.clk); in skl_int3472_register_dsm_clock()
148 int3472->clock.cl = clkdev_create(int3472->clock.clk, NULL, int3472->sensor_name); in skl_int3472_register_dsm_clock()
149 if (!int3472->clock.cl) { in skl_int3472_register_dsm_clock()
158 clk_unregister(int3472->clock.clk); in skl_int3472_register_dsm_clock()
174 if (int3472->clock.cl) in skl_int3472_register_gpio_clock()
[all …]
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| /drivers/net/ethernet/mellanox/mlxsw/ |
| D | spectrum_ptp.c | 111 static u64 __mlxsw_sp1_ptp_read_frc(struct mlxsw_sp1_ptp_clock *clock, in __mlxsw_sp1_ptp_read_frc() argument
114 struct mlxsw_core *mlxsw_core = clock->common.core; in __mlxsw_sp1_ptp_read_frc()
135 struct mlxsw_sp1_ptp_clock *clock = in mlxsw_sp1_ptp_read_frc() local
138 return __mlxsw_sp1_ptp_read_frc(clock, NULL) & cc->mask; in mlxsw_sp1_ptp_read_frc()
142 mlxsw_sp_ptp_phc_adjfreq(struct mlxsw_sp_ptp_clock *clock, int freq_adj) in mlxsw_sp_ptp_phc_adjfreq() argument
144 struct mlxsw_core *mlxsw_core = clock->core; in mlxsw_sp_ptp_phc_adjfreq()
163 mlxsw_sp1_ptp_phc_settime(struct mlxsw_sp1_ptp_clock *clock, u64 nsec) in mlxsw_sp1_ptp_phc_settime() argument
165 struct mlxsw_core *mlxsw_core = clock->common.core; in mlxsw_sp1_ptp_phc_settime()
174 spin_lock_bh(&clock->lock); in mlxsw_sp1_ptp_phc_settime()
175 cycles = mlxsw_sp1_ptp_ns2cycles(&clock->tc, next_sec_in_nsec); in mlxsw_sp1_ptp_phc_settime()
[all …]
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| /drivers/clk/bcm/ |
| D | Kconfig | 11 Enable common clock framework support for the Broadcom BCM2711
15 bool "Broadcom BCM2835 clock support"
20 Enable common clock framework support for Broadcom BCM2835
24 bool "Broadcom BCM63xx clock support"
29 Enable common clock framework support for Broadcom BCM63xx DSL SoCs
33 bool "Broadcom BCM63xx gated clock support"
37 Enable common clock framework support for Broadcom BCM63xx DSL SoCs
41 bool "Broadcom BCM63268 timer clock and reset support"
46 Enable timer clock and reset support for Broadcom BCM63268 DSL SoCs
50 bool "Broadcom Kona CCU clock support"
[all …]
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| /drivers/media/platform/qcom/camss/ |
| D | camss-csiphy.c | 143 struct camss_clock *clock = &csiphy->clock[i]; in csiphy_set_clock_rates() local
151 for (j = 0; j < clock->nfreqs; j++) in csiphy_set_clock_rates()
152 if (min_rate < clock->freq[j]) in csiphy_set_clock_rates()
155 if (j == clock->nfreqs) { in csiphy_set_clock_rates()
164 j = clock->nfreqs - 1; in csiphy_set_clock_rates()
166 round_rate = clk_round_rate(clock->clk, clock->freq[j]); in csiphy_set_clock_rates()
175 ret = clk_set_rate(clock->clk, csiphy->timer_clk_rate); in csiphy_set_clock_rates()
211 ret = camss_enable_clocks(csiphy->nclocks, csiphy->clock, dev); in csiphy_set_power()
225 camss_disable_clocks(csiphy->nclocks, csiphy->clock); in csiphy_set_power()
615 while (res->clock[csiphy->nclocks]) in msm_csiphy_subdev_init()
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| D | camss.c | 38 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer" },
50 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy1_timer" },
64 .clock = { "top_ahb", "ispif_ahb", "csi0_ahb", "ahb",
81 .clock = { "top_ahb", "ispif_ahb", "csi1_ahb", "ahb",
98 .clock = { "top_ahb", "ahb", "ispif_ahb",
111 .clock = { "top_ahb", "vfe0", "csi_vfe0",
133 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer" },
145 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy1_timer" },
157 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy2_timer" },
171 .clock = { "top_ahb", "ispif_ahb", "csi0_ahb", "ahb",
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| D | camss-csid.c | 103 struct camss_clock *clock = &csid->clock[i]; in csid_set_clock_rates() local
105 if (!strcmp(clock->name, "csi0") || in csid_set_clock_rates()
106 !strcmp(clock->name, "csi1") || in csid_set_clock_rates()
107 !strcmp(clock->name, "csi2") || in csid_set_clock_rates()
108 !strcmp(clock->name, "csi3")) { in csid_set_clock_rates()
114 for (j = 0; j < clock->nfreqs; j++) in csid_set_clock_rates()
115 if (min_rate < clock->freq[j]) in csid_set_clock_rates()
118 if (j == clock->nfreqs) { in csid_set_clock_rates()
127 j = clock->nfreqs - 1; in csid_set_clock_rates()
129 rate = clk_round_rate(clock->clk, clock->freq[j]); in csid_set_clock_rates()
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| /drivers/clk/samsung/ |
| D | Kconfig | 4 bool "Samsung Exynos clock controller support" if COMPILE_TEST
18 bool "Samsung S3C64xx clock controller support" if COMPILE_TEST
21 Support for the clock controller present on the Samsung S3C64xx SoCs.
25 bool "Samsung S5Pv210 clock controller support" if COMPILE_TEST
28 Support for the clock controller present on the Samsung S5Pv210 SoCs.
32 bool "Samsung Exynos3250 clock controller support" if COMPILE_TEST
35 Support for the clock controller present on the Samsung
39 bool "Samsung Exynos4 clock controller support" if COMPILE_TEST
42 Support for the clock controller present on the Samsung
47 bool "Samsung Exynos5250 clock controller support" if COMPILE_TEST
[all …]
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| /drivers/clk/ti/ |
| D | adpll.c | 197 static int ti_adpll_setup_clock(struct ti_adpll_data *d, struct clk *clock, in ti_adpll_setup_clock() argument
205 d->clocks[index].clk = clock; in ti_adpll_setup_clock()
215 cl = clkdev_create(clock, con_id, NULL); in ti_adpll_setup_clock()
226 d->outputs.clks[output_index] = clock; in ti_adpll_setup_clock()
242 struct clk *clock; in ti_adpll_init_divider() local
249 clock = clk_register_divider(d->dev, child_name, parent_name, 0, in ti_adpll_init_divider()
252 if (IS_ERR(clock)) { in ti_adpll_init_divider()
254 name, PTR_ERR(clock)); in ti_adpll_init_divider()
255 return PTR_ERR(clock); in ti_adpll_init_divider()
258 return ti_adpll_setup_clock(d, clock, index, output_index, child_name, in ti_adpll_init_divider()
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| /drivers/ptp/ |
| D | ptp_ines.c | 148 struct ines_clock *clock; member
180 static void ines_clock_cleanup(struct ines_clock *clock) in ines_clock_cleanup() argument
186 port = &clock->port[i]; in ines_clock_cleanup()
191 static int ines_clock_init(struct ines_clock *clock, struct device *device, in ines_clock_init() argument
199 INIT_LIST_HEAD(&clock->list); in ines_clock_init()
200 clock->node = node; in ines_clock_init()
201 clock->dev = device; in ines_clock_init()
202 clock->base = addr; in ines_clock_init()
203 clock->regs = clock->base; in ines_clock_init()
206 port = &clock->port[i]; in ines_clock_init()
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| D | Kconfig | 3 # PTP clock support configuration
6 menu "PTP clock support"
9 tristate "PTP clock support"
24 devices. If you want to use a PTP clock, then you should
25 also enable at least one clock driver as well.
43 tristate "Broadcom DTE as PTP clock"
50 (DTE) in the Broadcom SoC's as a PTP clock.
52 The clock can be used in both wired and wireless networks
59 tristate "Freescale QorIQ 1588 timer as PTP clock"
65 timer as a PTP clock. This clock is only useful if your PTP
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| /drivers/clk/starfive/ |
| D | Kconfig | 7 bool "StarFive JH7100 clock support"
12 Say yes here to support the clock controller on the StarFive JH7100
16 tristate "StarFive JH7100 audio clock support"
25 bool "StarFive JH7110 PLL clock support"
29 Say yes here to support the PLL clock controller on the
33 bool "StarFive JH7110 system clock support"
41 Say yes here to support the system clock controller on the
45 tristate "StarFive JH7110 always-on clock support"
49 Say yes here to support the always-on clock controller on the
53 tristate "StarFive JH7110 System-Top-Group clock support"
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| /drivers/clk/rockchip/ |
| D | Kconfig | 2 # common clock support for ROCKCHIP SoC family.
5 bool "Rockchip clock controller common support"
9 Say y here to enable common clock controller for Rockchip platforms.
13 bool "Rockchip PX30 clock controller support"
20 bool "Rockchip RV110x clock controller support"
27 bool "Rockchip RV1126 clock controller support"
34 bool "Rockchip RK3036 clock controller support"
41 bool "Rockchip RK312x clock controller support"
48 bool "Rockchip RK3188 clock controller support"
55 bool "Rockchip RK322x clock controller support"
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| /drivers/clk/qcom/ |
| D | Kconfig | 14 tristate "Support for Qualcomm's clock controllers"
54 Support for the CPU clock controller on msm8996 devices.
55 Say Y if you want to support CPU clock scaling using CPUfreq
76 memory and accepts clock requests, aggregates the requests and turns
89 memory and accepts clock requests, aggregates the requests and turns
108 Support for the global clock controller on apq8084 devices.
118 Support for the multimedia clock controller on apq8084 devices.
126 clock that feeds the CPUs on ipq based devices.
136 Support for APSS clock controller on IPQ platforms. The
137 APSS clock controller manages the Mux and enable block that feeds the
[all …]
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