| /drivers/spi/ |
| D | spi-zynq-qspi.c | 183 u32 config_reg; in zynq_qspi_init_hw() local
189 config_reg = 0; in zynq_qspi_init_hw()
192 config_reg |= ZYNQ_QSPI_LCFG_TWO_MEM; in zynq_qspi_init_hw()
194 zynq_qspi_write(xqspi, ZYNQ_QSPI_LINEAR_CFG_OFFSET, config_reg); in zynq_qspi_init_hw()
202 config_reg = zynq_qspi_read(xqspi, ZYNQ_QSPI_CONFIG_OFFSET); in zynq_qspi_init_hw()
203 config_reg &= ~(ZYNQ_QSPI_CONFIG_MSTREN_MASK | in zynq_qspi_init_hw()
210 config_reg |= (ZYNQ_QSPI_CONFIG_MSTREN_MASK | in zynq_qspi_init_hw()
214 zynq_qspi_write(xqspi, ZYNQ_QSPI_CONFIG_OFFSET, config_reg); in zynq_qspi_init_hw()
294 u32 config_reg; in zynq_qspi_chipselect() local
298 config_reg = zynq_qspi_read(xqspi, ZYNQ_QSPI_LINEAR_CFG_OFFSET); in zynq_qspi_chipselect()
[all …]
|
| D | spi-zynqmp-gqspi.c | 356 u32 config_reg, baud_rate_val = 0; in zynqmp_qspi_init_hw() local
379 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST); in zynqmp_qspi_init_hw()
380 config_reg &= ~GQSPI_CFG_MODE_EN_MASK; in zynqmp_qspi_init_hw()
382 config_reg |= GQSPI_CFG_GEN_FIFO_START_MODE_MASK; in zynqmp_qspi_init_hw()
384 config_reg &= ~GQSPI_CFG_ENDIAN_MASK; in zynqmp_qspi_init_hw()
386 config_reg &= ~GQSPI_CFG_EN_POLL_TO_MASK; in zynqmp_qspi_init_hw()
388 config_reg |= GQSPI_CFG_WP_HOLD_MASK; in zynqmp_qspi_init_hw()
390 config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK; in zynqmp_qspi_init_hw()
393 config_reg |= GQSPI_CFG_CLK_PHA_MASK; in zynqmp_qspi_init_hw()
395 config_reg &= ~GQSPI_CFG_CLK_PHA_MASK; in zynqmp_qspi_init_hw()
[all …]
|
| /drivers/iio/common/ms_sensors/ |
| D | ms_sensors_i2c.c | 254 u8 *config_reg) in ms_sensors_read_config_reg() argument
264 ret = i2c_master_recv(client, config_reg, 1); in ms_sensors_read_config_reg()
269 dev_dbg(&client->dev, "Config register :%x\n", *config_reg); in ms_sensors_read_config_reg()
288 u8 config_reg; in ms_sensors_write_resolution() local
291 ret = ms_sensors_read_config_reg(dev_data->client, &config_reg); in ms_sensors_write_resolution()
295 config_reg &= 0x7E; in ms_sensors_write_resolution()
296 config_reg |= ((i & 1) << 7) + ((i & 2) >> 1); in ms_sensors_write_resolution()
300 config_reg); in ms_sensors_write_resolution()
319 u8 config_reg; in ms_sensors_show_battery_low() local
322 ret = ms_sensors_read_config_reg(dev_data->client, &config_reg); in ms_sensors_show_battery_low()
[all …]
|
| /drivers/net/phy/ |
| D | aquantia_main.c | 365 u32 config_reg; in aqr107_read_rate() local
380 config_reg = VEND1_GLOBAL_CFG_10M; in aqr107_read_rate()
384 config_reg = VEND1_GLOBAL_CFG_100M; in aqr107_read_rate()
388 config_reg = VEND1_GLOBAL_CFG_1G; in aqr107_read_rate()
392 config_reg = VEND1_GLOBAL_CFG_2_5G; in aqr107_read_rate()
396 config_reg = VEND1_GLOBAL_CFG_5G; in aqr107_read_rate()
400 config_reg = VEND1_GLOBAL_CFG_10G; in aqr107_read_rate()
407 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, config_reg); in aqr107_read_rate()
|
| D | phylink.c | 3388 uint16_t config_reg, int speed) in phylink_decode_c37_word() argument
3397 mii_lpa_mod_linkmode_x(state->lp_advertising, config_reg, fd_bit); in phylink_decode_c37_word()
3412 uint16_t config_reg) in phylink_decode_sgmii_word() argument
3414 if (!(config_reg & LPA_SGMII_LINK)) { in phylink_decode_sgmii_word()
3419 switch (config_reg & LPA_SGMII_SPD_MASK) { in phylink_decode_sgmii_word()
3433 if (config_reg & LPA_SGMII_FULL_DUPLEX) in phylink_decode_sgmii_word()
|
| /drivers/input/misc/ |
| D | max77693-haptic.c | 107 unsigned int value, config_reg; in max77693_haptic_configure() local
116 config_reg = MAX77693_HAPTIC_REG_CONFIG2; in max77693_haptic_configure()
122 config_reg = MAX77843_HAP_REG_MCONFIG; in max77693_haptic_configure()
129 config_reg, value); in max77693_haptic_configure()
|
| /drivers/hwmon/ |
| D | max6620.c | 99 static const u8 config_reg[] = { variable
171 ret = i2c_smbus_read_byte_data(client, config_reg[i]); in max6620_update_device()
449 reg = i2c_smbus_read_byte_data(client, config_reg[i]); in max6620_init_client()
456 err = i2c_smbus_write_byte_data(client, config_reg[i], data->fancfg[i]); in max6620_init_client()
|
| /drivers/clk/qcom/ |
| D | clk-pll.c | 103 regmap_read(pll->clkr.regmap, pll->config_reg, &config); in clk_pll_recalc_rate()
162 regmap_write(pll->clkr.regmap, pll->config_reg, f->ibits); in clk_pll_set_rate()
242 regmap_update_bits(regmap, pll->config_reg, mask, val); in clk_pll_configure()
|
| D | clk-hfpll.h | 17 u32 config_reg; member
|
| D | clk-pll.h | 43 u32 config_reg; member
|
| D | hfpll.c | 22 .config_reg = 0x14,
|
| D | gcc-ipq806x.c | 36 .config_reg = 0x30d4,
65 .config_reg = 0x3174,
94 .config_reg = 0x3154,
124 .config_reg = 0x3204,
150 .config_reg = 0x3244,
176 .config_reg = 0x3304,
201 .config_reg = 0x31d4,
246 .config_reg = 0x31b4,
265 .config_reg = 0x3194,
|
| D | gcc-msm8960.c | 32 .config_reg = 0x3174,
63 .config_reg = 0x3154,
95 .config_reg = 0x3204,
123 .config_reg = 0x3244,
137 .config_reg = 0x3304,
165 .config_reg = 0x3284,
193 .config_reg = 0x32c4,
221 .config_reg = 0x3304,
235 .config_reg = 0x3404,
262 .config_reg = 0x31d4,
|
| D | a53-pll.c | 113 pll->config_reg = 0x14; in qcom_a53pll_probe()
|
| D | gcc-msm8939.c | 56 .config_reg = 0x21010,
87 .config_reg = 0x20010,
118 .config_reg = 0x4a010,
149 .config_reg = 0x23010,
180 .config_reg = 0x22010,
227 .config_reg = 0x24010,
273 .config_reg = 0x25010,
304 .config_reg = 0x37010,
|
| D | clk-hfpll.c | 31 regmap_write(regmap, hd->config_reg, hd->config_val); in __clk_hfpll_init_once()
|
| D | gcc-mdm9615.c | 51 .config_reg = 0x30d4,
93 .config_reg = 0x3154,
122 .config_reg = 0x31d4,
|
| D | lcc-ipq806x.c | 30 .config_reg = 0x14,
|
| D | mmcc-apq8084.c | 47 .config_reg = 0x0014,
78 .config_reg = 0x0050,
109 .config_reg = 0x4110,
126 .config_reg = 0x0090,
144 .config_reg = 0x00b0,
|
| D | lcc-msm8960.c | 33 .config_reg = 0x14,
|
| D | mmcc-msm8974.c | 48 .config_reg = 0x0014,
79 .config_reg = 0x0050,
110 .config_reg = 0x4110,
127 .config_reg = 0x0090,
|
| D | gcc-msm8976.c | 59 .config_reg = 0x21014,
92 .config_reg = 0x4a014,
128 .config_reg = 0x22010,
176 .config_reg = 0x24018,
208 .config_reg = 0x37014,
|
| /drivers/pinctrl/renesas/ |
| D | core.c | 252 const struct pinmux_cfg_reg *config_reg = in sh_pfc_get_config_reg() local
254 unsigned int r_width = config_reg->reg_width; in sh_pfc_get_config_reg()
255 unsigned int f_width = config_reg->field_width; in sh_pfc_get_config_reg()
271 curr_width = abs(config_reg->var_field_width[m]); in sh_pfc_get_config_reg()
272 if (config_reg->var_field_width[m] < 0) in sh_pfc_get_config_reg()
278 if (config_reg->enum_ids[pos + n] == enum_id) { in sh_pfc_get_config_reg()
279 *crp = config_reg; in sh_pfc_get_config_reg()
|
| /drivers/i2c/busses/ |
| D | i2c-mlxbf.c | 1413 u32 config_reg; in mlxbf_i2c_init_master() local
1450 config_reg = readl(gpio_res->io + MLXBF_I2C_GPIO_0_FUNC_EN_0); in mlxbf_i2c_init_master()
1451 config_reg = MLXBF_I2C_GPIO_SMBUS_GW_ASSERT_PINS(priv->bus, in mlxbf_i2c_init_master()
1452 config_reg); in mlxbf_i2c_init_master()
1453 writel(config_reg, gpio_res->io + MLXBF_I2C_GPIO_0_FUNC_EN_0); in mlxbf_i2c_init_master()
1455 config_reg = readl(gpio_res->io + MLXBF_I2C_GPIO_0_FORCE_OE_EN); in mlxbf_i2c_init_master()
1456 config_reg = MLXBF_I2C_GPIO_SMBUS_GW_RESET_PINS(priv->bus, in mlxbf_i2c_init_master()
1457 config_reg); in mlxbf_i2c_init_master()
1458 writel(config_reg, gpio_res->io + MLXBF_I2C_GPIO_0_FORCE_OE_EN); in mlxbf_i2c_init_master()
|
| /drivers/usb/cdns3/ |
| D | cdnsp-mem.c | 1223 val = readl(&pdev->op_regs->config_reg); in cdnsp_mem_init()
1225 writel(val, &pdev->op_regs->config_reg); in cdnsp_mem_init()
|