Home
last modified time | relevance | path

Searched refs:cpt (Results 1 – 22 of 22) sorted by relevance

/drivers/crypto/marvell/octeontx/
Dotx_cptpf_main.c17 static void otx_cpt_disable_mbox_interrupts(struct otx_cpt_device *cpt) in otx_cpt_disable_mbox_interrupts() argument
20 writeq(~0ull, cpt->reg_base + OTX_CPT_PF_MBOX_ENA_W1CX(0)); in otx_cpt_disable_mbox_interrupts()
23 static void otx_cpt_enable_mbox_interrupts(struct otx_cpt_device *cpt) in otx_cpt_enable_mbox_interrupts() argument
26 writeq(~0ull, cpt->reg_base + OTX_CPT_PF_MBOX_ENA_W1SX(0)); in otx_cpt_enable_mbox_interrupts()
30 void *cpt) in otx_cpt_mbx0_intr_handler() argument
32 otx_cpt_mbox_intr_handler(cpt, 0); in otx_cpt_mbx0_intr_handler()
37 static void otx_cpt_reset(struct otx_cpt_device *cpt) in otx_cpt_reset() argument
39 writeq(1, cpt->reg_base + OTX_CPT_PF_RESET); in otx_cpt_reset()
42 static void otx_cpt_find_max_enabled_cores(struct otx_cpt_device *cpt) in otx_cpt_find_max_enabled_cores() argument
46 pf_cnsts.u = readq(cpt->reg_base + OTX_CPT_PF_CONSTANTS); in otx_cpt_find_max_enabled_cores()
[all …]
Dotx_cptpf_mbox.c74 static void otx_cpt_send_msg_to_vf(struct otx_cpt_device *cpt, int vf, in otx_cpt_send_msg_to_vf() argument
78 writeq(mbx->data, cpt->reg_base + OTX_CPT_PF_VFX_MBOXX(vf, 1)); in otx_cpt_send_msg_to_vf()
79 writeq(mbx->msg, cpt->reg_base + OTX_CPT_PF_VFX_MBOXX(vf, 0)); in otx_cpt_send_msg_to_vf()
86 static void otx_cpt_mbox_send_ack(struct otx_cpt_device *cpt, int vf, in otx_cpt_mbox_send_ack() argument
91 otx_cpt_send_msg_to_vf(cpt, vf, mbx); in otx_cpt_mbox_send_ack()
95 static void otx_cptpf_mbox_send_nack(struct otx_cpt_device *cpt, int vf, in otx_cptpf_mbox_send_nack() argument
100 otx_cpt_send_msg_to_vf(cpt, vf, mbx); in otx_cptpf_mbox_send_nack()
103 static void otx_cpt_clear_mbox_intr(struct otx_cpt_device *cpt, u32 vf) in otx_cpt_clear_mbox_intr() argument
106 writeq(1ull << vf, cpt->reg_base + OTX_CPT_PF_MBOX_INTX(0)); in otx_cpt_clear_mbox_intr()
112 static void otx_cpt_cfg_qlen_for_vf(struct otx_cpt_device *cpt, int vf, in otx_cpt_cfg_qlen_for_vf() argument
[all …]
Dotx_cptpf_ucode.c177 struct otx_cpt_device *cpt = (struct otx_cpt_device *) obj; in cpt_set_ucode_base() local
182 bmap = get_cores_bmap(&cpt->pdev->dev, eng_grp); in cpt_set_ucode_base()
198 writeq((u64) dma_addr, cpt->reg_base + in cpt_set_ucode_base()
206 struct otx_cpt_device *cpt = (struct otx_cpt_device *) obj; in cpt_detach_and_disable_cores() local
212 bmap = get_cores_bmap(&cpt->pdev->dev, eng_grp); in cpt_detach_and_disable_cores()
217 reg = readq(cpt->reg_base + OTX_CPT_PF_GX_EN(eng_grp->idx)); in cpt_detach_and_disable_cores()
224 writeq(reg, cpt->reg_base + OTX_CPT_PF_GX_EN(eng_grp->idx)); in cpt_detach_and_disable_cores()
233 reg = readq(cpt->reg_base + OTX_CPT_PF_EXEC_BUSY); in cpt_detach_and_disable_cores()
242 reg = readq(cpt->reg_base + OTX_CPT_PF_EXE_CTL); in cpt_detach_and_disable_cores()
246 writeq(reg, cpt->reg_base + OTX_CPT_PF_EXE_CTL); in cpt_detach_and_disable_cores()
[all …]
Dotx_cptpf.h31 void otx_cpt_mbox_intr_handler(struct otx_cpt_device *cpt, int mbx);
32 void otx_cpt_disable_all_cores(struct otx_cpt_device *cpt);
DMakefile2 obj-$(CONFIG_CRYPTO_DEV_OCTEONTX_CPT) += octeontx-cpt.o octeontx-cptvf.o
4 octeontx-cpt-objs := otx_cptpf_main.o otx_cptpf_mbox.o otx_cptpf_ucode.o
Dotx_cptvf.h22 #define otx_cpt_device_ready(cpt) ((cpt)->flags & OTX_CPT_FLAG_DEVICE_READY) argument
/drivers/crypto/cavium/cpt/
Dcptpf_main.c26 static void cpt_disable_cores(struct cpt_device *cpt, u64 coremask, in cpt_disable_cores() argument
32 struct device *dev = &cpt->pdev->dev; in cpt_disable_cores()
35 coremask = (coremask << cpt->max_se_cores); in cpt_disable_cores()
38 grpmask = cpt_read_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp)); in cpt_disable_cores()
39 cpt_write_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp), in cpt_disable_cores()
42 grp = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXEC_BUSY(0)); in cpt_disable_cores()
45 grp = cpt_read_csr64(cpt->reg_base, in cpt_disable_cores()
54 pf_exe_ctl = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0)); in cpt_disable_cores()
55 cpt_write_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0), in cpt_disable_cores()
63 static void cpt_enable_cores(struct cpt_device *cpt, u64 coremask, in cpt_enable_cores() argument
[all …]
Dcptpf_mbox.c8 static void cpt_send_msg_to_vf(struct cpt_device *cpt, int vf, in cpt_send_msg_to_vf() argument
12 cpt_write_csr64(cpt->reg_base, CPTX_PF_VFX_MBOXX(0, vf, 1), in cpt_send_msg_to_vf()
14 cpt_write_csr64(cpt->reg_base, CPTX_PF_VFX_MBOXX(0, vf, 0), mbx->msg); in cpt_send_msg_to_vf()
20 static void cpt_mbox_send_ack(struct cpt_device *cpt, int vf, in cpt_mbox_send_ack() argument
25 cpt_send_msg_to_vf(cpt, vf, mbx); in cpt_mbox_send_ack()
28 static void cpt_clear_mbox_intr(struct cpt_device *cpt, u32 vf) in cpt_clear_mbox_intr() argument
31 cpt_write_csr64(cpt->reg_base, CPTX_PF_MBOX_INTX(0, 0), (1 << vf)); in cpt_clear_mbox_intr()
37 static void cpt_cfg_qlen_for_vf(struct cpt_device *cpt, int vf, u32 size) in cpt_cfg_qlen_for_vf() argument
41 pf_qx_ctl.u = cpt_read_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, vf)); in cpt_cfg_qlen_for_vf()
44 cpt_write_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, vf), pf_qx_ctl.u); in cpt_cfg_qlen_for_vf()
[all …]
Dcpt_common.h24 #define cpt_sriov_enabled(cpt) ((cpt)->flags & CPT_FLAG_SRIOV_ENABLED) argument
25 #define cpt_vf_driver(cpt) ((cpt)->flags & CPT_FLAG_VF_DRIVER) argument
26 #define cpt_device_ready(cpt) ((cpt)->flags & CPT_FLAG_DEVICE_READY) argument
Dcptpf.h60 void cpt_mbox_intr_handler(struct cpt_device *cpt, int mbx);
/drivers/crypto/marvell/
DKconfig37 the modules will be called octeontx-cpt and octeontx-cptvf
/drivers/crypto/
DMakefile15 obj-$(CONFIG_CRYPTO_DEV_CPT) += cavium/cpt/
DKconfig478 source "drivers/crypto/cavium/cpt/Kconfig"
/drivers/s390/cio/
Ddevice_status.c159 cdev_irb->esw.esw0.erw.cpt = irb->esw.esw0.erw.cpt; in ccw_device_accumulate_esw()
/drivers/media/dvb-frontends/
Dstv0367.c1420 int cpt = 0; in stv0367ter_snr_readreg() local
1423 while (cpt < 10) { in stv0367ter_snr_readreg()
1430 cpt++; in stv0367ter_snr_readreg()
1581 int abc = 0, def = 0, cpt = 0;
1584 (cpt < 400)) || ((Errors == 0) && (cpt < 400))) {
1591 cpt++;
/drivers/net/ethernet/marvell/octeontx2/af/
Drvu_debugfs.c3364 rvu->rvu_dbg.cpt = debugfs_create_dir("cpt", rvu->rvu_dbg.root); in rvu_dbg_cpt_init()
3369 rvu->rvu_dbg.cpt = debugfs_create_dir("cpt1", in rvu_dbg_cpt_init()
3376 debugfs_create_file("cpt_pc", 0600, rvu->rvu_dbg.cpt, ctx, in rvu_dbg_cpt_init()
3378 debugfs_create_file("cpt_ae_sts", 0600, rvu->rvu_dbg.cpt, ctx, in rvu_dbg_cpt_init()
3380 debugfs_create_file("cpt_se_sts", 0600, rvu->rvu_dbg.cpt, ctx, in rvu_dbg_cpt_init()
3382 debugfs_create_file("cpt_ie_sts", 0600, rvu->rvu_dbg.cpt, ctx, in rvu_dbg_cpt_init()
3384 debugfs_create_file("cpt_engines_info", 0600, rvu->rvu_dbg.cpt, ctx, in rvu_dbg_cpt_init()
3386 debugfs_create_file("cpt_lfs_info", 0600, rvu->rvu_dbg.cpt, ctx, in rvu_dbg_cpt_init()
3388 debugfs_create_file("cpt_err_info", 0600, rvu->rvu_dbg.cpt, ctx, in rvu_dbg_cpt_init()
Drvu.h69 struct dentry *cpt; member
Drvu.c1031 goto cpt; in rvu_setup_hw_resources()
1053 cpt: in rvu_setup_hw_resources()
1928 rsp->cpt = rvu_rsrc_free_count(&block->lf); in rvu_mbox_handler_free_rsrc_cnt()
Dmbox.h468 u16 cpt; member
/drivers/net/ethernet/chelsio/cxgb3/
Dt3_hw.c2974 unsigned int v, tps, cpt, bpt, delta, mindelta = ~0; in t3_config_sched() local
2980 for (cpt = 1; cpt <= 255; cpt++) { in t3_config_sched()
2981 tps = clk / cpt; in t3_config_sched()
2988 selected_cpt = cpt; in t3_config_sched()
Dcxgb3_main.c803 unsigned int v, addr, bpt, cpt; in tm_attr_show() local
813 cpt = v & 0xff; in tm_attr_show()
814 if (!cpt) in tm_attr_show()
817 v = (adap->params.vpd.cclk * 1000) / cpt; in tm_attr_show()
/drivers/net/ethernet/chelsio/cxgb4/
Dt4_hw.c10286 unsigned int v, addr, bpt, cpt; in t4_get_tx_sched() local
10294 cpt = v & 0xff; in t4_get_tx_sched()
10295 if (!cpt) { in t4_get_tx_sched()
10298 v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */ in t4_get_tx_sched()