Searched refs:cqe_sz (Results 1 – 17 of 17) sorted by relevance
| /drivers/infiniband/hw/mlx5/ |
| D | cq.c | 84 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64; in get_sw_cqe()
467 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64; in mlx5_poll_one()
893 cq->mcq.cqe_sz = cqe_size; in create_cq_kernel()
1003 MLX5_SET(cqc, cqc, cqe_sz, in mlx5_ib_create_cq()
1097 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64; in __mlx5_ib_cq_clean()
1104 dest64 = (cq->mcq.cqe_sz == 64) ? dest : dest + 64; in __mlx5_ib_cq_clean()
1106 memcpy(dest, cqe, cq->mcq.cqe_sz); in __mlx5_ib_cq_clean()
1354 MLX5_SET(cqc, cqc, cqe_sz, in mlx5_ib_resize_cq()
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| /drivers/net/ethernet/mellanox/mlx5/core/lib/ |
| D | aso.c | 60 mcq->cqe_sz = 64; in mlx5_aso_alloc_cq()
134 MLX5_SET(cqc, cqc_data, cqe_sz, CQE_STRIDE_128_PAD); in mlx5_aso_create_cq()
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| /drivers/net/ethernet/mellanox/mlx4/ |
| D | mlx4_en.h | 660 static inline struct mlx4_cqe *mlx4_en_get_cqe(void *buf, int idx, int cqe_sz) in mlx4_en_get_cqe() argument
662 return buf + idx * cqe_sz; in mlx4_en_get_cqe()
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| /drivers/net/ethernet/mellanox/mlx5/core/ |
| D | wq.c | 164 u8 log_wq_stride = MLX5_GET(cqc, cqc, cqe_sz) == CQE_STRIDE_64 ? 6 : 7; in mlx5_cqwq_create()
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| D | en_main.c | 1935 mcq->cqe_sz = 64; in mlx5e_alloc_cq_common()
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| /drivers/infiniband/hw/hns/ |
| D | hns_roce_cq.c | 336 hr_cq->cqe_size = hr_dev->caps.cqe_sz; in set_cqe_size()
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| D | hns_roce_device.h | 755 u32 cqe_sz; member
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| D | hns_roce_main.c | 412 resp.cqe_size = hr_dev->caps.cqe_sz; in hns_roce_alloc_ucontext()
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| D | hns_roce_hw_v2.h | 1153 u8 cqe_sz; member
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| D | hns_roce_hw_v2.c | 2027 calc_pg_sz(caps->max_cqes, caps->cqe_sz, caps->cqe_hop_num, in set_hem_page_size()
2086 caps->cqe_sz = HNS_ROCE_V3_CQE_SIZE; in apply_func_caps()
2234 caps->cqe_sz = resp_a->cqe_sz; in hns_roce_query_caps()
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| /drivers/vfio/pci/mlx5/ |
| D | cmd.c | 967 cq->mcq.cqe_sz = cqe_size; in mlx5vf_create_cq()
1529 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64; in get_sw_cqe()
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| /drivers/crypto/hisilicon/ |
| D | qm.c | 233 #define QM_MK_CQC_DW3_V1(hop_num, pg_sz, buf_sz, cqe_sz) \ argument
237 ((cqe_sz) << QM_CQ_CQE_SIZE_SHIFT))
239 #define QM_MK_CQC_DW3_V2(cqe_sz, cq_depth) \ argument
240 ((((u32)cq_depth) - 1) | ((cqe_sz) << QM_CQ_CQE_SIZE_SHIFT))
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| /drivers/net/ethernet/mellanox/mlx5/core/en/ |
| D | params.c | 877 MLX5_SET(cqc, cqc, cqe_sz, CQE_STRIDE_128_PAD); in mlx5e_build_common_cq_param()
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| /drivers/net/ethernet/mellanox/mlx5/core/fpga/ |
| D | conn.c | 471 conn->cq.mcq.cqe_sz = 64; in mlx5_fpga_conn_create_cq()
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| /drivers/net/ethernet/mellanox/mlx5/core/steering/ |
| D | dr_send.c | 1125 cq->mcq.cqe_sz = 64; in dr_create_cq()
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| /drivers/vdpa/mlx5/net/ |
| D | mlx5_vnet.c | 555 vcq->mcq.cqe_sz = 64; in cq_create()
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| /drivers/infiniband/hw/bnxt_re/ |
| D | ib_verbs.c | 4150 resp.cqe_sz = sizeof(struct cq_base); in bnxt_re_alloc_ucontext()
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