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/drivers/edac/
Damd64_edac.c379 csbase = pvt->csels[dct].csbases[csrow]; in get_cs_base_and_mask()
380 csmask = pvt->csels[dct].csmasks[csrow]; in get_cs_base_and_mask()
391 csbase = pvt->csels[dct].csbases[csrow]; in get_cs_base_and_mask()
392 csmask = pvt->csels[dct].csmasks[csrow >> 1]; in get_cs_base_and_mask()
407 csbase = pvt->csels[dct].csbases[csrow]; in get_cs_base_and_mask()
408 csmask = pvt->csels[dct].csmasks[csrow >> 1]; in get_cs_base_and_mask()
429 for (i = 0; i < pvt->csels[dct].b_cnt; i++)
432 pvt->csels[dct].csbases[i]
435 for (i = 0; i < pvt->csels[dct].m_cnt; i++)
1372 u32 *dcsb = ctrl ? pvt->csels[1].csbases : pvt->csels[0].csbases; in dct_debug_display_dimm_sizes()
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Damd64_edac.h166 #define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE)
167 #define csrow_sec_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases_sec[(i)] & DCSB_CS_ENABLE)
354 struct chip_select csels[NUM_CONTROLLERS]; member