Searched refs:csr_offset (Results 1 – 9 of 9) sorted by relevance
| /drivers/crypto/intel/qat/qat_common/ |
| D | adf_accel_devices.h | 242 #define ADF_CSR_WR(csr_base, csr_offset, val) \ argument
243 __raw_writel(val, csr_base + csr_offset)
246 #define ADF_CSR_RD(csr_base, csr_offset) __raw_readl(csr_base + csr_offset) argument
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| /drivers/firewire/ |
| D | core.h | 91 u32 (*read_csr)(struct fw_card *card, int csr_offset);
92 void (*write_csr)(struct fw_card *card, int csr_offset, u32 value);
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| D | core-card.c | 647 static u32 dummy_read_csr(struct fw_card *card, int csr_offset) in dummy_read_csr() argument
652 static void dummy_write_csr(struct fw_card *card, int csr_offset, u32 value) in dummy_write_csr() argument
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| D | ohci.c | 2676 static u32 ohci_read_csr(struct fw_card *card, int csr_offset) in ohci_read_csr() argument
2682 switch (csr_offset) { in ohci_read_csr()
2727 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value) in ohci_write_csr() argument
2732 switch (csr_offset) { in ohci_write_csr()
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| /drivers/net/ethernet/marvell/octeontx2/af/ |
| D | cgx.h | 40 #define CGXX_CMRX_RX_DMAC_CTL0 (0x1F8 + mac_ops->csr_offset)
46 #define CGXX_CMRX_RX_DMAC_CAM0 (0x200 + mac_ops->csr_offset)
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| D | lmac_common.h | 62 u64 csr_offset; member
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| D | rpm.c | 13 .csr_offset = 0x4e00,
45 .csr_offset = RPM2_CSR_OFFSET,
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| D | cgx.c | 1765 .csr_offset = 0,
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| /drivers/net/ethernet/cavium/thunder/ |
| D | thunder_bgx.c | 438 u64 csr_offset, cfg; in bgx_config_timestamping() local
448 csr_offset = BGX_GMP_GMI_RXX_FRM_CTL; in bgx_config_timestamping()
450 csr_offset = BGX_SMUX_RX_FRM_CTL; in bgx_config_timestamping()
452 cfg = bgx_reg_read(bgx, lmacid, csr_offset); in bgx_config_timestamping()
458 bgx_reg_write(bgx, lmacid, csr_offset, cfg); in bgx_config_timestamping()
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