Searched refs:ctrl_bit (Results 1 – 5 of 5) sorted by relevance
| /drivers/net/ethernet/hisilicon/hns3/hns3pf/ |
| D | hclge_mdio.c | 32 u8 ctrl_bit; member
62 hnae3_set_bit(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_START_B, 1); in hclge_mdio_write()
63 hnae3_set_field(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_ST_M, in hclge_mdio_write()
65 hnae3_set_field(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_OP_M, in hclge_mdio_write()
100 hnae3_set_bit(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_START_B, 1); in hclge_mdio_read()
101 hnae3_set_field(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_ST_M, in hclge_mdio_read()
103 hnae3_set_field(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_OP_M, in hclge_mdio_read()
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| /drivers/gpu/drm/omapdrm/dss/ |
| D | dss.c | 476 u8 ctrl_bit = ctrl_bits[channel]; in dss_lcd_clk_mux_dra7() local
481 REG_FLD_MOD(dss, DSS_CONTROL, 0, ctrl_bit, ctrl_bit); in dss_lcd_clk_mux_dra7()
489 REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit); in dss_lcd_clk_mux_dra7()
509 u8 ctrl_bit = ctrl_bits[channel]; in dss_lcd_clk_mux_omap5() local
513 REG_FLD_MOD(dss, DSS_CONTROL, 0, ctrl_bit, ctrl_bit); in dss_lcd_clk_mux_omap5()
520 REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit); in dss_lcd_clk_mux_omap5()
538 u8 ctrl_bit = ctrl_bits[channel]; in dss_lcd_clk_mux_omap4() local
542 REG_FLD_MOD(dss, DSS_CONTROL, 0, ctrl_bit, ctrl_bit); in dss_lcd_clk_mux_omap4()
549 REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit); in dss_lcd_clk_mux_omap4()
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| /drivers/hwmon/ |
| D | ltc2992.c | 129 u8 ctrl_bit; member
143 .ctrl_bit = LTC2992_GPIO1_BIT,
155 .ctrl_bit = LTC2992_GPIO2_BIT,
167 .ctrl_bit = LTC2992_GPIO3_BIT,
179 .ctrl_bit = LTC2992_GPIO4_BIT,
273 assign_bit(ltc2992_gpio_addr_map[offset].ctrl_bit, &gpio_ctrl, value); in ltc2992_gpio_set()
289 assign_bit(ltc2992_gpio_addr_map[gpio_nr].ctrl_bit, &gpio_ctrl_io, true); in ltc2992_gpio_set_multiple()
292 assign_bit(ltc2992_gpio_addr_map[gpio_nr].ctrl_bit, &gpio_ctrl, true); in ltc2992_gpio_set_multiple()
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| /drivers/net/ethernet/netronome/nfp/nfpcore/ |
| D | nfp_nsp_eth.c | 500 unsigned int val, const u64 ctrl_bit) in nfp_eth_set_bit_config() argument
524 entries[idx].control |= cpu_to_le64(ctrl_bit); in nfp_eth_set_bit_config()
561 #define NFP_ETH_SET_BIT_CONFIG(nsp, raw_idx, mask, val, ctrl_bit) \ argument
565 val, ctrl_bit); \
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| /drivers/regulator/ |
| D | rk808-regulator.c | 131 _n_voltages, _vr, _er, _lr, ctrl_bit,\ argument
147 .enable_mask = ENABLE_MASK(ctrl_bit),\
148 .enable_val = ENABLE_MASK(ctrl_bit),\
149 .disable_val = DISABLE_VAL(ctrl_bit),\
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