Searched refs:dcn3_03_soc (Results 1 – 3 of 3) sorted by relevance
112 struct _vcs_dpi_soc_bounding_box_st dcn3_03_soc = { variable173 bw_from_dram1 = uclk_mts * dcn3_03_soc.num_chans * in dcn303_get_optimal_dcfclk_fclk_for_uclk()174 dcn3_03_soc.dram_channel_width_bytes * (dcn3_03_soc.max_avg_dram_bw_use_normal_percent / 100); in dcn303_get_optimal_dcfclk_fclk_for_uclk()175 bw_from_dram2 = uclk_mts * dcn3_03_soc.num_chans * in dcn303_get_optimal_dcfclk_fclk_for_uclk()176 dcn3_03_soc.dram_channel_width_bytes * (dcn3_03_soc.max_avg_sdp_bw_use_normal_percent / 100); in dcn303_get_optimal_dcfclk_fclk_for_uclk()182 (dcn3_03_soc.fabric_datapath_to_dcn_data_return_bytes * in dcn303_get_optimal_dcfclk_fclk_for_uclk()183 (dcn3_03_soc.max_avg_sdp_bw_use_normal_percent / 100)); in dcn303_get_optimal_dcfclk_fclk_for_uclk()187 (dcn3_03_soc.return_bus_width_bytes * (dcn3_03_soc.max_avg_sdp_bw_use_normal_percent / 100)); in dcn303_get_optimal_dcfclk_fclk_for_uclk()208 dcn3_03_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans; in dcn303_fpu_update_bw_bounding_box()211 dcn3_03_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; in dcn303_fpu_update_bw_bounding_box()[all …]
14 extern struct _vcs_dpi_soc_bounding_box_st dcn3_03_soc;
880 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_03_soc; in init_soc_bounding_box()1261 dml_init_instance(&dc->dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30); in dcn303_resource_construct()