Home
last modified time | relevance | path

Searched refs:display_e2e_pipe_params_st (Results 1 – 25 of 48) sorted by relevance

12

/drivers/gpu/drm/amd/display/dc/dml/dcn32/
Ddcn32_fpu.h36 display_e2e_pipe_params_st *pipes,
40 display_e2e_pipe_params_st *pipe_e2e);
46 display_e2e_pipe_params_st *pipes,
52 display_e2e_pipe_params_st *pipes,
58 display_e2e_pipe_params_st *pipes,
66 display_e2e_pipe_params_st *pipes,
72 void dcn32_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes,
Ddisplay_rq_dlg_calc_32.h46 const display_e2e_pipe_params_st *e2e_pipe_param,
66 display_e2e_pipe_params_st *e2e_pipe_param,
/drivers/gpu/drm/amd/display/dc/dml/dcn20/
Ddcn20_fpu.h33 display_e2e_pipe_params_st *pipes);
37 display_e2e_pipe_params_st *pipes,
41 display_e2e_pipe_params_st *pipes,
46 display_e2e_pipe_params_st *pipes,
50 display_e2e_pipe_params_st *pipes,
78 display_e2e_pipe_params_st *pipes,
89 display_e2e_pipe_params_st *pipes);
Ddisplay_rq_dlg_calc_20v2.h64 const display_e2e_pipe_params_st *e2e_pipe_param,
Ddisplay_rq_dlg_calc_20.h64 const display_e2e_pipe_params_st *e2e_pipe_param,
Ddcn20_fpu.c989 display_e2e_pipe_params_st *pipes) in dcn20_populate_dml_writeback_from_context()
1029 display_e2e_pipe_params_st *pipes, in dcn20_fpu_set_wb_arb_params()
1136 display_e2e_pipe_params_st *pipes, in dcn20_calculate_dlg_params()
1310 display_e2e_pipe_params_st *pipes, in dcn20_populate_dml_pipes_from_context()
1723 display_e2e_pipe_params_st *pipes, in dcn20_calculate_wm()
2030 …display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_par… in dcn20_validate_bandwidth_internal()
2151 display_e2e_pipe_params_st *pipes, in dcn21_populate_dml_pipes_from_context()
2204 display_e2e_pipe_params_st *pipes, in calculate_wm_set_for_vlevel()
2231 display_e2e_pipe_params_st *pipes, in dcn21_calculate_wm()
2325 …display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_par… in dcn21_validate_bandwidth_fp()
[all …]
/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_resource.h51 display_e2e_pipe_params_st *pipes,
64 display_e2e_pipe_params_st *pipes,
71 display_e2e_pipe_params_st *pipes,
76 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
80 display_e2e_pipe_params_st *pipes,
106 display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel);
/drivers/gpu/drm/amd/display/dc/dml/dcn30/
Ddcn30_fpu.h36 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
40 display_e2e_pipe_params_st *pipes,
48 display_e2e_pipe_params_st *pipes,
68 display_e2e_pipe_params_st *pipes,
Ddisplay_rq_dlg_calc_30.h60 const display_e2e_pipe_params_st *e2e_pipe_param,
Ddcn30_fpu.c258 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes) in dcn30_fpu_populate_dml_writeback_from_context()
349 display_e2e_pipe_params_st *pipes, in dcn30_fpu_set_mcif_arb_params()
381 display_e2e_pipe_params_st *pipes, in dcn30_fpu_calculate_wm_and_dlg()
693 display_e2e_pipe_params_st *pipes, in dcn30_find_dummy_latency_index_for_fw_based_mclk_switch()
/drivers/gpu/drm/amd/display/dc/dcn31/
Ddcn31_resource.h45 display_e2e_pipe_params_st *pipes,
50 display_e2e_pipe_params_st *pipes,
55 display_e2e_pipe_params_st *pipes);
59 display_e2e_pipe_params_st *pipes,
Ddcn31_resource.c1615 display_e2e_pipe_params_st *pipes, in dcn31x_populate_dml_pipes_from_context()
1640 display_e2e_pipe_params_st *pipes, in dcn31_populate_dml_pipes_from_context()
1722 display_e2e_pipe_params_st *pipes, in dcn31_calculate_wm_and_dlg()
1734 display_e2e_pipe_params_st *pipes) in dcn31_populate_dml_writeback_from_context()
1744 display_e2e_pipe_params_st *pipes, in dcn31_set_mcif_arb_params()
1762 …display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_par… in dcn31_validate_bandwidth()
/drivers/gpu/drm/amd/display/dc/dml/
Ddisplay_mode_lib.h55 const display_e2e_pipe_params_st *e2e_pipe_param,
73 display_e2e_pipe_params_st *e2e_pipe_param,
78 const display_e2e_pipe_params_st *e2e_pipe_param,
105 display_e2e_pipe_params_st *pipes,
Ddisplay_mode_vba.h34 …tr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, …
75 …tr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, …
150 const display_e2e_pipe_params_st *pipes,
154 const display_e2e_pipe_params_st *pipes,
158 const display_e2e_pipe_params_st *pipes,
162 const display_e2e_pipe_params_st *pipes,
167 const display_e2e_pipe_params_st *pipes,
171 const display_e2e_pipe_params_st *pipes,
587 display_e2e_pipe_params_st cache_pipes[DC__NUM_DPP__MAX];
Ddisplay_mode_vba.c46 const display_e2e_pipe_params_st *pipes,
54 const display_e2e_pipe_params_st *pipes, in dml_get_voltage_level()
61 sizeof(display_e2e_pipe_params_st) * num_pipes) != 0; in dml_get_voltage_level()
82 …r) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, …
130 …r) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, …
209 const display_e2e_pipe_params_st *pipes, in get_total_immediate_flip_bytes()
218 const display_e2e_pipe_params_st *pipes, in get_total_immediate_flip_bw()
231 const display_e2e_pipe_params_st *pipes, in get_total_prefetch_bw()
245 const display_e2e_pipe_params_st *pipes, in get_total_surface_size_in_mall_bytes()
275 …_det_buffer_size_kbytes(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, in get_det_buffer_size_kbytes()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn31/
Ddcn31_fpu.h34 void dcn31_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes,
42 display_e2e_pipe_params_st *pipes,
56 display_e2e_pipe_params_st *pipes,
Ddisplay_rq_dlg_calc_31.h60 const display_e2e_pipe_params_st *e2e_pipe_param,
/drivers/gpu/drm/amd/display/dc/inc/
Dcore_types.h86 display_e2e_pipe_params_st *pipes,
101 display_e2e_pipe_params_st *pipes,
158 display_e2e_pipe_params_st *pipes);
163 display_e2e_pipe_params_st *pipes,
188 display_e2e_pipe_params_st *pipes,
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_resource.h118 display_e2e_pipe_params_st *pipes,
155 display_e2e_pipe_params_st *pipes,
/drivers/gpu/drm/amd/display/dc/dml/dcn314/
Ddcn314_fpu.h37 display_e2e_pipe_params_st *pipes,
Ddisplay_rq_dlg_calc_314.h61 const display_e2e_pipe_params_st *e2e_pipe_param,
/drivers/gpu/drm/amd/display/dc/dml/dcn301/
Ddcn301_fpu.h39 display_e2e_pipe_params_st *pipes,
Ddcn301_fpu.c296 display_e2e_pipe_params_st *pipes, in calculate_wm_set_for_vlevel()
414 display_e2e_pipe_params_st *pipes, in dcn301_calculate_wm_and_dlg_fp()
/drivers/gpu/drm/amd/display/dc/dml/dcn21/
Ddisplay_rq_dlg_calc_21.h64 const display_e2e_pipe_params_st *e2e_pipe_param,
/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_resource.h50 display_e2e_pipe_params_st *pipes,

12