Searched refs:divq (Results 1 – 8 of 8) sorted by relevance
| /drivers/clk/analogbits/ |
| D | wrpll-cln28hpc.c | 151 u8 divq = 0; in __wrpll_calc_divq() local
160 divq = 1; in __wrpll_calc_divq()
163 divq = ilog2(MAX_DIVQ_DIVISOR); in __wrpll_calc_divq()
166 divq = ilog2(s); in __wrpll_calc_divq()
167 *vco_rate = (u64)target_rate << divq; in __wrpll_calc_divq()
171 return divq; in __wrpll_calc_divq()
231 u8 fbdiv, divq, best_r, r; in wrpll_configure_for_rate() local
259 divq = __wrpll_calc_divq(target_rate, &target_vco_rate); in wrpll_configure_for_rate()
260 if (!divq) in wrpll_configure_for_rate()
262 c->divq = divq; in wrpll_configure_for_rate()
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| /drivers/clk/ |
| D | clk-highbank.c | 97 unsigned long divf, divq, vco_freq, reg; in clk_pll_recalc_rate() local
104 divq = (reg & HB_PLL_DIVQ_MASK) >> HB_PLL_DIVQ_SHIFT; in clk_pll_recalc_rate()
107 return vco_freq / (1 << divq); in clk_pll_recalc_rate()
113 u32 divq, divf; in clk_pll_calc() local
121 for (divq = 1; divq <= 6; divq++) { in clk_pll_calc()
122 if ((rate * (1 << divq)) >= HB_PLL_VCO_MIN_FREQ) in clk_pll_calc()
126 vco_freq = rate * (1 << divq); in clk_pll_calc()
130 *pdivq = divq; in clk_pll_calc()
137 u32 divq, divf; in clk_pll_round_rate() local
140 clk_pll_calc(rate, ref_freq, &divq, &divf); in clk_pll_round_rate()
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| /drivers/clk/imx/ |
| D | clk-sscg-pll.c | 74 int divq; member
133 for (temp_setup->divq = 0; temp_setup->divq <= PLL_DIVQ_MAX; in clk_sscg_divq_lookup()
134 temp_setup->divq++) { in clk_sscg_divq_lookup()
142 do_div(temp_setup->fout, 2 * (temp_setup->divq + 1)); in clk_sscg_divq_lookup()
331 u32 val, divr1, divf1, divr2, divf2, divq; in clk_sscg_pll_recalc_rate() local
339 divq = FIELD_GET(PLL_DIVQ_MASK, val); in clk_sscg_pll_recalc_rate()
348 do_div(temp64, (divr2 + 1) * (divq + 1)); in clk_sscg_pll_recalc_rate()
352 do_div(temp64, (divr1 + 1) * (divr2 + 1) * (divq + 1)); in clk_sscg_pll_recalc_rate()
378 val |= FIELD_PREP(PLL_DIVQ_MASK, setup->divq); in clk_sscg_pll_set_rate()
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| D | clk-frac-pll.c | 100 u32 val, divff, divfi, divq; in clk_pll_recalc_rate() local
105 divq = (FIELD_GET(PLL_OUTPUT_DIV_MASK, val) + 1) * 2; in clk_pll_recalc_rate()
113 do_div(temp64, divq); in clk_pll_recalc_rate()
116 do_div(rate, divq); in clk_pll_recalc_rate()
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| /drivers/clk/socfpga/ |
| D | clk-pll-a10.c | 38 unsigned long divf, divq, reg; in clk_pll_recalc_rate() local
44 divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT; in clk_pll_recalc_rate()
46 do_div(vco_freq, (1 + divq)); in clk_pll_recalc_rate()
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| D | clk-pll.c | 42 unsigned long divf, divq, reg; in clk_pll_recalc_rate() local
52 divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT; in clk_pll_recalc_rate()
54 do_div(vco_freq, (1 + divq)); in clk_pll_recalc_rate()
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| /drivers/media/pci/solo6x10/ |
| D | solo6x10-core.c | 525 u32 divq, divf; in solo_pci_probe() local
530 divq = 3; in solo_pci_probe()
533 divq = 2; in solo_pci_probe()
540 (divq << 12) | in solo_pci_probe()
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| /drivers/clk/sifive/ |
| D | sifive-prci.c | 71 c->divq = v; in __prci_wrpll_unpack()
105 r |= c->divq << PRCI_COREPLLCFG0_DIVQ_SHIFT; in __prci_wrpll_pack()
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