| /drivers/gpu/drm/amd/display/dc/dml/ |
| D | display_rq_dlg_helpers.c | 191 …dlg_regs_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_dlg_regs_st *dlg_regs) in print__dlg_regs_st() argument
197 dlg_regs->refcyc_h_blank_end); in print__dlg_regs_st()
200 dlg_regs->dlg_vblank_end); in print__dlg_regs_st()
203 dlg_regs->min_dst_y_next_start); in print__dlg_regs_st()
206 dlg_regs->refcyc_per_htotal); in print__dlg_regs_st()
209 dlg_regs->refcyc_x_after_scaler); in print__dlg_regs_st()
212 dlg_regs->dst_y_after_scaler); in print__dlg_regs_st()
215 dlg_regs->dst_y_prefetch); in print__dlg_regs_st()
218 dlg_regs->dst_y_per_vm_vblank); in print__dlg_regs_st()
221 dlg_regs->dst_y_per_row_vblank); in print__dlg_regs_st()
[all …]
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| D | display_mode_lib.h | 53 display_dlg_regs_st *dlg_regs,
71 display_dlg_regs_st *dlg_regs,
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| D | dml1_display_rq_dlg_calc.h | 56 struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
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| D | display_rq_dlg_helpers.h | 43 …lg_regs_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_dlg_regs_st *dlg_regs);
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| /drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| D | display_rq_dlg_calc_32.c | 207 display_dlg_regs_st *dlg_regs, in dml32_rq_dlg_get_dlg_reg() argument
266 memset(dlg_regs, 0, sizeof(*dlg_regs)); in dml32_rq_dlg_get_dlg_reg()
275 dlg_regs->ref_freq_to_pix_freq = (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19)); in dml32_rq_dlg_get_dlg_reg()
276 …dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal * dml_pow(2, … in dml32_rq_dlg_get_dlg_reg()
277 dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits in dml32_rq_dlg_get_dlg_reg()
290 dlg_regs->vready_after_vcount0 = vready_after_vcount0; in dml32_rq_dlg_get_dlg_reg()
292 dml_print("DML_DLG: %s: vready_after_vcount0 = %d\n", __func__, dlg_regs->vready_after_vcount0); in dml32_rq_dlg_get_dlg_reg()
334 dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end * ref_freq_to_pix_freq); in dml32_rq_dlg_get_dlg_reg()
341 dlg_regs->refcyc_h_blank_end = (unsigned int) (((double) hblank_end in dml32_rq_dlg_get_dlg_reg()
345 ASSERT(dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13)); in dml32_rq_dlg_get_dlg_reg()
[all …]
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| D | display_rq_dlg_calc_32.h | 64 display_dlg_regs_st *dlg_regs,
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_hw_sequencer_debug.c | 251 struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &s->dlg_attr; in dcn10_get_dlg_states() local
261 …pool->hubps[i]->inst, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_… in dcn10_get_dlg_states()
262 dlg_regs->refcyc_per_htotal, dlg_regs->refcyc_x_after_scaler, dlg_regs->dst_y_after_scaler, in dcn10_get_dlg_states()
263 dlg_regs->dst_y_prefetch, dlg_regs->dst_y_per_vm_vblank, dlg_regs->dst_y_per_row_vblank, in dcn10_get_dlg_states()
264 dlg_regs->dst_y_per_vm_flip, dlg_regs->dst_y_per_row_flip, dlg_regs->ref_freq_to_pix_freq, in dcn10_get_dlg_states()
265 dlg_regs->vratio_prefetch, dlg_regs->vratio_prefetch_c, dlg_regs->refcyc_per_pte_group_vblank_l, in dcn10_get_dlg_states()
266 dlg_regs->refcyc_per_pte_group_vblank_c, dlg_regs->refcyc_per_meta_chunk_vblank_l, in dcn10_get_dlg_states()
267 dlg_regs->refcyc_per_meta_chunk_vblank_c, dlg_regs->refcyc_per_pte_group_flip_l, in dcn10_get_dlg_states()
268 dlg_regs->refcyc_per_pte_group_flip_c, dlg_regs->refcyc_per_meta_chunk_flip_l, in dcn10_get_dlg_states()
269 dlg_regs->refcyc_per_meta_chunk_flip_c, dlg_regs->dst_y_per_pte_row_nom_l, in dcn10_get_dlg_states()
[all …]
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| D | dcn10_hw_sequencer.c | 235 struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &s->dlg_attr; in dcn10_log_hubp_states() local
241 …pool->hubps[i]->inst, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_… in dcn10_log_hubp_states()
242 dlg_regs->refcyc_per_htotal, dlg_regs->refcyc_x_after_scaler, dlg_regs->dst_y_after_scaler, in dcn10_log_hubp_states()
243 dlg_regs->dst_y_prefetch, dlg_regs->dst_y_per_vm_vblank, dlg_regs->dst_y_per_row_vblank, in dcn10_log_hubp_states()
244 dlg_regs->dst_y_per_vm_flip, dlg_regs->dst_y_per_row_flip, dlg_regs->ref_freq_to_pix_freq, in dcn10_log_hubp_states()
245 dlg_regs->vratio_prefetch, dlg_regs->vratio_prefetch_c, dlg_regs->refcyc_per_pte_group_vblank_l, in dcn10_log_hubp_states()
246 dlg_regs->refcyc_per_pte_group_vblank_c, dlg_regs->refcyc_per_meta_chunk_vblank_l, in dcn10_log_hubp_states()
247 dlg_regs->refcyc_per_meta_chunk_vblank_c, dlg_regs->refcyc_per_pte_group_flip_l, in dcn10_log_hubp_states()
248 dlg_regs->refcyc_per_pte_group_flip_c, dlg_regs->refcyc_per_meta_chunk_flip_l, in dcn10_log_hubp_states()
249 dlg_regs->refcyc_per_meta_chunk_flip_c, dlg_regs->dst_y_per_pte_row_nom_l, in dcn10_log_hubp_states()
[all …]
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| /drivers/gpu/drm/amd/display/dc/inc/hw/ |
| D | hubp.h | 98 struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
105 struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
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| D | mem_input.h | 98 struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
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| /drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| D | display_rq_dlg_calc_20v2.h | 62 display_dlg_regs_st *dlg_regs,
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| D | display_rq_dlg_calc_20.h | 62 display_dlg_regs_st *dlg_regs,
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| D | display_rq_dlg_calc_20v2.c | 1551 display_dlg_regs_st *dlg_regs, in dml20v2_rq_dlg_get_dlg_reg() argument
1591 dlg_regs, in dml20v2_rq_dlg_get_dlg_reg()
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| D | display_rq_dlg_calc_20.c | 1550 display_dlg_regs_st *dlg_regs, in dml20_rq_dlg_get_dlg_reg() argument
1590 dlg_regs, in dml20_rq_dlg_get_dlg_reg()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| D | display_rq_dlg_calc_21.h | 62 display_dlg_regs_st *dlg_regs,
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| D | display_rq_dlg_calc_21.c | 1659 display_dlg_regs_st *dlg_regs, in dml21_rq_dlg_get_dlg_reg() argument
1703 dlg_regs, in dml21_rq_dlg_get_dlg_reg()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| D | display_rq_dlg_calc_30.h | 58 display_dlg_regs_st *dlg_regs,
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| D | display_rq_dlg_calc_30.c | 1743 display_dlg_regs_st *dlg_regs, in dml30_rq_dlg_get_dlg_reg() argument
1783 dlg_regs, in dml30_rq_dlg_get_dlg_reg()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| D | display_rq_dlg_calc_31.h | 58 display_dlg_regs_st *dlg_regs,
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| D | display_rq_dlg_calc_31.c | 1562 display_dlg_regs_st *dlg_regs, in dml31_rq_dlg_get_dlg_reg() argument
1597 dlg_regs, in dml31_rq_dlg_get_dlg_reg()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| D | display_rq_dlg_calc_314.h | 59 display_dlg_regs_st *dlg_regs,
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| D | display_rq_dlg_calc_314.c | 1650 display_dlg_regs_st *dlg_regs, in dml314_rq_dlg_get_dlg_reg() argument
1685 dlg_regs, in dml314_rq_dlg_get_dlg_reg()
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_hwseq.c | 1439 struct _vcs_dpi_display_dlg_regs_st old_dlg_attr = old_pipe->dlg_regs; in dcn20_detect_pipe_changes()
1441 struct _vcs_dpi_display_dlg_regs_st *new_dlg_attr = &new_pipe->dlg_regs; in dcn20_detect_pipe_changes()
1484 if (memcmp(&old_dlg_attr, &new_pipe->dlg_regs, sizeof(old_dlg_attr)) || in dcn20_detect_pipe_changes()
1521 &pipe_ctx->dlg_regs, in dcn20_update_dchubp_dpp()
1533 &pipe_ctx->dlg_regs, in dcn20_update_dchubp_dpp()
2151 pipe_ctx->dlg_regs.min_dst_y_next_start); in dcn20_optimize_bandwidth()
2199 &pipe_ctx->dlg_regs, in dcn20_update_bandwidth()
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| /drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| D | dcn_calcs.c | 459 struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &pipe->dlg_regs; in dcn_bw_calc_rq_dlg_ttu() local
470 memset(dlg_regs, 0, sizeof(*dlg_regs)); in dcn_bw_calc_rq_dlg_ttu()
511 dlg_regs, in dcn_bw_calc_rq_dlg_ttu()
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| D | core_types.h | 396 struct _vcs_dpi_display_dlg_regs_st dlg_regs; member
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