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Searched refs:dma_base (Results 1 – 25 of 39) sorted by relevance

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/drivers/dma/
Dmv_xor_v2.c157 void __iomem *dma_base; member
231 writel(num_of_desc, xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_ADD_OFF); in mv_xor_v2_add_desc_to_desq()
241 writel(num_of_desc, xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_DEALLOC_OFF); in mv_xor_v2_free_desc_from_desq()
251 xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_CTRL_OFF); in mv_xor_v2_set_desc_size()
265 reg = readl(xor_dev->dma_base + MV_XOR_V2_DMA_IMSG_THRD_OFF); in mv_xor_v2_enable_imsg_thrd()
269 writel(reg, xor_dev->dma_base + MV_XOR_V2_DMA_IMSG_THRD_OFF); in mv_xor_v2_enable_imsg_thrd()
272 reg = readl(xor_dev->dma_base + MV_XOR_V2_DMA_IMSG_TMOT); in mv_xor_v2_enable_imsg_thrd()
275 writel(reg, xor_dev->dma_base + MV_XOR_V2_DMA_IMSG_TMOT); in mv_xor_v2_enable_imsg_thrd()
284 reg = readl(xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_DONE_OFF); in mv_xor_v2_interrupt_handler()
542 reg = readl(xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_DONE_OFF); in mv_xor_v2_get_pending_params()
[all …]
/drivers/net/ethernet/8390/
Detherh.c67 void __iomem *dma_base; member
309 void __iomem *dma_base, *addr; in etherh_block_output() local
327 dma_base = etherh_priv(dev)->dma_base; in etherh_block_output()
348 writesw (dma_base, buf, count >> 1); in etherh_block_output()
350 writesb (dma_base, buf, count); in etherh_block_output()
374 void __iomem *dma_base, *addr; in etherh_block_input() local
386 dma_base = etherh_priv(dev)->dma_base; in etherh_block_input()
397 readsw (dma_base, buf, count >> 1); in etherh_block_input()
399 buf[count - 1] = readb (dma_base); in etherh_block_input()
401 readsb (dma_base, buf, count); in etherh_block_input()
[all …]
/drivers/ata/
Dpata_octeon_cf.c59 u64 dma_base; member
249 c = (cf_port->dma_base & 8) >> 3; in octeon_cf_set_dmamode()
279 cvmx_write_csr(cf_port->dma_base + DMA_TIM, dma_tim.u64); in octeon_cf_set_dmamode()
550 cvmx_write_csr(cf_port->dma_base + DMA_INT, mio_boot_dma_int.u64); in octeon_cf_dma_start()
553 cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, mio_boot_dma_int.u64); in octeon_cf_dma_start()
581 cvmx_write_csr(cf_port->dma_base + DMA_CFG, mio_boot_dma_cfg.u64); in octeon_cf_dma_start()
604 dma_cfg.u64 = cvmx_read_csr(cf_port->dma_base + DMA_CFG); in octeon_cf_dma_finished()
614 cvmx_write_csr(cf_port->dma_base + DMA_CFG, dma_cfg.u64); in octeon_cf_dma_finished()
618 cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, dma_int.u64); in octeon_cf_dma_finished()
622 cvmx_write_csr(cf_port->dma_base + DMA_INT, dma_int.u64); in octeon_cf_dma_finished()
[all …]
/drivers/gpu/drm/nouveau/nvkm/falcon/
Dbase.c40 nvkm_falcon_dma_wr(struct nvkm_falcon *falcon, const u8 *img, u64 dma_addr, u32 dma_base, in nvkm_falcon_dma_wr() argument
54 dma_start = dma_base; in nvkm_falcon_dma_wr()
55 dma_addr += dma_base; in nvkm_falcon_dma_wr()
59 type, mem_base, len, dma_base, dma_addr - dma_base, dma_start); in nvkm_falcon_dma_wr()
68 src = dma_base; in nvkm_falcon_dma_wr()
81 printk(KERN_CONT " <- %08x+%08x", dma_base, in nvkm_falcon_dma_wr()
82 src + i - dma_base - (x * 4)); in nvkm_falcon_dma_wr()
Dga102.c34 ga102_flcn_dma_xfer(struct nvkm_falcon *falcon, u32 mem_base, u32 dma_base, u32 cmd) in ga102_flcn_dma_xfer() argument
37 nvkm_falcon_wr32(falcon, 0x11c, dma_base); in ga102_flcn_dma_xfer()
/drivers/media/platform/samsung/s5p-mfc/
Ds5p_mfc_ctrl.c176 mfc_write(dev, dev->dma_base[BANK_L_CTX], in s5p_mfc_init_memctrl()
179 &dev->dma_base[BANK_L_CTX]); in s5p_mfc_init_memctrl()
181 mfc_write(dev, dev->dma_base[BANK_L_CTX], in s5p_mfc_init_memctrl()
183 mfc_write(dev, dev->dma_base[BANK_R_CTX], in s5p_mfc_init_memctrl()
186 &dev->dma_base[BANK_L_CTX], in s5p_mfc_init_memctrl()
187 &dev->dma_base[BANK_R_CTX]); in s5p_mfc_init_memctrl()
Ds5p_mfc_opr_v5.c30 #define OFFSETA(x) (((x) - dev->dma_base[BANK_L_CTX]) >> MFC_OFFSET_SHIFT)
31 #define OFFSETB(x) (((x) - dev->dma_base[BANK_R_CTX]) >> MFC_OFFSET_SHIFT)
233 ctx->shm.ofs = ctx->shm.dma - dev->dma_base[BANK_L_CTX]; in s5p_mfc_alloc_instance_buffer_v5()
532 *y_addr = dev->dma_base[BANK_R_CTX] + in s5p_mfc_get_enc_frame_buffer_v5()
534 *c_addr = dev->dma_base[BANK_R_CTX] + in s5p_mfc_get_enc_frame_buffer_v5()
1212 s5p_mfc_set_enc_frame_buffer_v5(ctx, dev->dma_base[BANK_R_CTX], in s5p_mfc_run_enc_frame()
1213 dev->dma_base[BANK_R_CTX]); in s5p_mfc_run_enc_frame()
1222 dev->dma_base[BANK_R_CTX], in s5p_mfc_run_enc_frame()
1223 dev->dma_base[BANK_R_CTX]); in s5p_mfc_run_enc_frame()
Ds5p_mfc.c1162 mfc_dev->dma_base[BANK_L_CTX] = mfc_dev->fw_buf.dma; in s5p_mfc_configure_2port_memory()
1177 mfc_dev->dma_base[BANK_R_CTX] = bank2_dma_addr - align_size; in s5p_mfc_configure_2port_memory()
1222 mfc_dev->dma_base[BANK_L_CTX] = mfc_dev->mem_base; in s5p_mfc_configure_common_memory()
1223 mfc_dev->dma_base[BANK_R_CTX] = mfc_dev->mem_base; in s5p_mfc_configure_common_memory()
1233 mfc_dev->dma_base[BANK_L_CTX] += offset; in s5p_mfc_configure_common_memory()
1234 mfc_dev->dma_base[BANK_R_CTX] += offset; in s5p_mfc_configure_common_memory()
Ds5p_mfc_opr.c58 dma_addr_t base = dev->dma_base[mem_ctx]; in s5p_mfc_alloc_priv_buf()
/drivers/net/ethernet/cortina/
Dgemini.c110 void __iomem *dma_base; member
525 readl(port->dma_base + GMAC_AHB_WEIGHT_REG); in gmac_init()
526 writel(ahb_weight.bits32, port->dma_base + GMAC_AHB_WEIGHT_REG); in gmac_init()
529 port->dma_base + GMAC_TX_WEIGHTING_CTRL_0_REG); in gmac_init()
531 port->dma_base + GMAC_TX_WEIGHTING_CTRL_1_REG); in gmac_init()
559 rwptr_reg = port->dma_base + GMAC_SW_TX_QUEUE0_PTR_REG; in gmac_setup_txqs()
582 port->dma_base + GMAC_SW_TX_QUEUE_BASE_REG); in gmac_setup_txqs()
683 rwptr_reg = port->dma_base + GMAC_SW_TX_QUEUE0_PTR_REG; in gmac_cleanup_txqs()
693 writel(0, port->dma_base + GMAC_SW_TX_QUEUE_BASE_REG); in gmac_cleanup_txqs()
1267 ptr_reg = port->dma_base + GMAC_SW_TX_QUEUE_PTR_REG(txq_num); in gmac_start_xmit()
[all …]
/drivers/mmc/host/
Dcavium-thunderx.c86 host->dma_base = host->base; in thunder_mmc_probe()
181 dma_cfg = readq(host->dma_base + MIO_EMM_DMA_CFG(host)); in thunder_mmc_remove()
183 writeq(dma_cfg, host->dma_base + MIO_EMM_DMA_CFG(host)); in thunder_mmc_remove()
Dcavium.c387 fifo_cfg = readq(host->dma_base + MIO_EMM_DMA_FIFO_CFG(host)); in finish_dma_sg()
396 writeq(BIT_ULL(16), host->dma_base + MIO_EMM_DMA_FIFO_CFG(host)); in finish_dma_sg()
538 writeq(dma_cfg, host->dma_base + MIO_EMM_DMA_CFG(host)); in prepare_dma_single()
544 writeq(addr, host->dma_base + MIO_EMM_DMA_ADR(host)); in prepare_dma_single()
566 writeq(0, host->dma_base + MIO_EMM_DMA_FIFO_CFG(host)); in prepare_dma_sg()
573 writeq(addr, host->dma_base + MIO_EMM_DMA_FIFO_ADR(host)); in prepare_dma_sg()
596 writeq(fifo_cmd, host->dma_base + MIO_EMM_DMA_FIFO_CMD(host)); in prepare_dma_sg()
613 writeq(BIT_ULL(16), host->dma_base + MIO_EMM_DMA_FIFO_CFG(host)); in prepare_dma_sg()
Dcavium-octeon.c218 host->dma_base = base; in octeon_mmc_probe()
309 dma_cfg = readq(host->dma_base + MIO_EMM_DMA_CFG(host)); in octeon_mmc_remove()
311 writeq(dma_cfg, host->dma_base + MIO_EMM_DMA_CFG(host)); in octeon_mmc_remove()
/drivers/gpu/drm/msm/dsi/
Ddsi.h63 bool msm_dsi_manager_cmd_xfer_trigger(int id, u32 dma_base, u32 len);
85 u32 dma_base, u32 len);
Ddsi_host.c1288 int dsi_dma_base_get_6g(struct msm_dsi_host *msm_host, uint64_t *dma_base) in dsi_dma_base_get_6g() argument
1293 if (!dma_base) in dsi_dma_base_get_6g()
1297 priv->kms->aspace, dma_base); in dsi_dma_base_get_6g()
1300 int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *dma_base) in dsi_dma_base_get_v2() argument
1302 if (!dma_base) in dsi_dma_base_get_v2()
1305 *dma_base = msm_host->tx_buf_paddr; in dsi_dma_base_get_v2()
1313 uint64_t dma_base; in dsi_cmd_dma_tx() local
1316 ret = cfg_hnd->ops->dma_base_get(msm_host, &dma_base); in dsi_cmd_dma_tx()
1327 msm_host->id, dma_base, len); in dsi_cmd_dma_tx()
2213 void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base, in msm_dsi_host_cmd_xfer_commit() argument
[all …]
Ddsi_manager.c611 bool msm_dsi_manager_cmd_xfer_trigger(int id, u32 dma_base, u32 len) in msm_dsi_manager_cmd_xfer_trigger() argument
621 msm_dsi_host_cmd_xfer_commit(msm_dsi0->host, dma_base, len); in msm_dsi_manager_cmd_xfer_trigger()
623 msm_dsi_host_cmd_xfer_commit(host, dma_base, len); in msm_dsi_manager_cmd_xfer_trigger()
/drivers/net/ethernet/broadcom/
Dbgmac.c585 ring->dma_base); in bgmac_dma_ring_desc_free()
638 &ring->dma_base, in bgmac_dma_alloc()
649 ring->index_base = lower_32_bits(ring->dma_base); in bgmac_dma_alloc()
663 &ring->dma_base, in bgmac_dma_alloc()
674 ring->index_base = lower_32_bits(ring->dma_base); in bgmac_dma_alloc()
697 lower_32_bits(ring->dma_base)); in bgmac_dma_init()
699 upper_32_bits(ring->dma_base)); in bgmac_dma_init()
715 lower_32_bits(ring->dma_base)); in bgmac_dma_init()
717 upper_32_bits(ring->dma_base)); in bgmac_dma_init()
/drivers/ntb/test/
Dntb_tool.c214 dma_addr_t dma_base; member
589 &inmw->dma_base, GFP_KERNEL); in tool_setup_mw()
593 if (!IS_ALIGNED(inmw->dma_base, addr_align)) { in tool_setup_mw()
598 ret = ntb_mw_set_trans(tc->ntb, pidx, widx, inmw->dma_base, inmw->size); in tool_setup_mw()
611 inmw->dma_base); in tool_setup_mw()
613 inmw->dma_base = 0; in tool_setup_mw()
628 inmw->mm_base, inmw->dma_base); in tool_free_mw()
632 inmw->dma_base = 0; in tool_free_mw()
673 &inmw->dma_base); in tool_mw_trans_read()
/drivers/usb/mtu3/
Dmtu3_qmu.c122 dma_addr_t dma_base = ring->dma; in gpd_dma_to_virt() local
124 u32 offset = (dma_addr - dma_base) / sizeof(*gpd_head); in gpd_dma_to_virt()
135 dma_addr_t dma_base = ring->dma; in gpd_virt_to_dma() local
143 return dma_base + (offset * sizeof(*gpd)); in gpd_virt_to_dma()
/drivers/spi/
Dspi-pic32.c96 dma_addr_t dma_base; member
366 cfg.src_addr = pic32s->dma_base + buf_offset; in pic32_spi_dma_config()
367 cfg.dst_addr = pic32s->dma_base + buf_offset; in pic32_spi_dma_config()
717 pic32s->dma_base = mem->start; in pic32_spi_hw_probe()
/drivers/gpu/drm/nouveau/include/nvkm/core/
Dfalcon.h37 void (*xfer)(struct nvkm_falcon *, u32 mem_base, u32 dma_base, u32 cmd);
49 int nvkm_falcon_dma_wr(struct nvkm_falcon *, const u8 *img, u64 dma_addr, u32 dma_base,
/drivers/gpu/drm/nouveau/include/nvfw/
Dpmu.h15 u32 dma_base; member
/drivers/net/ethernet/mscc/
Docelot_fdma.c239 dma_addr_t new_llp, dma_base; in ocelot_fdma_rx_restart() local
259 dma_base = rx_ring->dcbs_dma; in ocelot_fdma_rx_restart()
262 idx = ocelot_fdma_dma_idx(dma_base, llp_prev); in ocelot_fdma_rx_restart()
264 new_llp = ocelot_fdma_idx_dma(dma_base, idx); in ocelot_fdma_rx_restart()
/drivers/media/platform/nvidia/tegra-vde/
Dv4l2.c181 &tb->dma_base[i]); in tegra_buf_init()
198 tb->dma_base[i] = iova_dma_addr(&vde->iova, tb->iova[i]); in tegra_buf_init()
200 tb->dma_base[i] = vb2_dma_contig_plane_dma_addr(vb, i); in tegra_buf_init()
269 tb->dma_addr[i] = tb->dma_base[i] + offset; in tegra_buf_prepare()
/drivers/vfio/pci/pds/
Ddirty.c65 i, le64_to_cpu(region_info[i].dma_base), in pds_vfio_print_guest_region_info()
250 region_info->dma_base = cpu_to_le64(region_start); in pds_vfio_dirty_enable()

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