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Searched refs:dpte_row_height (Results 1 – 19 of 19) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dml/
Ddml1_display_rq_dlg_calc.c615 unsigned int dpte_row_height; in get_surf_rq_param() local
809 dpte_row_height = 0; in get_surf_rq_param()
859 rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height; in get_surf_rq_param()
865 data_pitch * dpte_row_height - 1, in get_surf_rq_param()
884 rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height; in get_surf_rq_param()
896 rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height; in get_surf_rq_param()
951 if (rq_dlg_param->dpte_row_height != func_dpte_row_height) { in get_surf_rq_param()
954 rq_dlg_param->dpte_row_height); in get_surf_rq_param()
1556 dpte_row_height_l = rq_dlg_param->rq_l.dpte_row_height; in dml1_rq_dlg_get_dlg_params()
1557 dpte_row_height_c = rq_dlg_param->rq_c.dpte_row_height; in dml1_rq_dlg_get_dlg_params()
Ddisplay_rq_dlg_helpers.c89 rq_dlg_param->dpte_row_height); in print__data_rq_dlg_params_st()
Ddisplay_mode_structs.h587 unsigned int dpte_row_height; member
Ddisplay_mode_vba.h830 unsigned int dpte_row_height[DC__NUM_DPP__MAX]; member
/drivers/gpu/drm/amd/display/dc/dml/dcn20/
Ddisplay_rq_dlg_calc_20v2.c198 rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_l.dpte_row_height), in extract_rq_regs()
203 rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_c.dpte_row_height), in extract_rq_regs()
608 unsigned int dpte_row_height; in get_meta_and_pte_attr() local
625 dpte_row_height = 1 << log2_dpte_row_height; in get_meta_and_pte_attr()
626 dpte_row_width_ub = dml_round_to_multiple(data_pitch * dpte_row_height - 1, in get_meta_and_pte_attr()
652 rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height; in get_meta_and_pte_attr()
1149 dpte_row_height_l = rq_dlg_param->rq_l.dpte_row_height; in dml20v2_rq_dlg_get_dlg_params()
1150 dpte_row_height_c = rq_dlg_param->rq_c.dpte_row_height; in dml20v2_rq_dlg_get_dlg_params()
Ddisplay_rq_dlg_calc_20.c198 rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_l.dpte_row_height), in extract_rq_regs()
203 rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_c.dpte_row_height), in extract_rq_regs()
608 unsigned int dpte_row_height; in get_meta_and_pte_attr() local
625 dpte_row_height = 1 << log2_dpte_row_height; in get_meta_and_pte_attr()
626 dpte_row_width_ub = dml_round_to_multiple(data_pitch * dpte_row_height - 1, in get_meta_and_pte_attr()
652 rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height; in get_meta_and_pte_attr()
1148 dpte_row_height_l = rq_dlg_param->rq_l.dpte_row_height; in dml20_rq_dlg_get_dlg_params()
1149 dpte_row_height_c = rq_dlg_param->rq_c.dpte_row_height; in dml20_rq_dlg_get_dlg_params()
Ddisplay_mode_vba_20.c154 unsigned int *dpte_row_height,
213 unsigned int dpte_row_height,
881 unsigned int *dpte_row_height, in CalculateVMAndRowBytes() argument
1039 *dpte_row_height = in CalculateVMAndRowBytes()
1055 (double) (Pitch * *dpte_row_height - 1) in CalculateVMAndRowBytes()
1059 *dpte_row_height = PixelPTEReqHeight; in CalculateVMAndRowBytes()
1064 *dpte_row_height = dml_min(PixelPTEReqWidth, *MacroTileWidth); in CalculateVMAndRowBytes()
1891 &mode_lib->vba.dpte_row_height[k], in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1970 mode_lib->vba.dpte_row_height[k], in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2290 mode_lib->vba.dpte_row_height[k], in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
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Ddisplay_mode_vba_20v2.c178 unsigned int *dpte_row_height,
237 unsigned int dpte_row_height,
941 unsigned int *dpte_row_height, in CalculateVMAndRowBytes() argument
1099 *dpte_row_height = in CalculateVMAndRowBytes()
1115 (double) (Pitch * *dpte_row_height - 1) in CalculateVMAndRowBytes()
1119 *dpte_row_height = PixelPTEReqHeight; in CalculateVMAndRowBytes()
1124 *dpte_row_height = dml_min(PixelPTEReqWidth, *MacroTileWidth); in CalculateVMAndRowBytes()
1927 &mode_lib->vba.dpte_row_height[k], in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2006 mode_lib->vba.dpte_row_height[k], in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2324 mode_lib->vba.dpte_row_height[k], in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
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/drivers/gpu/drm/amd/display/dc/dml/dcn21/
Ddisplay_rq_dlg_calc_21.c177 dml_log2(rq_param->dlg.rq_l.dpte_row_height), in extract_rq_regs()
183 dml_log2(rq_param->dlg.rq_c.dpte_row_height), in extract_rq_regs()
606 unsigned int dpte_row_height; in get_meta_and_pte_attr() local
626 dpte_row_height = 1 << log2_dpte_row_height; in get_meta_and_pte_attr()
628 data_pitch * dpte_row_height - 1, in get_meta_and_pte_attr()
654 rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height; in get_meta_and_pte_attr()
1200 dpte_row_height_l = rq_dlg_param->rq_l.dpte_row_height; in dml_rq_dlg_get_dlg_params()
1201 dpte_row_height_c = rq_dlg_param->rq_c.dpte_row_height; in dml_rq_dlg_get_dlg_params()
Ddisplay_mode_vba_21.c195 unsigned int *dpte_row_height,
268 unsigned int dpte_row_height,
433 unsigned int dpte_row_height[],
1283 unsigned int *dpte_row_height, in CalculateVMAndRowBytes()
1418 *dpte_row_height = dml_min(128, in CalculateVMAndRowBytes()
1423 …*dpte_row_width_ub = (dml_ceil((double) (Pitch * *dpte_row_height - 1) / *PixelPTEReqWidth, 1) + 1… in CalculateVMAndRowBytes()
1426 *dpte_row_height = *PixelPTEReqHeight; in CalculateVMAndRowBytes()
1430 *dpte_row_height = dml_min(*PixelPTEReqWidth, *MacroTileWidth); in CalculateVMAndRowBytes()
1964 &locals->dpte_row_height[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1994 locals->dpte_row_height[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn31/
Ddisplay_rq_dlg_calc_31.c119 …rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_l.dpte_row_height),… in extract_rq_regs()
123 …rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_c.dpte_row_height),… in extract_rq_regs()
578 unsigned int dpte_row_height; in get_meta_and_pte_attr() local
594 dpte_row_height = 1 << log2_dpte_row_height; in get_meta_and_pte_attr()
595 …dpte_row_width_ub = dml_round_to_multiple(data_pitch * dpte_row_height - 1, dpte_req_width, 1) + d… in get_meta_and_pte_attr()
615 rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height; in get_meta_and_pte_attr()
1142 dpte_row_height_l = rq_dlg_param->rq_l.dpte_row_height; in dml_rq_dlg_get_dlg_params()
1143 dpte_row_height_c = rq_dlg_param->rq_c.dpte_row_height; in dml_rq_dlg_get_dlg_params()
Ddisplay_mode_vba_31.c222 unsigned int *dpte_row_height,
415 int dpte_row_height[],
1815 unsigned int *dpte_row_height,
1951 …*dpte_row_height = dml_min(128, 1 << (unsigned int) dml_floor(dml_log2(PTEBufferSizeInRequests * *…
1952 …*dpte_row_width_ub = (dml_ceil((double)(Pitch * *dpte_row_height - 1) / *PixelPTEReqWidth, 1) + 1)…
1955 *dpte_row_height = *PixelPTEReqHeight;
1959 *dpte_row_height = dml_min(*PixelPTEReqWidth, *MacroTileWidth);
2406 &v->dpte_row_height[k],
2446 v->dpte_row_height[k],
3034 v->dpte_row_height,
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn30/
Ddisplay_rq_dlg_calc_30.c122 rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_l.dpte_row_height), in extract_rq_regs()
127 rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_c.dpte_row_height), in extract_rq_regs()
577 unsigned int dpte_row_height = 0; in get_meta_and_pte_attr() local
593 dpte_row_height = 1 << log2_dpte_row_height; in get_meta_and_pte_attr()
594 dpte_row_width_ub = dml_round_to_multiple(data_pitch * dpte_row_height - 1, in get_meta_and_pte_attr()
620 rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height; in get_meta_and_pte_attr()
1301 dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height; in dml_rq_dlg_get_dlg_params()
1302 dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height; in dml_rq_dlg_get_dlg_params()
Ddisplay_mode_vba_30.c205 unsigned int *dpte_row_height,
261 unsigned int dpte_row_height,
451 int dpte_row_height[],
1681 unsigned int *dpte_row_height, in CalculateVMAndRowBytes()
1803 *dpte_row_height = 1; in CalculateVMAndRowBytes()
1805 …*dpte_row_height = dml_min(128, 1 << (unsigned int) dml_floor(dml_log2(PTEBufferSizeInRequests * *… in CalculateVMAndRowBytes()
1809 *dpte_row_height = *PixelPTEReqHeight; in CalculateVMAndRowBytes()
1813 *dpte_row_height = dml_min(*PixelPTEReqWidth, *MacroTileWidth); in CalculateVMAndRowBytes()
2275 &v->dpte_row_height[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2316 v->dpte_row_height[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn314/
Ddisplay_rq_dlg_calc_314.c207 …rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_l.dpte_row_height),… in extract_rq_regs()
211 …rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_c.dpte_row_height),… in extract_rq_regs()
666 unsigned int dpte_row_height; in get_meta_and_pte_attr() local
682 dpte_row_height = 1 << log2_dpte_row_height; in get_meta_and_pte_attr()
683 …dpte_row_width_ub = dml_round_to_multiple(data_pitch * dpte_row_height - 1, dpte_req_width, 1) + d… in get_meta_and_pte_attr()
703 rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height; in get_meta_and_pte_attr()
1230 dpte_row_height_l = rq_dlg_param->rq_l.dpte_row_height; in dml_rq_dlg_get_dlg_params()
1231 dpte_row_height_c = rq_dlg_param->rq_c.dpte_row_height; in dml_rq_dlg_get_dlg_params()
Ddisplay_mode_vba_314.c234 unsigned int *dpte_row_height,
427 int dpte_row_height[],
1835 unsigned int *dpte_row_height,
1971 …*dpte_row_height = dml_min(128, 1 << (unsigned int) dml_floor(dml_log2(PTEBufferSizeInRequests * *…
1972 …*dpte_row_width_ub = (dml_ceil((double)(Pitch * *dpte_row_height - 1) / *PixelPTEReqWidth, 1) + 1)…
1975 *dpte_row_height = *PixelPTEReqHeight;
1979 *dpte_row_height = dml_min(*PixelPTEReqWidth, *MacroTileWidth);
2427 &v->dpte_row_height[k],
2467 v->dpte_row_height[k],
3055 v->dpte_row_height,
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/drivers/gpu/drm/amd/display/dc/dml/dcn32/
Ddisplay_mode_vba_util_32.h464 unsigned int *dpte_row_height,
792 unsigned int dpte_row_height,
906 unsigned int dpte_row_height[],
Ddisplay_mode_vba_util_32.c2290 unsigned int *dpte_row_height, in dml32_CalculateVMAndRowBytes()
2454 *dpte_row_height = dml_min(128, 1 << (unsigned int) dml_floor(dml_log2(PTEBufferSizeInRequests * in dml32_CalculateVMAndRowBytes()
2466 dml_print("DML::%s: dpte_row_height = %d\n", __func__, *dpte_row_height); in dml32_CalculateVMAndRowBytes()
2468 *dpte_row_width_ub = dml_ceil(((double) Pitch * (double) *dpte_row_height - 1), in dml32_CalculateVMAndRowBytes()
2479 *dpte_row_height = *PixelPTEReqHeight; in dml32_CalculateVMAndRowBytes()
2482 *dpte_row_width_ub = (dml_ceil((Pitch * *dpte_row_height / *PixelPTEReqHeight - 1) / in dml32_CalculateVMAndRowBytes()
2495 *dpte_row_height = dml_min(*PixelPTEReqWidth, MacroTileWidth); in dml32_CalculateVMAndRowBytes()
2515 dml_print("DML::%s: dpte_row_height = %d\n", __func__, *dpte_row_height); in dml32_CalculateVMAndRowBytes()
4137 unsigned int dpte_row_height, in dml32_CalculateFlipSchedule() argument
4216 min_row_time = dml_min(dpte_row_height * in dml32_CalculateFlipSchedule()
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Ddisplay_mode_vba_32.c489 v->dpte_row_height, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1057 v->dpte_row_height[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1303 v->dpte_row_height, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2782 mode_lib->vba.dpte_row_height, in dml32_ModeSupportAndSystemConfigurationFull()
3495 mode_lib->vba.dpte_row_height[k], in dml32_ModeSupportAndSystemConfigurationFull()