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Searched refs:dsaf_write_dev (Results 1 – 7 of 7) sorted by relevance

/drivers/net/ethernet/hisilicon/hns/
Dhns_dsaf_rcb.c102 dsaf_write_dev(q, RCB_RING_PREFETCH_EN_REG, 0); in hns_rcb_reset_ring_hw()
104 dsaf_write_dev(q, RCB_RING_T0_BE_RST, 1); in hns_rcb_reset_ring_hw()
111 dsaf_write_dev(q, RCB_RING_T0_BE_RST, 0); in hns_rcb_reset_ring_hw()
113 dsaf_write_dev(q, RCB_RING_T0_BE_RST, 1); in hns_rcb_reset_ring_hw()
121 dsaf_write_dev(q, RCB_RING_T0_BE_RST, 0); in hns_rcb_reset_ring_hw()
143 dsaf_write_dev(q, RCB_RING_INTMSK_TXWL_REG, int_mask_en); in hns_rcb_int_ctrl_hw()
144 dsaf_write_dev(q, RCB_RING_INTMSK_TX_OVERTIME_REG, in hns_rcb_int_ctrl_hw()
149 dsaf_write_dev(q, RCB_RING_INTMSK_RXWL_REG, int_mask_en); in hns_rcb_int_ctrl_hw()
150 dsaf_write_dev(q, RCB_RING_INTMSK_RX_OVERTIME_REG, in hns_rcb_int_ctrl_hw()
158 dsaf_write_dev(q, RCB_RING_INTSTS_TX_RING_REG, 1); in hns_rcb_int_clr_hw()
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Dhns_dsaf_main.c338 dsaf_write_dev(dsaf_dev, in hns_dsaf_sbm_cfg()
408 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); in hns_dsaf_sbm_bp_wl_cfg()
416 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); in hns_dsaf_sbm_bp_wl_cfg()
424 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); in hns_dsaf_sbm_bp_wl_cfg()
434 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); in hns_dsaf_sbm_bp_wl_cfg()
445 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); in hns_dsaf_sbm_bp_wl_cfg()
456 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); in hns_dsaf_sbm_bp_wl_cfg()
467 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); in hns_dsaf_sbm_bp_wl_cfg()
487 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); in hns_dsafv2_sbm_bp_wl_cfg()
495 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); in hns_dsafv2_sbm_bp_wl_cfg()
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Dhns_dsaf_ppe.c26 dsaf_write_dev(ppe_cb, PPEV2_RSS_KEY_REG + key_item * 0x4, in hns_ppe_set_rss_key()
52 dsaf_write_dev( in hns_ppe_set_indir_table()
138 dsaf_write_dev(ppe_cb, PPEV2_VLAN_STRIP_EN_REG, en); in hns_ppe_set_vlan_strip()
173 dsaf_write_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG, qid_mod); in hns_ppe_set_qid()
185 dsaf_write_dev(ppe_cb, PPE_CFG_XGE_MODE_REG, mode); in hns_ppe_set_port_mode()
266 dsaf_write_dev(ppe_cb, PPE_RINT_REG, clr_vlue); in hns_ppe_exc_irq_en()
269 dsaf_write_dev(ppe_cb, PPE_INTEN_REG, msk_vlue & vld_msk); in hns_ppe_exc_irq_en()
318 dsaf_write_dev(ppe_cb, PPE_CFG_PAUSE_IDLE_CNT_REG, 0); in hns_ppe_init_hw()
329 dsaf_write_dev(ppe_cb, PPE_CFG_MAX_FRAME_LEN_REG, in hns_ppe_init_hw()
Dhns_dsaf_xgmac.c128 dsaf_write_dev(mac_drv, XGMAC_MAC_TX_LF_RF_CONTROL_REG, val); in hns_xgmac_lf_rf_control_init()
189 dsaf_write_dev(drv, XGMAC_PMA_FEC_CONTROL_REG, origin); in hns_xgmac_pma_fec_enable()
198 dsaf_write_dev(drv, XGMAC_INT_STATUS_REG, clr_vlue); in hns_xgmac_exc_irq_en()
199 dsaf_write_dev(drv, XGMAC_INT_ENABLE_REG, msk_vlue); in hns_xgmac_exc_irq_en()
239 dsaf_write_dev(drv, XGMAC_MAC_CONTROL_REG, origin); in hns_xgmac_config_pad_and_crc()
255 dsaf_write_dev(drv, XGMAC_MAC_PAUSE_CTRL_REG, origin); in hns_xgmac_pausefrm_cfg()
265 dsaf_write_dev(drv, XGMAC_MAC_PAUSE_LOCAL_MAC_L_REG, low_val); in hns_xgmac_set_pausefrm_mac_addr()
266 dsaf_write_dev(drv, XGMAC_MAC_PAUSE_LOCAL_MAC_H_REG, high_val); in hns_xgmac_set_pausefrm_mac_addr()
283 dsaf_write_dev(drv, XGMAC_MAC_PAUSE_TIME_REG, enable); in hns_xgmac_set_tx_auto_pause_frames()
295 dsaf_write_dev(drv, XGMAC_MAC_MAX_PKT_SIZE_REG, newval); in hns_xgmac_config_max_frame_length()
Dhns_dsaf_gmac.c152 dsaf_write_dev(drv, GMAC_TRANSMIT_CONTROL_REG, tx_ctrl); in hns_gmac_config_pad_and_crc()
171 dsaf_write_dev(drv, GMAC_TX_LOOP_PKT_PRI_REG, tx_loop_pkt_pri); in hns_gmac_tx_loop_pkt_dis()
231 dsaf_write_dev(drv, GMAC_PAUSE_EN_REG, pause_en); in hns_gmac_pause_frm_cfg()
465 dsaf_write_dev(drv, GMAC_STATION_ADDR_LOW_2_REG, low_val); in hns_gmac_set_mac_addr()
466 dsaf_write_dev(drv, GMAC_STATION_ADDR_HIGH_2_REG, in hns_gmac_set_mac_addr()
Dhns_dsaf_main.h409 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul); in hns_dsaf_tbl_tcam_load_pul()
411 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul); in hns_dsaf_tbl_tcam_load_pul()
Dhns_dsaf_reg.h1022 #define dsaf_write_dev(a, reg, value) \ macro