| /drivers/media/platform/ti/vpe/ |
| D | vpdma_priv.h | 302 static inline int dtd_get_data_type(struct vpdma_dtd *dtd) in dtd_get_data_type() argument
304 return dtd->type_ctl_stride >> DTD_DATA_TYPE_SHFT; in dtd_get_data_type()
307 static inline bool dtd_get_notify(struct vpdma_dtd *dtd) in dtd_get_notify() argument
309 return (dtd->type_ctl_stride >> DTD_NOTIFY_SHFT) & DTD_NOTIFY_MASK; in dtd_get_notify()
312 static inline int dtd_get_field(struct vpdma_dtd *dtd) in dtd_get_field() argument
314 return (dtd->type_ctl_stride >> DTD_FIELD_SHFT) & DTD_FIELD_MASK; in dtd_get_field()
317 static inline bool dtd_get_1d(struct vpdma_dtd *dtd) in dtd_get_1d() argument
319 return (dtd->type_ctl_stride >> DTD_1D_SHFT) & DTD_1D_MASK; in dtd_get_1d()
322 static inline bool dtd_get_even_line_skip(struct vpdma_dtd *dtd) in dtd_get_even_line_skip() argument
324 return (dtd->type_ctl_stride >> DTD_EVEN_LINE_SKIP_SHFT) in dtd_get_even_line_skip()
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| D | vpdma.c | 553 static void dump_dtd(struct vpdma_dtd *dtd);
559 struct vpdma_dtd *dtd = list->buf.addr; in vpdma_update_dma_addr() local
563 dtd += idx; in vpdma_update_dma_addr()
566 dtd->start_addr = dma_addr; in vpdma_update_dma_addr()
575 dtd->desc_write_addr = dtd_desc_write_addr(write_desc_addr, in vpdma_update_dma_addr()
578 dtd->desc_write_addr = dtd_desc_write_addr(write_desc_addr, in vpdma_update_dma_addr()
583 dump_dtd(dtd); in vpdma_update_dma_addr()
748 static void dump_dtd(struct vpdma_dtd *dtd) in dump_dtd() argument
752 dir = dtd_get_dir(dtd); in dump_dtd()
753 chan = dtd_get_chan(dtd); in dump_dtd()
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| /drivers/gpu/drm/gma500/ |
| D | psb_intel_sdvo.c | 692 struct psb_intel_sdvo_dtd *dtd) in psb_intel_sdvo_set_timing() argument
694 return psb_intel_sdvo_set_value(psb_intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && in psb_intel_sdvo_set_timing()
695 psb_intel_sdvo_set_value(psb_intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); in psb_intel_sdvo_set_timing()
699 struct psb_intel_sdvo_dtd *dtd) in psb_intel_sdvo_set_input_timing() argument
702 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); in psb_intel_sdvo_set_input_timing()
706 struct psb_intel_sdvo_dtd *dtd) in psb_intel_sdvo_set_output_timing() argument
709 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); in psb_intel_sdvo_set_output_timing()
737 struct psb_intel_sdvo_dtd *dtd) in psb_intel_sdvo_get_preferred_input_timing() argument
739 BUILD_BUG_ON(sizeof(dtd->part1) != 8); in psb_intel_sdvo_get_preferred_input_timing()
740 BUILD_BUG_ON(sizeof(dtd->part2) != 8); in psb_intel_sdvo_get_preferred_input_timing()
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| /drivers/gpu/drm/i915/display/ |
| D | intel_sdvo.c | 749 struct intel_sdvo_dtd *dtd) in intel_sdvo_set_timing() argument
751 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && in intel_sdvo_set_timing()
752 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); in intel_sdvo_set_timing()
756 struct intel_sdvo_dtd *dtd) in intel_sdvo_get_timing() argument
758 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && in intel_sdvo_get_timing()
759 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); in intel_sdvo_get_timing()
763 struct intel_sdvo_dtd *dtd) in intel_sdvo_set_input_timing() argument
766 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); in intel_sdvo_set_input_timing()
770 struct intel_sdvo_dtd *dtd) in intel_sdvo_set_output_timing() argument
773 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); in intel_sdvo_set_output_timing()
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| D | intel_bios.c | 920 const struct generic_dtd_entry *dtd; in parse_generic_dtd() local
959 dtd = &generic_dtd->dtd[panel->vbt.panel_type]; in parse_generic_dtd()
965 panel_fixed_mode->hdisplay = dtd->hactive; in parse_generic_dtd()
967 panel_fixed_mode->hdisplay + dtd->hfront_porch; in parse_generic_dtd()
969 panel_fixed_mode->hsync_start + dtd->hsync; in parse_generic_dtd()
971 panel_fixed_mode->hdisplay + dtd->hblank; in parse_generic_dtd()
973 panel_fixed_mode->vdisplay = dtd->vactive; in parse_generic_dtd()
975 panel_fixed_mode->vdisplay + dtd->vfront_porch; in parse_generic_dtd()
977 panel_fixed_mode->vsync_start + dtd->vsync; in parse_generic_dtd()
979 panel_fixed_mode->vdisplay + dtd->vblank; in parse_generic_dtd()
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| D | intel_vbt_defs.h | 1059 struct generic_dtd_entry dtd[]; /* up to 24 DTD's */ member
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| /drivers/usb/gadget/udc/ |
| D | fsl_udc_core.c | 773 struct ep_td_struct *dtd; in fsl_build_dtd() local
779 dtd = dma_pool_alloc(udc_controller->td_pool, gfp_flags, dma); in fsl_build_dtd()
780 if (dtd == NULL) in fsl_build_dtd()
781 return dtd; in fsl_build_dtd()
783 dtd->td_dma = *dma; in fsl_build_dtd()
785 swap_temp = hc32_to_cpu(dtd->size_ioc_sts); in fsl_build_dtd()
787 dtd->size_ioc_sts = cpu_to_hc32(swap_temp); in fsl_build_dtd()
791 dtd->buff_ptr0 = cpu_to_hc32(swap_temp); in fsl_build_dtd()
792 dtd->buff_ptr1 = cpu_to_hc32(swap_temp + 0x1000); in fsl_build_dtd()
793 dtd->buff_ptr2 = cpu_to_hc32(swap_temp + 0x2000); in fsl_build_dtd()
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| D | mv_udc_core.c | 337 struct mv_dtd *dtd; in build_dtd() local
359 dtd = dma_pool_alloc(udc->dtd_pool, GFP_ATOMIC, dma); in build_dtd()
360 if (dtd == NULL) in build_dtd()
361 return dtd; in build_dtd()
363 dtd->td_dma = *dma; in build_dtd()
366 dtd->buff_ptr0 = cpu_to_le32(temp); in build_dtd()
368 dtd->buff_ptr1 = cpu_to_le32(temp + 0x1000); in build_dtd()
369 dtd->buff_ptr2 = cpu_to_le32(temp + 0x2000); in build_dtd()
370 dtd->buff_ptr3 = cpu_to_le32(temp + 0x3000); in build_dtd()
371 dtd->buff_ptr4 = cpu_to_le32(temp + 0x4000); in build_dtd()
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| D | mv_udc.h | 241 struct mv_dtd *dtd, *head, *tail; member
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| /drivers/pinctrl/tegra/ |
| D | pinctrl-tegra20.c | 2063 MUX_PG(dtd, RSVD1, SDIO2, VI, RSVD4, 0x14, 14, 0x84, 28, 0xa0, 24),
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