Searched refs:ecc_err_cnt_sel_addr (Results 1 – 4 of 4) sorted by relevance
/drivers/gpu/drm/amd/amdgpu/ |
D | umc_v6_1.c | 98 uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr; in umc_v6_1_clear_error_count_per_channel() local 102 ecc_err_cnt_sel_addr = in umc_v6_1_clear_error_count_per_channel() 110 ecc_err_cnt_sel_addr = in umc_v6_1_clear_error_count_per_channel() 119 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + in umc_v6_1_clear_error_count_per_channel() 124 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v6_1_clear_error_count_per_channel() 132 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + in umc_v6_1_clear_error_count_per_channel() 137 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v6_1_clear_error_count_per_channel() 173 uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr; in umc_v6_1_query_correctable_error_count() local 180 ecc_err_cnt_sel_addr = in umc_v6_1_query_correctable_error_count() 188 ecc_err_cnt_sel_addr = in umc_v6_1_query_correctable_error_count() [all …]
|
D | umc_v8_7.c | 184 uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr; in umc_v8_7_clear_error_count_per_channel() local 186 ecc_err_cnt_sel_addr = in umc_v8_7_clear_error_count_per_channel() 192 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + in umc_v8_7_clear_error_count_per_channel() 197 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v8_7_clear_error_count_per_channel() 205 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + in umc_v8_7_clear_error_count_per_channel() 210 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v8_7_clear_error_count_per_channel() 238 uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr; in umc_v8_7_query_correctable_error_count() local 244 ecc_err_cnt_sel_addr = in umc_v8_7_query_correctable_error_count() 252 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); in umc_v8_7_query_correctable_error_count() 255 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v8_7_query_correctable_error_count() [all …]
|
D | umc_v6_7.c | 267 uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr; in umc_v6_7_query_correctable_error_count() local 273 ecc_err_cnt_sel_addr = in umc_v6_7_query_correctable_error_count() 281 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); in umc_v6_7_query_correctable_error_count() 284 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v6_7_query_correctable_error_count() 294 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v6_7_query_correctable_error_count() 366 uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr; in umc_v6_7_reset_error_count_per_channel() local 370 ecc_err_cnt_sel_addr = in umc_v6_7_reset_error_count_per_channel() 378 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + in umc_v6_7_reset_error_count_per_channel() 383 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v6_7_reset_error_count_per_channel() 391 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + in umc_v6_7_reset_error_count_per_channel() [all …]
|
D | umc_v8_10.c | 298 uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr; in umc_v8_10_err_cnt_init_per_channel() local 303 ecc_err_cnt_sel_addr = in umc_v8_10_err_cnt_init_per_channel() 308 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); in umc_v8_10_err_cnt_init_per_channel() 313 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v8_10_err_cnt_init_per_channel()
|