Searched refs:edp (Results 1 – 16 of 16) sorted by relevance
| /drivers/phy/qualcomm/ |
| D | phy-qcom-edp.c | 87 void __iomem *edp; member
175 struct qcom_edp *edp = phy_get_drvdata(phy); in qcom_edp_phy_init() local
176 const struct qcom_edp_cfg *cfg = edp->cfg; in qcom_edp_phy_init()
180 ret = regulator_bulk_enable(ARRAY_SIZE(edp->supplies), edp->supplies); in qcom_edp_phy_init()
184 ret = clk_bulk_prepare_enable(ARRAY_SIZE(edp->clks), edp->clks); in qcom_edp_phy_init()
190 edp->edp + DP_PHY_PD_CTL); in qcom_edp_phy_init()
193 writel(0x17, edp->pll + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN); in qcom_edp_phy_init()
195 writel(DP_PHY_PD_CTL_PSR_PWRDN, edp->edp + DP_PHY_PD_CTL); in qcom_edp_phy_init()
201 edp->edp + DP_PHY_PD_CTL); in qcom_edp_phy_init()
208 writel(0xfc, edp->edp + DP_PHY_MODE); in qcom_edp_phy_init()
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| D | Makefile | 4 obj-$(CONFIG_PHY_QCOM_EDP) += phy-qcom-edp.o
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| /drivers/gpu/drm/gma500/ |
| D | intel_bios.c | 48 struct bdb_edp *edp; in parse_edp() local
53 edp = find_section(bdb, BDB_EDP); in parse_edp()
55 dev_priv->edp.bpp = 18; in parse_edp()
56 if (!edp) { in parse_edp()
57 if (dev_priv->edp.support) { in parse_edp()
59 dev_priv->edp.bpp); in parse_edp()
65 switch ((edp->color_depth >> (panel_type * 2)) & 3) { in parse_edp()
67 dev_priv->edp.bpp = 18; in parse_edp()
70 dev_priv->edp.bpp = 24; in parse_edp()
73 dev_priv->edp.bpp = 30; in parse_edp()
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| D | cdv_intel_dp.c | 526 (cdv_intel_dp_link_required(mode->clock, dev_priv->edp.bpp) in cdv_intel_dp_mode_valid()
908 bpp = dev_priv->edp.bpp; in cdv_intel_dp_mode_fixup()
1012 bpp = dev_priv->edp.bpp; in cdv_intel_dp_set_m_n()
1139 int edp = is_edp(intel_encoder); in cdv_intel_dp_prepare() local
1141 if (edp) { in cdv_intel_dp_prepare()
1149 if (edp) in cdv_intel_dp_prepare()
1156 int edp = is_edp(intel_encoder); in cdv_intel_dp_commit() local
1158 if (edp) in cdv_intel_dp_commit()
1162 if (edp) in cdv_intel_dp_commit()
1173 int edp = is_edp(intel_encoder); in cdv_intel_dp_dpms() local
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| D | psb_drv.h | 541 } edp; member
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| D | cdv_intel_display.c | 688 switch (dev_priv->edp.bpp) { in cdv_intel_crtc_mode_set()
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| /drivers/gpu/drm/i915/display/ |
| D | intel_dp_aux_backlight.c | 159 panel->backlight.edp.intel.sdr_uses_aux = in intel_dp_aux_supports_hdr_backlight()
181 if (!panel->backlight.edp.intel.sdr_uses_aux) { in intel_dp_aux_hdr_get_backlight()
224 if (panel->backlight.edp.intel.sdr_uses_aux) { in intel_dp_aux_hdr_set_backlight()
254 if (panel->backlight.edp.intel.sdr_uses_aux) { in intel_dp_aux_hdr_enable_backlight()
278 if (panel->backlight.edp.intel.sdr_uses_aux) in intel_dp_aux_hdr_disable_backlight()
301 dpcd_vs_pwm_str(panel->backlight.edp.intel.sdr_uses_aux)); in intel_dp_aux_hdr_setup_backlight()
303 if (!panel->backlight.edp.intel.sdr_uses_aux) { in intel_dp_aux_hdr_setup_backlight()
345 if (!panel->backlight.edp.vesa.info.aux_set) { in intel_dp_aux_vesa_set_backlight()
351 drm_edp_backlight_set_level(&intel_dp->aux, &panel->backlight.edp.vesa.info, level); in intel_dp_aux_vesa_set_backlight()
362 if (!panel->backlight.edp.vesa.info.aux_enable) { in intel_dp_aux_vesa_enable_backlight()
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| D | intel_bios.c | 1378 panel->vbt.edp.hobl = panel_bool(power->hobl, panel_type); in parse_power_conservation_features()
1389 const struct bdb_edp *edp; in parse_edp() local
1394 edp = bdb_find_section(i915, BDB_EDP); in parse_edp()
1395 if (!edp) in parse_edp()
1398 switch (panel_bits(edp->color_depth, panel_type, 2)) { in parse_edp()
1400 panel->vbt.edp.bpp = 18; in parse_edp()
1403 panel->vbt.edp.bpp = 24; in parse_edp()
1406 panel->vbt.edp.bpp = 30; in parse_edp()
1411 edp_pps = &edp->power_seqs[panel_type]; in parse_edp()
1412 edp_link_params = &edp->fast_link_params[panel_type]; in parse_edp()
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| D | intel_dp.c | 451 int edp_max_rate = connector->panel.vbt.edp.max_link_rate; in vbt_max_link_rate()
1407 intel_connector->panel.vbt.edp.bpp && in intel_dp_max_bpp()
1408 intel_connector->panel.vbt.edp.bpp < bpp) { in intel_dp_max_bpp()
1411 intel_connector->panel.vbt.edp.bpp); in intel_dp_max_bpp()
1412 bpp = intel_connector->panel.vbt.edp.bpp; in intel_dp_max_bpp()
2169 pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay; in intel_dp_drrs_compute_config()
3066 if (connector->panel.vbt.edp.bpp && pipe_bpp > connector->panel.vbt.edp.bpp) { in intel_edp_fixup_vbt_bpp()
3082 pipe_bpp, connector->panel.vbt.edp.bpp); in intel_edp_fixup_vbt_bpp()
3083 connector->panel.vbt.edp.bpp = pipe_bpp; in intel_edp_fixup_vbt_bpp()
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| D | intel_display_types.h | 326 } edp; member
399 } edp; member
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| D | intel_ddi_buf_trans.c | 1128 return connector->panel.vbt.edp.hobl && !intel_dp->hobl_failed; in use_edp_hobl()
1136 return connector->panel.vbt.edp.low_vswing; in use_edp_low_vswing()
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| D | intel_pps.c | 1357 *vbt = connector->panel.vbt.edp.pps; in pps_init_delays_vbt()
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| /drivers/gpu/drm/tegra/ |
| D | dp.h | 138 unsigned char edp; member
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| D | dp.c | 48 link->edp = 0; in drm_dp_link_reset()
201 link->edp = drm_dp_edp_revisions[value]; in drm_dp_link_probe()
236 if (link->edp >= 0x14) { in drm_dp_link_probe()
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| D | sor.c | 923 if (link->edp == 0) in tegra_sor_dp_link_configure()
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| /drivers/gpu/drm/panel/ |
| D | Makefile | 12 obj-$(CONFIG_DRM_PANEL_EDP) += panel-edp.o
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