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Searched refs:first_vid (Results 1 – 14 of 14) sorted by relevance

/drivers/net/ethernet/mellanox/mlx5/core/esw/acl/
Dhelper.c67 MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.first_vid); in esw_egress_acl_vlan_create()
68 MLX5_SET(fte_match_param, spec->match_value, outer_headers.first_vid, vlan_id); in esw_egress_acl_vlan_create()
112 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.first_vid); in esw_acl_egress_vlan_grp_create()
/drivers/net/ethernet/mellanox/mlx5/core/esw/
Dbridge_mcast.c106 outer_headers.first_vid); in mlx5_esw_bridge_mdb_flow_create()
107 MLX5_SET(fte_match_param, rule_spec->match_value, outer_headers.first_vid, in mlx5_esw_bridge_mdb_flow_create()
386 MLX5_SET_TO_ONES(fte_match_param, match, outer_headers.first_vid); in mlx5_esw_bridge_mcast_vlan_proto_fg_create()
608 MLX5_SET_TO_ONES(fte_match_param, rule_spec->match_criteria, outer_headers.first_vid); in mlx5_esw_bridge_mcast_vlan_flow_create()
609 MLX5_SET(fte_match_param, rule_spec->match_value, outer_headers.first_vid, vlan->vid); in mlx5_esw_bridge_mcast_vlan_flow_create()
Dbridge.c112 MLX5_SET_TO_ONES(fte_match_param, match, outer_headers.first_vid); in mlx5_esw_bridge_ingress_vlan_proto_fg_create()
269 MLX5_SET_TO_ONES(fte_match_param, match, outer_headers.first_vid); in mlx5_esw_bridge_egress_vlan_proto_fg_create()
623 outer_headers.first_vid); in mlx5_esw_bridge_ingress_flow_with_esw_create()
624 MLX5_SET(fte_match_param, rule_spec->match_value, outer_headers.first_vid, in mlx5_esw_bridge_ingress_flow_with_esw_create()
787 outer_headers.first_vid); in mlx5_esw_bridge_egress_flow_create()
788 MLX5_SET(fte_match_param, rule_spec->match_value, outer_headers.first_vid, in mlx5_esw_bridge_egress_flow_create()
/drivers/net/ethernet/mellanox/mlx5/core/
Den_fs.c262 outer_headers.first_vid); in __mlx5e_add_vlan_rule()
263 MLX5_SET(fte_match_param, spec->match_value, outer_headers.first_vid, in __mlx5e_add_vlan_rule()
272 outer_headers.first_vid); in __mlx5e_add_vlan_rule()
273 MLX5_SET(fte_match_param, spec->match_value, outer_headers.first_vid, in __mlx5e_add_vlan_rule()
1140 MLX5_SET_TO_ONES(fte_match_param, mc, outer_headers.first_vid); in __mlx5e_create_vlan_table_groups()
1152 MLX5_SET_TO_ONES(fte_match_param, mc, outer_headers.first_vid); in __mlx5e_create_vlan_table_groups()
Den_fs_ethtool.c334 MLX5E_FTE_SET(headers_c, first_vid, 0xfff); in set_cvlan()
335 MLX5E_FTE_SET(headers_v, first_vid, ntohs(vlan_tci)); in set_cvlan()
Den_tc.c2702 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid, in __parse_cls_flower()
2704 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, in __parse_cls_flower()
3128 OFFLOAD(FIRST_VID, 16, U16_MAX, vlan.h_vlan_TCI, 0, first_vid),
/drivers/net/ethernet/mellanox/mlx5/core/diag/
Dfs_tracepoint.c145 PRINT_MASKED_VAL_L2(u16, first_vid, first_vid, p, "%04x"); in print_lyr_2_4_hdrs()
/drivers/net/ethernet/mellanox/mlx5/core/steering/
Ddr_ste_v0.c721 DR_STE_SET_TAG(eth_l2_src_dst, bit_mask, first_vlan_id, mask, first_vid); in dr_ste_v0_build_eth_l2_src_dst_bit_mask()
766 DR_STE_SET_TAG(eth_l2_src_dst, tag, first_vlan_id, spec, first_vid); in dr_ste_v0_build_eth_l2_src_dst_tag()
887 DR_STE_SET_TAG(eth_l2_src, bit_mask, first_vlan_id, mask, first_vid); in dr_ste_v0_build_eth_l2_src_or_dst_bit_mask()
938 DR_STE_SET_TAG(eth_l2_src, tag, first_vlan_id, spec, first_vid); in dr_ste_v0_build_eth_l2_src_or_dst_tag()
1073 DR_STE_SET_TAG(eth_l2_tnl, bit_mask, first_vlan_id, mask, first_vid); in dr_ste_v0_build_eth_l2_tnl_bit_mask()
1103 DR_STE_SET_TAG(eth_l2_tnl, tag, first_vlan_id, spec, first_vid); in dr_ste_v0_build_eth_l2_tnl_tag()
Ddr_ste_v1.c1112 DR_STE_SET_TAG(eth_l2_src_dst_v1, bit_mask, first_vlan_id, mask, first_vid); in dr_ste_v1_build_eth_l2_src_dst_bit_mask()
1148 DR_STE_SET_TAG(eth_l2_src_dst_v1, tag, first_vlan_id, spec, first_vid); in dr_ste_v1_build_eth_l2_src_dst_tag()
1261 DR_STE_SET_TAG(eth_l2_src_v1, bit_mask, first_vlan_id, mask, first_vid); in dr_ste_v1_build_eth_l2_src_or_dst_bit_mask()
1311 DR_STE_SET_TAG(eth_l2_src_v1, tag, first_vlan_id, spec, first_vid); in dr_ste_v1_build_eth_l2_src_or_dst_tag()
1437 DR_STE_SET_TAG(eth_l2_tnl_v1, bit_mask, first_vlan_id, mask, first_vid); in dr_ste_v1_build_eth_l2_tnl_bit_mask()
1466 DR_STE_SET_TAG(eth_l2_tnl_v1, tag, first_vlan_id, spec, first_vid); in dr_ste_v1_build_eth_l2_tnl_tag()
Ddr_ste.c872 spec->first_vid = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, first_vid, clr); in dr_ste_copy_mask_spec()
Ddr_matcher.c55 #define DR_MASK_IS_L2_DST(_spec, _misc, _inner_outer) (_spec.first_vid || \
Ddr_types.h551 u32 first_vid:12; member
/drivers/infiniband/hw/mlx5/
Dfs.c247 first_vid, ntohs(ib_spec->eth.mask.vlan_tag)); in parse_flow_attr()
249 first_vid, ntohs(ib_spec->eth.val.vlan_tag)); in parse_flow_attr()
/drivers/vdpa/mlx5/net/
Dmlx5_vnet.c1607 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, first_vid); in mlx5_vdpa_add_mac_vlan_rules()
1611 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, vid); in mlx5_vdpa_add_mac_vlan_rules()