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Searched refs:group_idx (Results 1 – 10 of 10) sorted by relevance

/drivers/pinctrl/cirrus/
Dpinctrl-cs42l43.c103 unsigned int group_idx) in cs42l43_pin_get_group_name() argument
105 return cs42l43_pin_groups[group_idx].name; in cs42l43_pin_get_group_name()
109 unsigned int group_idx, in cs42l43_pin_get_group_pins() argument
113 *pins = cs42l43_pin_groups[group_idx].pins; in cs42l43_pin_get_group_pins()
114 *num_pins = cs42l43_pin_groups[group_idx].npins; in cs42l43_pin_get_group_pins()
186 unsigned int func_idx, unsigned int group_idx) in cs42l43_pin_set_mux() argument
192 cs42l43_pin_groups[group_idx].name, cs42l43_pin_funcs[func_idx]); in cs42l43_pin_set_mux()
198 val = 0x2 << (group_idx + CS42L43_MIC_SHUTTER_CFG_SHIFT); in cs42l43_pin_set_mux()
203 val = 0x2 << (group_idx + CS42L43_SPK_SHUTTER_CFG_SHIFT); in cs42l43_pin_set_mux()
207 mask = BIT(group_idx + CS42L43_GPIO1_FN_SEL_SHIFT); in cs42l43_pin_set_mux()
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Dpinctrl-lochnagar.c735 unsigned int group_idx) in lochnagar_get_group_name() argument
739 return priv->groups[group_idx].name; in lochnagar_get_group_name()
743 unsigned int group_idx, in lochnagar_get_group_pins() argument
749 *pins = priv->groups[group_idx].pins; in lochnagar_get_group_pins()
750 *num_pins = priv->groups[group_idx].npins; in lochnagar_get_group_pins()
910 unsigned int func_idx, unsigned int group_idx) in lochnagar_set_mux() argument
914 const struct lochnagar_group *group = &priv->groups[group_idx]; in lochnagar_set_mux()
988 unsigned int group_idx, bool master) in lochnagar_aif_set_master() argument
991 const struct lochnagar_group *group = &priv->groups[group_idx]; in lochnagar_aif_set_master()
1016 unsigned int group_idx, in lochnagar_conf_group_set() argument
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/drivers/net/wireless/intel/iwlegacy/
D3945.c1468 clip_pwrs = il->_3945.clip_groups[ch_info->group_idx].clip_powers; in il3945_hw_reg_set_new_power()
1574 ref_temp = (s16) eeprom->groups[ch_info->group_idx].temperature; in il3945_hw_reg_comp_txpower_temp()
1599 il->_3945.clip_groups[ch_info->group_idx].clip_powers; in il3945_hw_reg_comp_txpower_temp()
1893 u16 group_idx = 0; /* based on factory calib frequencies */ in il3945_hw_reg_get_ch_grp_idx() local
1901 group_idx = group; in il3945_hw_reg_get_ch_grp_idx()
1907 group_idx = 4; in il3945_hw_reg_get_ch_grp_idx()
1909 group_idx = 0; /* 2.4 GHz, group 0 */ in il3945_hw_reg_get_ch_grp_idx()
1911 D_POWER("Chnl %d mapped to grp %d\n", ch_info->channel, group_idx); in il3945_hw_reg_get_ch_grp_idx()
1912 return group_idx; in il3945_hw_reg_get_ch_grp_idx()
2084 ch_info->group_idx = il3945_hw_reg_get_ch_grp_idx(il, ch_info); in il3945_txpower_set_from_eeprom()
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Dcommon.h484 u8 group_idx; /* 0-4, maps channel to group1/2/3/4/5 */ member
/drivers/media/radio/wl128x/
Dfmdrv_common.c704 unsigned long group_idx, flags; in fm_irq_handle_rdsdata_getcmd_resp() local
762 group_idx = (rds_fmt.data.groupgeneral.blk_b[0] >> 3); in fm_irq_handle_rdsdata_getcmd_resp()
763 fmdbg("(fmdrv):Group:%ld%s\n", group_idx/2, in fm_irq_handle_rdsdata_getcmd_resp()
764 (group_idx % 2) ? "B" : "A"); in fm_irq_handle_rdsdata_getcmd_resp()
766 group_idx = 1 << (rds_fmt.data.groupgeneral.blk_b[0] >> 3); in fm_irq_handle_rdsdata_getcmd_resp()
767 if (group_idx == FM_RDS_GROUP_TYPE_MASK_0A) { in fm_irq_handle_rdsdata_getcmd_resp()
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_optc.c107 int group_idx, in optc2_set_gsl_source_select() argument
112 switch (group_idx) { in optc2_set_gsl_source_select()
Ddcn20_optc.h93 int group_idx,
Ddcn20_hwseq.c103 int group_idx; in dcn20_setup_gsl_group_as_lock() local
114 group_idx = find_free_gsl_group(dc); in dcn20_setup_gsl_group_as_lock()
115 ASSERT(group_idx != 0); in dcn20_setup_gsl_group_as_lock()
116 pipe_ctx->stream_res.gsl_group = group_idx; in dcn20_setup_gsl_group_as_lock()
119 switch (group_idx) { in dcn20_setup_gsl_group_as_lock()
138 group_idx = pipe_ctx->stream_res.gsl_group; in dcn20_setup_gsl_group_as_lock()
139 if (group_idx == 0) in dcn20_setup_gsl_group_as_lock()
145 switch (group_idx) { in dcn20_setup_gsl_group_as_lock()
173 pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0); in dcn20_setup_gsl_group_as_lock()
/drivers/perf/
Dcxl_pmu.c154 u8 group_idx; in cxl_pmu_parse_caps() local
168 group_idx = FIELD_GET(CXL_PMU_COUNTER_CFG_EVENT_GRP_ID_IDX_MSK, val); in cxl_pmu_parse_caps()
170 eval = readq(base + CXL_PMU_EVENT_CAP_REG(group_idx)); in cxl_pmu_parse_caps()
186 set_bit(group_idx, &fixed_counter_event_cap_bm); in cxl_pmu_parse_caps()
/drivers/gpu/drm/amd/display/dc/inc/hw/
Dtiming_generator.h315 int group_idx,