| /drivers/gpu/drm/amd/display/dc/dcn201/ |
| D | dcn201_dpp.c | 208 if (in_taps->h_taps == 0) { in dpp201_get_optimal_number_of_taps()
210 scl_data->taps.h_taps = 8; in dpp201_get_optimal_number_of_taps()
212 scl_data->taps.h_taps = 4; in dpp201_get_optimal_number_of_taps()
214 scl_data->taps.h_taps = in_taps->h_taps; in dpp201_get_optimal_number_of_taps()
242 scl_data->taps.h_taps = 1; in dpp201_get_optimal_number_of_taps()
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| /drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_transform.c | 122 if (data->taps.h_taps + data->taps.v_taps <= 2) { in setup_scaling_configuration()
132 SCL_H_NUM_OF_TAPS, data->taps.h_taps - 1, in setup_scaling_configuration()
156 if (data->taps.h_taps + data->taps.v_taps <= 2) { in dce60_setup_scaling_configuration()
165 SCL_H_NUM_OF_TAPS, data->taps.h_taps - 1, in dce60_setup_scaling_configuration()
294 dc_fixpt_from_int(data->taps.h_taps + 1)), in calculate_inits()
440 coeffs_h = get_filter_coeffs_16p(data->taps.h_taps, data->ratios.horz); in dce_transform_set_scaler()
464 data->taps.h_taps, in dce_transform_set_scaler()
469 data->taps.h_taps, in dce_transform_set_scaler()
525 coeffs_h = get_filter_coeffs_16p(data->taps.h_taps, data->ratios.horz); in dce60_transform_set_scaler()
549 data->taps.h_taps, in dce60_transform_set_scaler()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_dpp.c | 154 if (in_taps->h_taps == 0) in dpp1_get_optimal_number_of_taps()
155 scl_data->taps.h_taps = 4; in dpp1_get_optimal_number_of_taps()
157 scl_data->taps.h_taps = in_taps->h_taps; in dpp1_get_optimal_number_of_taps()
176 scl_data->taps.h_taps = 1; in dpp1_get_optimal_number_of_taps()
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| D | dcn10_dpp_dscl.c | 295 h_2tap_hardcode_coef_en = scl_data->taps.h_taps < 3 in dpp1_dscl_set_scl_filter()
297 && (scl_data->taps.h_taps > 1 && scl_data->taps.h_taps_c > 1); in dpp1_dscl_set_scl_filter()
317 scl_data->taps.h_taps, scl_data->ratios.horz); in dpp1_dscl_set_scl_filter()
338 dpp, scl_data->taps.h_taps, in dpp1_dscl_set_scl_filter()
690 SCL_H_NUM_TAPS, scl_data->taps.h_taps - 1, in dpp1_dscl_set_scaler_manual_scale()
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| /drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_transform_v.c | 165 set_reg_field_value(value, data->taps.h_taps - 1, in setup_scaling_configuration()
176 if (data->taps.h_taps + data->taps.v_taps > 2) { in setup_scaling_configuration()
560 coeffs_h = get_filter_coeffs_64p(data->taps.h_taps, data->ratios.horz); in dce110_xfmv_set_scaler()
583 data->taps.h_taps, in dce110_xfmv_set_scaler()
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| /drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_debug.c | 85 plane_state->scaling_quality.h_taps, in pre_surface_trace()
289 update->scaling_info->scaling_quality.h_taps, in update_surface_trace()
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| D | dc_resource.c | 1340 data->taps.h_taps, in calculate_inits_and_viewports()
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| /drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_dpp.c | 405 if (in_taps->h_taps == 0) { in dpp3_get_optimal_number_of_taps()
407 scl_data->taps.h_taps = min(2 * dc_fixpt_ceil(scl_data->ratios.horz), 8); in dpp3_get_optimal_number_of_taps()
409 scl_data->taps.h_taps = 4; in dpp3_get_optimal_number_of_taps()
411 scl_data->taps.h_taps = in_taps->h_taps; in dpp3_get_optimal_number_of_taps()
474 scl_data->taps.h_taps = 1; in dpp3_get_optimal_number_of_taps()
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| /drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| D | dce_calcs.c | 382 data->h_taps[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1); in calculate_bandwidth()
383 data->h_taps[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1); in calculate_bandwidth()
436 data->h_taps[i] = bw_int_to_fixed(1); in calculate_bandwidth()
526 if (bw_mtn(data->hsr[i], data->h_taps[i])) { in calculate_bandwidth()
530 …sr[i], bw_int_to_fixed(1)) && bw_leq(data->hsr[i], bw_ceil2(bw_div(data->h_taps[i], bw_int_to_fixe… in calculate_bandwidth()
1258 …data->scaler_limits_factor = bw_max3(bw_int_to_fixed(1), bw_ceil2(bw_div(data->h_taps[i], bw_int_t… in calculate_bandwidth()
1706 …data->scaler_limits_factor = bw_max3(bw_int_to_fixed(1), bw_ceil2(bw_div(data->h_taps[i], bw_int_t… in calculate_bandwidth()
2830 data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps); in populate_initial_data()
2886 …data->h_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.… in populate_initial_data()
2933 data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps); in populate_initial_data()
[all …]
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| D | calcs_logger.h | 430 DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] h_taps[%d]:%d", i, bw_fixed_to_int(data->h_taps[i])); in print_bw_calcs_data()
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| D | dcn_calcs.c | 398 input->scale_taps.htaps = pipe->plane_res.scl_data.taps.h_taps; in pipe_ctx_to_e2e_pipe_params()
1012 v->override_hta_ps[input_idx] = pipe->plane_res.scl_data.taps.h_taps; in dcn_validate_bandwidth()
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_dwb_scl.c | 725 uint32_t h_taps_luma = num_taps.h_taps; in dwb_program_horz_scalar()
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| /drivers/gpu/drm/amd/display/dc/ |
| D | dc_hw_types.h | 674 uint32_t h_taps; member
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| D | dce_calcs.h | 396 struct bw_fixed h_taps[maximum_number_of_surfaces]; member
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| /drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| D | dcn30_fpu.c | 295 dout_wb.wb_htaps_luma = wb_info->dwb_params.scaler_taps.h_taps; in dcn30_fpu_populate_dml_writeback_from_context()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| D | dcn20_fpu.c | 1672 pipes[pipe_cnt].pipe.scale_taps.htaps = scl->taps.h_taps; in dcn20_populate_dml_pipes_from_context()
2508 dout_wb.wb_htaps_luma = wb_info->dwb_params.scaler_taps.h_taps; in dcn201_populate_dml_writeback_from_context_fpu()
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