| /drivers/gpu/drm/panel/ |
| D | panel-simple.c | 209 m->hdisplay, m->vdisplay, in panel_simple_get_display_modes()
716 .hdisplay = 1280,
742 .hdisplay = 480,
766 .hdisplay = 800,
876 .hdisplay = 1024,
901 .hdisplay = 1366,
924 .hdisplay = 1366,
984 .hdisplay = 1280,
1008 .hdisplay = 800,
1086 .hdisplay = 1366,
[all …]
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| D | panel-edp.c | 288 m->hdisplay, m->vdisplay, in panel_edp_get_display_modes()
990 .hdisplay = 1366,
1018 .hdisplay = 1920,
1045 .hdisplay = 1920,
1072 .hdisplay = 1366,
1094 .hdisplay = 1920,
1122 .hdisplay = 1280,
1133 .hdisplay = 1280,
1163 .hdisplay = 2160,
1175 .hdisplay = 2160,
[all …]
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| D | panel-arm-versatile.c | 138 .hdisplay = 320,
161 .hdisplay = 640,
183 .hdisplay = 176,
206 .hdisplay = 240,
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| D | panel-tpo-tpg110.c | 106 .hdisplay = 800,
122 .hdisplay = 640,
138 .hdisplay = 480,
154 .hdisplay = 480,
170 .hdisplay = 400,
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| D | panel-sharp-lq101r1sx01.c | 133 err = mipi_dsi_dcs_set_column_address(left, 0, mode->hdisplay / 2 - 1); in sharp_setup_symmetrical_split()
145 err = mipi_dsi_dcs_set_column_address(right, mode->hdisplay / 2, in sharp_setup_symmetrical_split()
146 mode->hdisplay - 1); in sharp_setup_symmetrical_split()
264 .hdisplay = 2560,
282 default_mode.hdisplay, default_mode.vdisplay, in sharp_panel_get_modes()
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| /drivers/gpu/drm/tve200/ |
| D | tve200_display.c | 82 if (!(mode->hdisplay == 352 && mode->vdisplay == 240) && /* SIF(525) */ in tve200_display_check()
83 !(mode->hdisplay == 352 && mode->vdisplay == 288) && /* CIF(625) */ in tve200_display_check()
84 !(mode->hdisplay == 640 && mode->vdisplay == 480) && /* VGA */ in tve200_display_check()
85 !(mode->hdisplay == 720 && mode->vdisplay == 480) && /* D1 */ in tve200_display_check()
86 !(mode->hdisplay == 720 && mode->vdisplay == 576)) { /* D1 */ in tve200_display_check()
88 mode->hdisplay, mode->vdisplay); in tve200_display_check()
105 if (fb->pitches[0] != mode->hdisplay * fb->format->cpp[0]) { in tve200_display_check()
171 if ((mode->hdisplay == 352 && mode->vdisplay == 240) || /* SIF(525) */ in tve200_display_enable()
172 (mode->hdisplay == 352 && mode->vdisplay == 288)) { /* CIF(625) */ in tve200_display_enable()
175 } else if (mode->hdisplay == 640 && mode->vdisplay == 480) { in tve200_display_enable()
[all …]
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| /drivers/gpu/drm/ |
| D | drm_modes.c | 455 mode->hdisplay = hactive; in fill_analog_mode()
456 mode->hsync_start = mode->hdisplay + hfp; in fill_analog_mode()
547 unsigned int hdisplay, in drm_analog_tv_mode() argument
584 pixel_clock_hz, hdisplay, vdisplay, interlace); in drm_analog_tv_mode()
620 struct drm_display_mode *drm_cvt_mode(struct drm_device *dev, int hdisplay, in drm_cvt_mode() argument
641 if (!hdisplay || !vdisplay) in drm_cvt_mode()
662 hdisplay_rnd = hdisplay - (hdisplay % CVT_H_GRANULARITY); in drm_cvt_mode()
671 drm_mode->hdisplay = hdisplay_rnd + 2 * hmargin; in drm_cvt_mode()
693 if (!(vdisplay % 3) && ((vdisplay * 4 / 3) == hdisplay)) in drm_cvt_mode()
695 else if (!(vdisplay % 9) && ((vdisplay * 16 / 9) == hdisplay)) in drm_cvt_mode()
[all …]
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| /drivers/gpu/drm/nouveau/dispnv04/ |
| D | tvnv17.c | 208 for (tv_mode = nv17_tv_modes; tv_mode->hdisplay; tv_mode++) { in nv17_tv_get_ld_modes()
222 if (mode->hdisplay == tv_norm->tv_enc_mode.hdisplay && in nv17_tv_get_ld_modes()
240 int hdisplay; in nv17_tv_get_hd_modes() member
256 if (modes[i].hdisplay > output_mode->hdisplay || in nv17_tv_get_hd_modes()
260 if (modes[i].hdisplay == output_mode->hdisplay && in nv17_tv_get_hd_modes()
268 mode = drm_cvt_mode(encoder->dev, modes[i].hdisplay, in nv17_tv_get_hd_modes()
277 if (output_mode->hdisplay <= 720 in nv17_tv_get_hd_modes()
278 || output_mode->hdisplay >= 1920) { in nv17_tv_get_hd_modes()
280 mode->hsync_start = (mode->hdisplay + (mode->htotal in nv17_tv_get_hd_modes()
281 - mode->hdisplay) * 9 / 10) & ~7; in nv17_tv_get_hd_modes()
[all …]
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| D | dfp.c | 192 mode->hdisplay > nv_connector->native_mode->hdisplay || in nv04_dfp_mode_fixup()
301 regp->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1; in nv04_dfp_mode_set()
304 (output_mode->hsync_start - output_mode->hdisplay) >= in nv04_dfp_mode_set()
306 regp->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay; in nv04_dfp_mode_set()
312 regp->fp_horiz_regs[FP_VALID_END] = output_mode->hdisplay - 1; in nv04_dfp_mode_set()
335 else if (adjusted_mode->hdisplay == output_mode->hdisplay && in nv04_dfp_mode_set()
375 mode_ratio = (1 << 12) * adjusted_mode->hdisplay / adjusted_mode->vdisplay; in nv04_dfp_mode_set()
376 panel_ratio = (1 << 12) * output_mode->hdisplay / output_mode->vdisplay; in nv04_dfp_mode_set()
394 diff = output_mode->hdisplay - in nv04_dfp_mode_set()
405 scale = (1 << 12) * adjusted_mode->hdisplay / output_mode->hdisplay; in nv04_dfp_mode_set()
[all …]
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| D | tvmodesnv17.c | 324 uint64_t rs[] = {mode->hdisplay * id3, in tv_setup_filter()
327 do_div(rs[0], overscan * tv_norm->tv_enc_mode.hdisplay); in tv_setup_filter()
558 hmargin = (output_mode->hdisplay - crtc_mode->hdisplay) / 2; in nv17_ctv_update_rescaler()
561 hmargin = interpolate(0, min(hmargin, output_mode->hdisplay/20), in nv17_ctv_update_rescaler()
566 hratio = crtc_mode->hdisplay * 0x800 / in nv17_ctv_update_rescaler()
567 (output_mode->hdisplay - 2*hmargin); in nv17_ctv_update_rescaler()
572 regs->fp_horiz_regs[FP_VALID_END] = output_mode->hdisplay - hmargin - 1; in nv17_ctv_update_rescaler()
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_encoders.c | 169 unsigned int hblank = native_mode->htotal - native_mode->hdisplay; in amdgpu_panel_mode_fixup()
171 unsigned int hover = native_mode->hsync_start - native_mode->hdisplay; in amdgpu_panel_mode_fixup()
179 adjusted_mode->hdisplay = native_mode->hdisplay; in amdgpu_panel_mode_fixup()
182 adjusted_mode->htotal = native_mode->hdisplay + hblank; in amdgpu_panel_mode_fixup()
183 adjusted_mode->hsync_start = native_mode->hdisplay + hover; in amdgpu_panel_mode_fixup()
192 adjusted_mode->crtc_hdisplay = native_mode->hdisplay; in amdgpu_panel_mode_fixup()
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| D | amdgpu_connectors.c | 389 if (native_mode->hdisplay != 0 && in amdgpu_connector_lcd_native_mode()
400 } else if (native_mode->hdisplay != 0 && in amdgpu_connector_lcd_native_mode()
409 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false); in amdgpu_connector_lcd_native_mode()
457 if (common_modes[i].w > native_mode->hdisplay || in amdgpu_connector_add_common_modes()
459 (common_modes[i].w == native_mode->hdisplay && in amdgpu_connector_add_common_modes()
636 if (mode->hdisplay != native_mode->hdisplay || in amdgpu_connector_fixup_lcd_native_mode()
645 if (mode->hdisplay == native_mode->hdisplay && in amdgpu_connector_fixup_lcd_native_mode()
703 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) in amdgpu_connector_lvds_mode_valid()
713 if ((mode->hdisplay > native_mode->hdisplay) || in amdgpu_connector_lvds_mode_valid()
719 if ((mode->hdisplay != native_mode->hdisplay) || in amdgpu_connector_lvds_mode_valid()
[all …]
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| /drivers/gpu/drm/radeon/ |
| D | radeon_encoders.c | 326 unsigned int hblank = native_mode->htotal - native_mode->hdisplay; in radeon_panel_mode_fixup()
328 unsigned int hover = native_mode->hsync_start - native_mode->hdisplay; in radeon_panel_mode_fixup()
337 adjusted_mode->hdisplay = native_mode->hdisplay; in radeon_panel_mode_fixup()
341 adjusted_mode->htotal = native_mode->hdisplay + hblank; in radeon_panel_mode_fixup()
342 adjusted_mode->hsync_start = native_mode->hdisplay + hover; in radeon_panel_mode_fixup()
352 adjusted_mode->crtc_hdisplay = native_mode->hdisplay; in radeon_panel_mode_fixup()
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| /drivers/gpu/drm/gma500/ |
| D | oaktrail_lvds.c | 137 (mode->hdisplay != adjusted_mode->crtc_hdisplay)) { in oaktrail_lvds_mode_set()
139 (mode->hdisplay * adjusted_mode->crtc_vdisplay)) in oaktrail_lvds_mode_set()
142 mode->vdisplay) > (mode->hdisplay * in oaktrail_lvds_mode_set()
231 mode->hdisplay = (ti->hactive_hi << 8) | ti->hactive_lo; in oaktrail_lvds_get_configuration_mode()
233 mode->hsync_start = mode->hdisplay + \ in oaktrail_lvds_get_configuration_mode()
239 mode->htotal = mode->hdisplay + ((ti->hblank_hi << 8) | \ in oaktrail_lvds_get_configuration_mode()
251 pr_info("hdisplay is %d\n", mode->hdisplay); in oaktrail_lvds_get_configuration_mode()
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| D | cdv_intel_lvds.c | 172 if (mode->hdisplay > fixed_mode->hdisplay) in cdv_intel_lvds_mode_valid()
207 adjusted_mode->hdisplay = panel_fixed_mode->hdisplay; in cdv_intel_lvds_mode_fixup()
280 if (mode->hdisplay != adjusted_mode->hdisplay || in cdv_intel_lvds_mode_set()
372 if (crtc->saved_mode.hdisplay != 0 && in cdv_intel_lvds_set_property()
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| /drivers/gpu/drm/i915/display/ |
| D | intel_tv.c | 1010 mode->hdisplay = in intel_tv_mode_to_mode()
1012 mode->hsync_start = mode->hdisplay + in intel_tv_mode_to_mode()
1053 mode->hdisplay, mode->vdisplay, in intel_tv_mode_to_mode()
1059 int hdisplay, int left_margin, in intel_tv_scale_mode_horiz() argument
1062 int hsync_start = mode->hsync_start - mode->hdisplay + right_margin; in intel_tv_scale_mode_horiz()
1063 int hsync_end = mode->hsync_end - mode->hdisplay + right_margin; in intel_tv_scale_mode_horiz()
1064 int new_htotal = mode->htotal * hdisplay / in intel_tv_scale_mode_horiz()
1065 (mode->hdisplay - left_margin - right_margin); in intel_tv_scale_mode_horiz()
1069 mode->hdisplay = hdisplay; in intel_tv_scale_mode_horiz()
1070 mode->hsync_start = hdisplay + hsync_start * new_htotal / mode->htotal; in intel_tv_scale_mode_horiz()
[all …]
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| D | dvo_ns2501.c | 532 mode->hdisplay, mode->htotal, mode->vdisplay, mode->vtotal); in ns2501_mode_valid()
540 if ((mode->hdisplay == 640 && mode->vdisplay == 480 && mode->clock == 25175) || in ns2501_mode_valid()
541 (mode->hdisplay == 800 && mode->vdisplay == 600 && mode->clock == 40000) || in ns2501_mode_valid()
542 (mode->hdisplay == 1024 && mode->vdisplay == 768 && mode->clock == 65000)) { in ns2501_mode_valid()
559 mode->hdisplay, mode->htotal, mode->vdisplay, mode->vtotal); in ns2501_mode_set()
591 if (mode->hdisplay == 640 && mode->vdisplay == 480) in ns2501_mode_set()
593 else if (mode->hdisplay == 800 && mode->vdisplay == 600) in ns2501_mode_set()
595 else if (mode->hdisplay == 1024 && mode->vdisplay == 768) in ns2501_mode_set()
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| /drivers/gpu/drm/gud/ |
| D | gud_internal.h | 136 dst->hdisplay = cpu_to_le16(src->hdisplay); in gud_from_display_mode()
154 dst->hdisplay = le16_to_cpu(src->hdisplay); in gud_to_display_mode()
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| /drivers/gpu/drm/mgag200/ |
| D | mgag200_mode.c | 205 unsigned int hdisplay, hsyncstart, hsyncend, htotal; in mgag200_set_mode_regs() local
209 hdisplay = mode->hdisplay / 8 - 1; in mgag200_set_mode_regs()
236 ((hdisplay & 0x100) >> 7) | in mgag200_set_mode_regs()
251 WREG_CRT(1, hdisplay); in mgag200_set_mode_regs()
252 WREG_CRT(2, hdisplay); in mgag200_set_mode_regs()
555 if (mode->hdisplay > info->max_hdisplay) in mgag200_crtc_helper_mode_valid()
560 if ((mode->hdisplay % 8) != 0 || (mode->hsync_start % 8) != 0 || in mgag200_crtc_helper_mode_valid()
769 active_area = mode->hdisplay * mode->vdisplay; in mgag200_calculate_mode_bandwidth()
791 fbsize = mode->hdisplay * mode->vdisplay * max_bpp; in mgag200_mode_config_mode_valid()
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| /drivers/gpu/drm/bridge/ |
| D | ti-dlpc3433.c | 136 buf[4] = mode->hdisplay & 0xff; in dlpc_atomic_enable()
137 buf[5] = (mode->hdisplay & 0xff00) >> 8; in dlpc_atomic_enable()
143 buf[4] = mode->hdisplay & 0xff; in dlpc_atomic_enable()
144 buf[5] = (mode->hdisplay & 0xff00) >> 8; in dlpc_atomic_enable()
150 buf[0] = mode->hdisplay & 0xff; in dlpc_atomic_enable()
151 buf[1] = (mode->hdisplay & 0xff00) >> 8; in dlpc_atomic_enable()
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| /drivers/gpu/drm/imx/lcdc/ |
| D | imx-lcdc.c | 160 framesize = FIELD_PREP(IMX21LCDC_LSR_XMAX, crtc->mode.hdisplay >> 4) | in imx_lcdc_update_hw_registers()
165 lhcr = FIELD_PREP(IMX21LCDC_LHCR_HFPORCH, crtc->mode.hsync_start - crtc->mode.hdisplay - 1) | in imx_lcdc_update_hw_registers()
281 if (mode->hdisplay < LCDC_MIN_XRES || mode->hdisplay > LCDC_MAX_XRES || in imx_lcdc_pipe_check()
283 mode->hdisplay % 0x10) { /* must be multiple of 16 */ in imx_lcdc_pipe_check()
285 mode->hdisplay, mode->vdisplay); in imx_lcdc_pipe_check()
290 old_mode->hdisplay != mode->hdisplay || in imx_lcdc_pipe_check()
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| /drivers/gpu/drm/pl111/ |
| D | pl111_display.c | 64 bw = bw * mode->hdisplay * mode->vdisplay * cpp; in pl111_mode_valid()
73 mode->hdisplay, mode->vdisplay, in pl111_mode_valid()
79 mode->hdisplay, mode->vdisplay, in pl111_mode_valid()
93 if (mode->hdisplay % 16) in pl111_display_check()
106 if (fb->pitches[0] != mode->hdisplay * fb->format->cpp[0]) in pl111_display_check()
147 ppl = (mode->hdisplay / 16) - 1; in pl111_display_enable()
149 hfp = mode->hsync_start - mode->hdisplay - 1; in pl111_display_enable()
157 cpl = mode->hdisplay - 1; in pl111_display_enable()
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| /drivers/gpu/drm/tilcdc/ |
| D | tilcdc_plane.c | 51 if (crtc_state->mode.hdisplay != new_state->crtc_w || in tilcdc_plane_atomic_check()
55 crtc_state->mode.hdisplay, crtc_state->mode.vdisplay, in tilcdc_plane_atomic_check()
60 pitch = crtc_state->mode.hdisplay * in tilcdc_plane_atomic_check()
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| /drivers/gpu/drm/exynos/ |
| D | exynos_hdmi.c | 936 mode->hdisplay, mode->vdisplay, in hdmi_mode_valid()
1032 m->hdisplay, m->vdisplay, in hdmi_mode_fixup()
1215 hdmi_reg_writev(hdata, HDMI_H_BLANK_0, 2, m->htotal - m->hdisplay); in hdmi_v13_mode_apply()
1225 val = (m->hsync_start - m->hdisplay - 2); in hdmi_v13_mode_apply()
1226 val |= ((m->hsync_end - m->hdisplay - 2) << 10); in hdmi_v13_mode_apply()
1255 val = ((m->htotal / 2) + (m->hsync_start - m->hdisplay)); in hdmi_v13_mode_apply()
1257 (m->hsync_start - m->hdisplay)) << 12; in hdmi_v13_mode_apply()
1284 hdmi_reg_writev(hdata, HDMI_TG_HACT_ST_L, 2, m->htotal - m->hdisplay); in hdmi_v13_mode_apply()
1285 hdmi_reg_writev(hdata, HDMI_TG_HACT_SZ_L, 2, m->hdisplay); in hdmi_v13_mode_apply()
1302 (m->hdisplay == 1280 || m->hdisplay == 1024 || m->hdisplay == 1366)) in hdmi_v14_mode_apply()
[all …]
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| /drivers/gpu/drm/virtio/ |
| D | virtgpu_display.c | 93 crtc->mode.hdisplay, in virtio_gpu_crtc_mode_set_nofb()
205 if (mode->hdisplay == XRES_DEF && mode->vdisplay == YRES_DEF) in virtio_gpu_conn_mode_valid()
207 if (mode->hdisplay <= width && mode->hdisplay >= width - 16 && in virtio_gpu_conn_mode_valid()
211 DRM_DEBUG("del mode: %dx%d\n", mode->hdisplay, mode->vdisplay); in virtio_gpu_conn_mode_valid()
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