| /drivers/gpu/drm/i915/display/ |
| D | intel_ddi_buf_trans.c | 19 { .hsw = { 0x00FFFFFF, 0x0006000E, 0x0 } },
20 { .hsw = { 0x00D75FFF, 0x0005000A, 0x0 } },
21 { .hsw = { 0x00C30FFF, 0x00040006, 0x0 } },
22 { .hsw = { 0x80AAAFFF, 0x000B0000, 0x0 } },
23 { .hsw = { 0x00FFFFFF, 0x0005000A, 0x0 } },
24 { .hsw = { 0x00D75FFF, 0x000C0004, 0x0 } },
25 { .hsw = { 0x80C30FFF, 0x000B0000, 0x0 } },
26 { .hsw = { 0x00FFFFFF, 0x00040006, 0x0 } },
27 { .hsw = { 0x80D75FFF, 0x000B0000, 0x0 } },
36 { .hsw = { 0x00FFFFFF, 0x0007000E, 0x0 } },
[all …]
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| D | intel_display_power_map.c | 111 .hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
145 .hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
362 .hsw.idx = SKL_PW_CTL_IDX_PW_1,
376 .hsw.idx = SKL_PW_CTL_IDX_MISC_IO,
390 .hsw.idx = SKL_PW_CTL_IDX_PW_2,
399 I915_PW("DDI_IO_A_E", &skl_pwdoms_ddi_io_a_e, .hsw.idx = SKL_PW_CTL_IDX_DDI_A_E),
400 I915_PW("DDI_IO_B", &skl_pwdoms_ddi_io_b, .hsw.idx = SKL_PW_CTL_IDX_DDI_B),
401 I915_PW("DDI_IO_C", &skl_pwdoms_ddi_io_c, .hsw.idx = SKL_PW_CTL_IDX_DDI_C),
402 I915_PW("DDI_IO_D", &skl_pwdoms_ddi_io_d, .hsw.idx = SKL_PW_CTL_IDX_DDI_D),
470 .hsw.idx = SKL_PW_CTL_IDX_PW_2,
[all …]
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| D | intel_display_power_well.c | 210 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; in icl_aux_pw_to_ch()
264 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; in hsw_wait_for_power_well_enable()
308 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; in hsw_wait_for_power_well_disable()
346 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; in hsw_power_well_enable()
390 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; in hsw_power_well_disable()
417 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; in icl_combo_phy_aux_power_well_enable()
443 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; in icl_combo_phy_aux_power_well_disable()
523 HSW_PWR_WELL_CTL_REQ(i915_power_well_instance(power_well)->hsw.idx)); in icl_tc_phy_aux_power_well_enable()
539 tc_port = TGL_AUX_PW_TO_TC_PORT(i915_power_well_instance(power_well)->hsw.idx); in icl_tc_phy_aux_power_well_enable()
588 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; in hsw_power_well_enabled()
[all …]
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| D | intel_ddi_buf_trans.h | 55 struct hsw_ddi_buf_trans hsw; member
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| D | intel_display_power_well.h | 83 } hsw; member
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| /drivers/gpu/drm/i915/gt/ |
| D | intel_sseu.c | 31 for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask.hsw); i++) in intel_sseu_subslice_total()
32 total += hweight8(sseu->subslice_mask.hsw[i]); in intel_sseu_subslice_total()
44 return sseu->subslice_mask.hsw[slice]; in intel_sseu_get_hsw_subslices()
54 return sseu->eu_mask.hsw[slice][subslice]; in sseu_get_eus()
66 sseu->eu_mask.hsw[slice][subslice] = eu_mask; in sseu_set_eus()
79 total += hweight16(sseu->eu_mask.hsw[s][ss]); in compute_eu_total()
157 sseu->subslice_mask.hsw[0] = ss_en & valid_ss_mask; in gen11_compute_sseu_info()
348 sseu->subslice_mask.hsw[0] |= BIT(0); in cherryview_sseu_info_init()
359 sseu->subslice_mask.hsw[0] |= BIT(1); in cherryview_sseu_info_init()
416 sseu->subslice_mask.hsw[s] = subslice_mask; in gen9_sseu_info_init()
[all …]
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| D | intel_sseu_debugfs.c | 37 sseu->subslice_mask.hsw[0] |= BIT(ss); in cherryview_sseu_device_status()
88 sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s]; in gen11_sseu_device_status()
143 sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s]; in gen9_sseu_device_status()
153 sseu->subslice_mask.hsw[s] |= BIT(ss); in gen9_sseu_device_status()
180 sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s]; in bdw_sseu_device_status()
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| D | intel_sseu.h | 60 u8 hsw[GEN_MAX_HSW_SLICES]; member
74 u16 hsw[GEN_MAX_HSW_SLICES][GEN_MAX_SS_PER_HSW_SLICE]; member
113 .subslice_mask = sseu->subslice_mask.hsw[0], in intel_sseu_from_device_info()
132 return sseu->subslice_mask.hsw[slice] & BIT(subslice); in intel_sseu_has_subslice()
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| /drivers/gpu/drm/bridge/adv7511/ |
| D | adv7533.c | 31 unsigned int hsw, hfp, hbp, vsw, vfp, vbp; in adv7511_dsi_config_timing_gen() local
34 hsw = mode->hsync_end - mode->hsync_start; in adv7511_dsi_config_timing_gen()
48 regmap_write(adv->regmap_cec, 0x2a, hsw >> 4); in adv7511_dsi_config_timing_gen()
49 regmap_write(adv->regmap_cec, 0x2b, (hsw << 4) & 0xff); in adv7511_dsi_config_timing_gen()
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| /drivers/gpu/drm/i915/gt/shaders/ |
| D | README | 42 ~ $ cp ~/linux/drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm \
43 ~/igt/lib/i915/shaders/clear_kernel/hsw.asm
45 igt $ ./scripts/generate_clear_kernel.sh -g hsw \
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| /drivers/video/fbdev/ |
| D | carminefb.c | 64 u32 hsw; member
107 .hsw = 96,
119 .hsw = 72,
372 u32 hdp, vdp, htp, hsp, hsw, vtr, vsp, vsw; in set_display_parameters() local
382 hsw = par->res->hsw - 1; in set_display_parameters()
393 (hsw << CARMINE_DISP_HSW_SHIFT) | in set_display_parameters()
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| /drivers/gpu/drm/tilcdc/ |
| D | tilcdc_crtc.c | 279 uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw; in tilcdc_crtc_set_mode() local
317 hsw = mode->hsync_end - mode->hsync_start; in tilcdc_crtc_set_mode()
323 mode->hdisplay, mode->vdisplay, hbp, hfp, hsw, vbp, vfp, vsw); in tilcdc_crtc_set_mode()
339 reg |= ((hsw-1) & 0x3c0) << 21; in tilcdc_crtc_set_mode()
346 (((hsw-1) & 0x3f) << 10); in tilcdc_crtc_set_mode()
776 uint32_t hbp, hfp, hsw, vbp, vfp, vsw; in tilcdc_crtc_mode_valid() local
798 hsw = mode->hsync_end - mode->hsync_start; in tilcdc_crtc_mode_valid()
813 if ((hsw-1) & ~0x3ff) { in tilcdc_crtc_mode_valid()
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| /drivers/video/fbdev/omap2/omapfb/dss/ |
| D | hdmi_wp.c | 172 timing_h |= FLD_VAL(timings->hsw, 7, 0); in hdmi_wp_video_config_timing()
194 timings->hsw = param->timings.hsw; in hdmi_wp_init_vid_fmt_timings()
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| D | hdmi5_core.c | 286 video_cfg->v_fc_config.timings.hsw = cfg->timings.hsw - 1; in hdmi_core_init()
290 cfg->timings.hbp + cfg->timings.hsw - 1; in hdmi_core_init()
356 (cfg->v_fc_config.timings.hsw >> 8), 1, 0); in hdmi_core_video_config()
358 cfg->v_fc_config.timings.hsw & 0xFF, 7, 0); in hdmi_core_video_config()
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| D | display.c | 268 ovt->hsw = vm->hsync_len; in videomode_to_omap_video_timings()
301 vm->hsync_len = ovt->hsw; in omap_video_timings_to_videomode()
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| D | display-sysfs.c | 99 t.x_res, t.hfp, t.hbp, t.hsw, in display_timings_show()
124 &t.x_res, &t.hfp, &t.hbp, &t.hsw, in display_timings_store()
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| D | dispc.c | 2115 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width; in check_horiz_timing_omap3()
2122 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk); in check_horiz_timing_omap3()
2973 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp, in _dispc_lcd_timings_ok() argument
2976 if (hsw < 1 || hsw > dispc.feat->sw_max || in _dispc_lcd_timings_ok()
3009 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp, in dispc_mgr_timings_ok()
3018 static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw, in _dispc_mgr_set_lcd_timings() argument
3030 timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) | in _dispc_mgr_set_lcd_timings()
3147 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw, in dispc_mgr_set_timings()
3151 xtot = t.x_res + t.hfp + t.hsw + t.hbp; in dispc_mgr_set_timings()
3159 t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp); in dispc_mgr_set_timings()
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| /drivers/video/fbdev/omap/ |
| D | hwa742.c | 792 int hsw, vsw; in setup_tearsync() local
798 hsw = hwa742_read_reg(HWA742_HS_W_REG); in setup_tearsync()
800 hs_pol_inv = !(hsw & 0x80); in setup_tearsync()
802 hsw = hsw & 0x7f; in setup_tearsync()
858 hs = hsw; in setup_tearsync()
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| D | lcd_palmte.c | 26 .hsw = 4,
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| D | lcd_ams_delta.c | 112 .hsw = 3,
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| D | omapfb.h | 66 int hsw; /* Horizontal synchronization member
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| /drivers/gpu/drm/pl111/ |
| D | pl111_display.c | 133 u32 ppl, hsw, hfp, hbp; in pl111_display_enable() local
148 hsw = mode->hsync_end - mode->hsync_start - 1; in pl111_display_enable()
160 (hsw << 8) | in pl111_display_enable()
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| /drivers/gpu/drm/hisilicon/kirin/ |
| D | dw_drm_dsi.c | 453 u32 hfp, hbp, hsw, vfp, vbp, vsw; in dsi_set_mode_timing() local
481 hsw = mode->hsync_end - mode->hsync_start; in dsi_set_mode_timing()
490 hsa_time = (hsw * lane_byte_clk_kHz) / pixel_clk_kHz; in dsi_set_mode_timing()
507 htot, hfp, hbp, hsw); in dsi_set_mode_timing()
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| /drivers/gpu/drm/mcde/ |
| D | mcde_display.c | 977 u32 hsw, hfp, hbp; in mcde_setup_dpi() local
982 hsw = mode->hsync_end - mode->hsync_start; in mcde_setup_dpi()
992 hsw, hfp, hbp, vsw, vfp, vbp); in mcde_setup_dpi()
1049 val = ((hsw - 1) << MCDE_TVLBALW_LBW_SHIFT); in mcde_setup_dpi()
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| /drivers/gpu/drm/tegra/ |
| D | dsi.c | 481 unsigned int hact, hsw, hbp, hfp, i, mul, div; in tegra_dsi_configure() local
542 hsw = (mode->hsync_end - mode->hsync_start) * mul / div; in tegra_dsi_configure()
548 hbp += hsw; in tegra_dsi_configure()
554 hsw -= 10; in tegra_dsi_configure()
558 tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1); in tegra_dsi_configure()
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