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Searched refs:hwsp_seqno (Results 1 – 15 of 15) sorted by relevance

/drivers/gpu/drm/i915/gt/
Dintel_timeline.c69 timeline->hwsp_seqno = memset(vaddr + ofs, 0, TIMELINE_SEQNO_BYTES); in intel_timeline_pin_map()
97 timeline->hwsp_seqno = (void *)(long)timeline->hwsp_offset; in intel_timeline_init()
225 u32 *hwsp_seqno = (u32 *)tl->hwsp_seqno; in intel_timeline_reset_seqno() local
229 memset(hwsp_seqno + 1, 0, TIMELINE_SEQNO_BYTES - sizeof(*hwsp_seqno)); in intel_timeline_reset_seqno()
230 WRITE_ONCE(*hwsp_seqno, tl->seqno); in intel_timeline_reset_seqno()
231 drm_clflush_virt_range(hwsp_seqno, TIMELINE_SEQNO_BYTES); in intel_timeline_reset_seqno()
318 tl->hwsp_seqno = tl->hwsp_map + next_ofs; in __intel_timeline_get_seqno()
322 GEM_BUG_ON(i915_seqno_passed(*tl->hwsp_seqno, *seqno)); in __intel_timeline_get_seqno()
355 offset_in_page(from->hwsp_seqno); in intel_timeline_read_hwsp()
456 *tl->hwsp_seqno, tl->seqno); in intel_gt_show_timelines()
Dselftest_timeline.c496 if (READ_ONCE(*tl->hwsp_seqno) != tl->seqno) { in checked_tl_write()
498 *tl->hwsp_seqno, tl->seqno); in checked_tl_write()
584 if (!err && READ_ONCE(*tl->hwsp_seqno) != n) { in live_hwsp_engine()
586 n, tl->fence_context, tl->hwsp_offset, *tl->hwsp_seqno); in live_hwsp_engine()
656 if (!err && READ_ONCE(*tl->hwsp_seqno) != n) { in live_hwsp_alternate()
658 n, tl->fence_context, tl->hwsp_offset, *tl->hwsp_seqno); in live_hwsp_alternate()
695 const u32 *hwsp_seqno[2]; in live_hwsp_wrap() local
725 hwsp_seqno[0] = tl->hwsp_seqno; in live_hwsp_wrap()
742 hwsp_seqno[1] = tl->hwsp_seqno; in live_hwsp_wrap()
746 GEM_BUG_ON(hwsp_seqno[0] == hwsp_seqno[1]); in live_hwsp_wrap()
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Dselftest_engine_cs.c200 cycles[i] = rq->hwsp_seqno[3] - rq->hwsp_seqno[2]; in perf_mi_bb_start()
355 (rq->hwsp_seqno[4] - rq->hwsp_seqno[3]) - in perf_mi_noop()
356 (rq->hwsp_seqno[3] - rq->hwsp_seqno[2]); in perf_mi_noop()
Dintel_engine_pm.c85 READ_ONCE(*ce->timeline->hwsp_seqno), in __engine_unpark()
88 READ_ONCE(*ce->timeline->hwsp_seqno)); in __engine_unpark()
Dintel_timeline_types.h47 const u32 *hwsp_seqno; member
Dgen6_engine_cs.c378 GEM_BUG_ON(offset_in_page(rq->hwsp_seqno) != I915_GEM_HWS_SEQNO_ADDR); in gen6_emit_breadcrumb_xcs()
398 GEM_BUG_ON(offset_in_page(rq->hwsp_seqno) != I915_GEM_HWS_SEQNO_ADDR); in gen7_emit_breadcrumb_xcs()
Dselftest_rc6.c152 result = rq->hwsp_seqno + 2; in __live_rc6_ctx()
Dgen2_engine_cs.c148 GEM_BUG_ON(offset_in_page(rq->hwsp_seqno) != I915_GEM_HWS_SEQNO_ADDR); in __gen2_emit_breadcrumb()
Dintel_engine_cs.c1362 frame->rq.hwsp_seqno = ce->timeline->hwsp_seqno; in measure_breadcrumb_dw()
2028 hwsp_seqno(rq), in print_ring()
Dgen8_engine_cs.c433 return page_mask_bits(tl->hwsp_offset) + offset_in_page(rq->hwsp_seqno); in hwsp_offset()
Dintel_execlists_submission.c1987 hwsp_seqno(rq)); in process_csb()
/drivers/gpu/drm/i915/
Di915_request.h68 hwsp_seqno(rq__), ##__VA_ARGS__); \
278 const u32 *hwsp_seqno; member
486 const u32 *hwsp = READ_ONCE(rq->hwsp_seqno); in __hwsp_seqno()
504 static inline u32 hwsp_seqno(const struct i915_request *rq) in hwsp_seqno() function
629 WRITE_ONCE(rq->hwsp_seqno, /* decouple from HWSP */ in i915_request_mark_complete()
697 u32 hwsp_relative_offset = offset_in_page(rq->hwsp_seqno); in i915_request_active_seqno()
Di915_gpu_error.h112 u32 hwsp_seqno; member
Di915_gpu_error.c508 err_printf(m, " context timeline seqno %u\n", ctx->hwsp_seqno); in error_print_context()
1410 e->hwsp_seqno = (ce->timeline && ce->timeline->hwsp_seqno) ? in record_context()
1411 *ce->timeline->hwsp_seqno : ~0U; in record_context()
Di915_request.c960 rq->hwsp_seqno = tl->hwsp_seqno; in __i915_request_create()