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Searched refs:i915_mcr_reg_t (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/i915/gt/
Dintel_gt_mcr.h16 i915_mcr_reg_t reg,
18 u32 intel_gt_mcr_read_any_fw(struct intel_gt *gt, i915_mcr_reg_t reg);
19 u32 intel_gt_mcr_read_any(struct intel_gt *gt, i915_mcr_reg_t reg);
22 i915_mcr_reg_t reg, u32 value,
25 i915_mcr_reg_t reg, u32 value);
27 i915_mcr_reg_t reg, u32 value);
29 u32 intel_gt_mcr_multicast_rmw(struct intel_gt *gt, i915_mcr_reg_t reg,
33 i915_mcr_reg_t reg,
43 i915_mcr_reg_t reg,
Dintel_gt_mcr.c224 static i915_reg_t mcr_reg_cast(const i915_mcr_reg_t mcr) in mcr_reg_cast()
246 i915_mcr_reg_t reg, u8 rw_flag, in rw_with_mcr_steering_fw()
323 i915_mcr_reg_t reg, u8 rw_flag, in rw_with_mcr_steering()
454 i915_mcr_reg_t reg, in intel_gt_mcr_read()
473 void intel_gt_mcr_unicast_write(struct intel_gt *gt, i915_mcr_reg_t reg, u32 value, in intel_gt_mcr_unicast_write()
490 i915_mcr_reg_t reg, u32 value) in intel_gt_mcr_multicast_write()
521 void intel_gt_mcr_multicast_write_fw(struct intel_gt *gt, i915_mcr_reg_t reg, u32 value) in intel_gt_mcr_multicast_write_fw()
555 u32 intel_gt_mcr_multicast_rmw(struct intel_gt *gt, i915_mcr_reg_t reg, in intel_gt_mcr_multicast_rmw()
580 i915_mcr_reg_t reg, in reg_needs_read_steering()
680 i915_mcr_reg_t reg, in intel_gt_mcr_get_nonterminated_steering()
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Dintel_workarounds_types.h18 i915_mcr_reg_t mcr_reg;
Dintel_workarounds.c228 static void wa_mcr_add(struct i915_wa_list *wal, i915_mcr_reg_t reg, in wa_mcr_add()
250 wa_mcr_write_clr_set(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clear, u32 set) in wa_mcr_write_clr_set()
262 wa_mcr_write(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 set) in wa_mcr_write()
274 wa_mcr_write_or(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 set) in wa_mcr_write_or()
286 wa_mcr_write_clr(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clr) in wa_mcr_write_clr()
309 wa_mcr_masked_en(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val) in wa_mcr_masked_en()
321 wa_mcr_masked_dis(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val) in wa_mcr_masked_dis()
334 wa_mcr_masked_field_set(struct i915_wa_list *wal, i915_mcr_reg_t reg, in wa_mcr_masked_field_set()
1922 whitelist_mcr_reg_ext(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 flags) in whitelist_mcr_reg_ext()
1946 whitelist_mcr_reg(struct i915_wa_list *wal, i915_mcr_reg_t reg) in whitelist_mcr_reg()
Dintel_engine_types.h350 i915_mcr_reg_t mcr_reg;
/drivers/gpu/drm/i915/
Di915_reg_defs.h271 } i915_mcr_reg_t; typedef
273 #define MCR_REG(offset) ((const i915_mcr_reg_t){ .reg = (offset) })
283 _Generic((r), i915_reg_t: (r).reg, i915_mcr_reg_t: (r).reg)
/drivers/gpu/drm/i915/gt/uc/
Dintel_guc_ads.c332 i915_mcr_reg_t reg, u32 flags) in guc_mcr_reg_add()
Dintel_guc_capture.c254 i915_mcr_reg_t reg;